Si2 Member Report 2008

Transcription

1 Si2 Member Report 2008 Innovation Through Collaboration

2 Board of Directors Term AMD Ward Vercruysse Director CAD/ AMD Fellow ARM John Goodenough Director, Design Technology Cadence Design Systems Ted Vucurevich CTO IBM Dr Leon Stok Director, EDA Intel Rahul Goyal Director, EDA Business LSI Ameesh Desai Senior Director, Design Tools & Methodology Si2 BOD Chair National Semiconductor James Lin VP Technology Infrastructure Group NXP Semiconductors Barry Dennington Senior VP, Design Technology Sequence Design Vic Kulkarni President & CEO Synopsys John Chilton Sr. VP & General Manager Si2 Steve Schulz President & CEO

3 Letter from the Chairman Ameesh Desai - LSI Senior Director, Design Tools & Methodology Si2 Board of Directors Chair As a key fabless Semiconductor supplier in the storage and networking markets, LSI is committed to delivering environmentally friendly, highly efficient products/services that both have a positive green impact and offer economic benefits to our customers. Green awareness and action inspire the highest levels of participation across our organization. Our investment will minimize the environmental impact of our own company and help us to develop products that reduce energy usage and costs for our customers. Of course, 2008 was a challenging year in the Semiconductor and EDA industry. With reduced resources available to meet these new "green" challenges, as well as decreasing node sizes coupled with more complex functionality on-chip, it has been ever-more critical to take advantage of shared industry efforts which are dedicated to solving common problems faced by all semiconductor designers. Challenges such as comprehensive top-to-bottom low-power design flows, interoperability of design tools, and design methods which enable accurate manufacturability are all examples of the projects which Si2, in teamwork with its member companies, are currently working on. The shared infrastructure model championed by Si2 enables the brightest minds from the leading Semiconductor and EDA companies to collaborate together to solve real engineering problems. Si2 does not just write standards and get them approved. Member companies dedicate significant engineering resources as well as solid technology donations to achieve the roadmap goals of each Si2 coalition. The dedicated Si2 engineering staff works with the member companies to ensure that technology donations are modified as necessary to meet not only the goals of the approved standard requirements, but are also capable of being adopted by the entire industry. Furthermore, Si2 provides the anti-trust and strong Intellectual Property protection umbrellas which ensure that the solutions developed are "safe" in today's business climate. As Chair of Si2's Board of Directors, it is my goal to help nurture these activities and, working with the other Board Members, provide a solid platform of leading industry support behind Si2 projects. The Si2 bylaws ensure that the Board places priority on the semiconductor/ip end-users of EDA design tools, while including not only strong EDA representation, but exposure to smaller start-up companies as well. I am proud to work alongside the Board members you see on the preceding pages, and look forward to making progress on the challenges we see in I encourage current Si2 members to become more deeply involved in the many technical activities being pursued in the Coalition Working Groups, and of course, encourage nonmembers to come join our efforts and get your voice heard as Si2 addresses critical industry needs. - AD -

4 President s Message Si2 Steve Schulz, President & CEO By all accounts, we can expect that history will remember 2008 as the "year of reckoning" on the hazards of complex financial derivatives and aggressive sub-prime lending, rather than on the significant technology innovation that occurred. Nonetheless, our industry made strong technological advancements during 2008, including important progress toward Si2's mission through the dedicated work of our members. Furthermore, despite the many macroeconomic challenges that worsened throughout the year, Si2 retained its healthy fund balance position at 2007 levels. I credit this result to a recognition of the strong fundamental value proposition Si2 offers to the strategic capability and efficiency of our industry proved to be a solid year of excellent technical innovation and continued market adoption progress on virtually all fronts at Si2, thanks to the passionate and dedicated working group members that made it possible. During the year, OpenAccess continued to lead the industry forward in interoperable design flows with new commercial adoption from both small and large EDA vendors alike, reflected in a Summer 2008 Design Automation Conference event that one industry observer labeled "the OpenAccess DAC". In addition to numerous end-user production flow adoptions using OpenAccess, 2008 also saw momentum build for another external industry effort (IPL) that builds upon OpenAccess, gaining major foundry support as testament to the role of enabling standards infrastructure in creating new opportunities. The Coalition thus turned its focus toward new processes and structures to prepare OpenAccess for its next phase of growth ahead. The DFM Coalition hit its stride in 2008, with eight technology contributions from an impressive membership. One contribution (courtesy Mentor Graphics) is resulting in a new emerging standard (icheck) for describing vendor-independent, interoperable DRC and DFM rule checks. DFMC members also embraced a new upcoming standard API that promises to enable multivendor DFM hotspot detection, avoidance, and repair. The DFMC also released a DFM Glossary of nearly 250 physical and electrical parameters, in precise detail, that must be communicated between design and manufacturing, which prepares the way for development of a DFM library standard to come. The Low-Power Coalition had a very productive year. Si2's Common Power Format (CPF) v1.1 was developed and released, incorporating over 100 pages of enhancements to the popular CPF 1.0 in the areas of memory modeling, hierarchy, and IP reuse. The LPC also released an ESL-to-GDSII power closure reference flow, power stimulus reduction guide, and industry glossary of low-power terminology in One new adoption aid, an interactive CPF Relational Analyzer, organizes and displays low-power intent for a design based on any number of CPF input files. Other aids include a CPF parser, CPF v1.1 Pocket Guide, and audio/video tutorial in three languages. Modeling of advanced physical and electrical effects continue to increase in complexity, as physical and electrical variations become more context-sensitive. The Open Modeling Coalition delivered significant technology development toward a new open architecture (OMCI) to support these physics realities, blending dynamic and static methods seamlessly to address modeling and characterization across various domains such as timing, power, and DFM. Recognizing the need for a unified industry approach, the OMC also demonstrated leadership with a landmark document on statistical methods including definition of terms, understanding the use of statistics in IC design, case studies, and more may well see continued propagation - and deepening - of the economic woes that rose to the forefront during Yet the best strategy in such times, as always, is to leverage these times as a launching point for new paradigms and new opportunities, fresh solutions to existing challenges, and increased efficiency in all that we do. Strategic, selective investments in collaborative R&D efforts that can enable new growth, such as key standardization efforts, offer "1/N" shared expense leverage and the promise of 100x return on investment for the future. In good times and bad, we appreciate the leadership demonstrated by our members. Thank you for your contributions to our shared success in Sincerely, Steven E. Schulz

5 OpenAccess Coalition The OpenAccess Coalition is a community-driven initiative formed to enable the creation of tightly integrated flows involving best-in-class commercial and proprietary tools and intellectual property, necessary to support design of today s complex chips. This is done through an open-standard data-access interface (API) and reference database implementation supporting that API. OpenAccess is on a successful adoption track and we expect to see many more contributions to the OpenAccess Eco-system and the popular usage of those contributions in In 2009 we will produce the first draft of recommendations for more powerful parasitic modeling using OpenAccess. With all major vendors supporting OpenAccess in one application space or another, 2009 will be an exciting year for the industry in terms of interoperability. Major Accomplishments One major release each of the Data Model 3 and 4 OA streams, multiple monthly source code releases for bug fixes, and the first beta release of Change Tracking Debug Working Group: Upgraded oadebug tool and provided demos at DAC 2008 and 2 OA Conferences, released OA Diff technology Parasitics Working Group: Currently identifying impact of parasitic handling on overall design flow Contributions Working Group: General contributions process in use, Contributions web site established, contributed utilities include: Si2 OpenAccess Tutorial, Si2 OpenAccess Debug, Analog Symbol Library, Si2Delta, Ciranova PCell Caching, and Synopsys oaviewer Contributions Reuse Library established OpenAccess Coalition Members Advanced Micro Devices AnaGlobe Technology, Inc. Applied Wave Research, Inc. Atrenta Blaze DFM Cadence Design Systems Ciranova D2S, Inc. Dolphin Integration Entasys Design Gradient Design Automation Hewlett-Packard IBM Corporation IC Manage Intel Corporation Jedat LSI Corporation Magma Design Automation MatrixOne Mentor Graphics Micro Magic, Inc. Nangate A/S NXP Semiconductors Pulsic Limited Pyxis Technology Renesas Technology Corp. Sagantec SoftJin Technologies SpringSoft, Inc Sun Microsystems Synopsys Teklatech A/S Tektronix

6 OpenAccess Success Story System Design (User Interface) Function Blocks C Level designs Renesas Prototyping Environment System Spec. Black Box RTL Area Timing Power Prototyping Logical-Physical Collaboration Netlist Floorplan SDC Path Analysis Design Topology Wire/hierarchy OpenAccess v2.2 or later Physical Design (background method) Generate FP Path Analysis Layer/Area Renesas Prototyping Environment Tr. Level Library

7 Open Modeling Coalition The Open Modeling Coalition (OMC) was formed in mid-2005 to address critical issues - such as accuracy, consistency, security, and process variations - in the characterization and modeling of libraries and IP blocks used for the design of integrated circuits. The OMC is developing an Open Modeling Common Interface (OMCI) that will seamlessly blend static and dynamic model representations for presentation to applications in conjunction with the OpenAccess database will see the first real world usage of the interface will also see the first release of a common Characterization and Validation Reference Flow. Statistical design techniques are also being advanced and will be reported on in Major Accomplishments Joint Data Model (JDM) Working Group: Open Modeling Calculation Interface (OMCI) developed by the JDM WG in partnership with the OAC, successful OMCI demos at DAC 2008 and Fall 2008 OpenAccess+ Conference, developed ability to handle mix of Liberty-based models and IEEE1481-based dynamic models Statistical Working Group: Published the "Statistical Design Methodology" document Characterization and Validation Working Group: Developed a recommended Characterization Setup document Open 45nm Library: In conjunction with Si2 and North Carolina State University, Nangate built and contributed an open standard cell library (including SPICE net-lists and OA views) This library uses the openpdk developed by Prof. Rhett Davis at NC State through research project partially funded by Si2 Open Modeling Coalition Members Altos Design Automation ARM Cadence Design Systems Fenix Design Automation IBM Corporation IMEC Nangate A/S NXP Semiconductors Renesas Technology Corp.

8 Low Power Coalition The Low-Power Coalition (LPC) will deliver enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. The LPC is steadily making the required advances for electronic circuits and systems to consume less power per function. Work is being done to aid in automating many of the steps along the tool chain, to that end, a draft data model and associated Application Procedural Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model. In addition, enhancements have been made to extend the Common Power Format (CPF) and CPF 1.2 is planned for release in Q4 of Modeling requirements for power are being developed and draft requirements are expected in 2009 Major Accomplishments Wide acceptance of CPF 1.0 with many tape-outs completed to-date using CPF-based flows, 100+ designs world-wide currently using CPF Contributions include: CPF 1.1 released as an Si2 Standard in September 2008, CPF 1.1 Pocket Programmer's Guide, CPF 1.0 Pocket Programmer's Guide, CPF 1.1 Beta Parser, CPF 1.0 Relational Analyzer, Online CPF 1.0 tutorial (available in English, Japanese and Mandarin) posted Flow Working Group: Published a complete Power-Aware Reference Flow from ESL through Implementation stage of design including power closure points in the flow, published a set of recommended low power design techniques for design flow steps Data Model and API Working Group: Approved and published the Low Power Glossary Format Working Group: Published a Format Requirements Document in February, 2008, released CPF 1.1 open standard and published the CPF 1.2 Roadmap in September, 2008 Low Power Coalition Members Advanced Micro Devices ARM Atrenta Cadence Design Systems Calypto Design Systems, Inc. Entasys Design Envis Corporation Global Unichip Corporation IBM Corporation LSI Corporation NXP Semiconductors Sequence Design, Inc. Virage Logic

9 Design for Manufacturability Coalition The subject of Design for Manufacturing is rushing to the forefront of the list of challenges in the Semiconductor and EDA industries. Few standards exist for DFM but they are critical for reducing product cost and time to market. The DFMC is establishing common DFM Terminology and a roadmap for developing interface standards between implementation, verification and analysis tools to improve functional and parametric yield. The DFMC is developing a language called icheck that describes a comprehensive set of DFM parameters for Design Rule Checks, Critical Area Analysis, Lithography and Chemical Mechanical Planarization. Silicon foundries use icheck to define the exact conditions required for a DFM hotspot check without describing how to perform the check. The first draft of the icheck specification and a multi-tool, multi-eda vendor and multi-foundry demonstration flow built on the icheck infrastructure will be released in Major Accomplishments The DFMC has defined icheck, based on a contribution from Mentor Graphics, which is an EDA vendor neutral and silicon foundry independent high level language to describe DFM checks that include; Design Rule Checks, Critical Area Analysis, Litho Checks, CMP checks and Routing Reliability. The icheck parser extracts and validates DFM parameters which are then used in the native language rule decks to verify Design for Manufacturability for a specific foundry The icheck parser uses a standard plug-in architecture so different rule formatters can be easily added. Rule formatters currently exist for Calibre DRC, Calibre LFD, Hercules and XML with plug-ins for additional verification languages coming soon The icheck parser handles both encrypted rules and plain text rules. The decrypted rules are only available to the DFM application since the icheck parser is embedded into the DFM application as a front-end translator from icheck rules into native format rules The DFMC has a new working group to complete the specification on the icheck language, the parser and the plug-in interface. A reference implementation and inter company demo of DFMC hotspot analysis, avoidance and repair will be given at DAC Developed and released a DFM Dictionary/Wiki which contains over 200 parameter definitions that will be used by DFM models, engines and tools Design for ManufacturabilityCoalition Members Cadence Design Systems IBM Corporation Infineon Technologies Mentor Graphics Pyxis Technology Sagantec Samsung Electronics Co., Ltd. STARC Takumi Technology Texas Instruments UMC

10 Executive Team Sumit DasGupta Sr. Vice President of Engineering Sumit DasGupta joined Si2 in 2002 as Vice President of Technology. As Vice President of Technology, he is responsible for Si2 engineering and service projects, with a special emphasis on OpenAccess. DasGupta comes to Si2 from Motorola, where he served as director of SoC and IP design systems in the semiconductor products sector. While at Motorola, DasGupta served on the Si2 Board of Directors and the Design Technology Council. Prior to Motorola, he worked at IBM in several management and technical positions. DasGupta holds a Ph.D. in computer science from Syracuse University and a master's degree in electrical engineering from Marquette University. He has eight patents and 20 publications to his name. Frank Childers Vice President, Business Development Frank Childers is responsible for the advancement and adoption of integration and collaboration business models across the Si2 member base. The business focus and related value proposition of each Si2 coalition requires operational management to ensure relevance, adoption and clarity of business results and ROI. Frank is a veteran of the EDA and electronics industries, having served in numerous sales, marketing and general management positions throughout his twenty five year career. His EDA experience includes Magma, Mentor, Nascentric and Silicon Metrics. He studied engineering at the US Air Force Academy and graduated with a bachelor of science degree. Jake Buurma VP, West Coast Operations Jake Buurma currently serves as VP of West Coast Operations for Si2. Mr. Buurma has more than 33 years of industry experience equally split between the design of integrated circuits at major semiconductor companies such as National Semiconductor and Toshiba Semiconductor and developing EDA software at companies such as Cadence Design Systems, Silicon Navigator and Aprio. Jake has worked extensively with global development teams in automated physical design, EDA software development and improving Design for Manufacturability (DFM) at sub-100nm process nodes.jake was a founding board member of the Virtual Socket Interface Alliance (VSIA) and he was the General Chairman of the Custom Integrated Circuit Conference (CICC). He has authored over 100 papers in technical conferences and engineering journals, he was a contributing author in the book Talking Chips, and the recipient of three patents in Analog and Digital Circuit Design. Mr. Buurma received his M.S.E.E. degree from Santa Clara University and graduated cum laude with a global MBA from Duke University Nick English - Vice President of Development As an experienced senior manager, Nick English is known for managing both business and technical processes that affect electronic design. He has over 25 years of high-technology industry experience in both engineering and management roles. He has previously served as the chair and the key driver of the OpenKit Initiative within Accellera to create standards for the semiconductor industry s process design kits. Over the last twenty years Nick has held senior management positions in semiconductor, EDA, and software companies. As an engineer he worked in the areas of statistical device modeling at the transistor level. He holds a BSEE and MSEE from the University of South Florida.

11 Membership Profile Si2 Membership Composition Total IDM: Total EDA: Total Fabless: Total IP: Total Mask: Total Equipment: Total Exchange: Sources of Si2 Funding End-User Funding EDA/Other Funding While the majority of the Si2 membership is EDA vendors, the majority of the funding and leasership comes from end-user companies. According to the Si2 by-laws, they hold at least 7 out 10 seats on the Board of Directors. All Coalitions are Chaired by an end-user company, and they typically are members of multiple Coalitions.

12 Member List Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world. Abound Logic Advanced Micro Devices Agilent Technologies Altera Altos Design Automation AnaGlobe Technology Analog Rails Anova Solutions Apache Design Solutions Applied Wave Research ARM Artwork Conversion Software Atoptech Atrenta Ausdia Blaze DFM Cadence Design Systems Calypto Design Systems ChipVision Design Systems Ciranova CLK Design Automation Concept Engineering Coupling Wave Solutions D2S Demos on Demand Dolphin Integration easic Corporation edacentrum EDXACT Entasys Design Envis Corporation Ericsson Extreme DA Fastrack Design Fenix Design Automation Global Unichip Corporation Gradient Design Automation Hewlett-Packard Honda Research Institute Japan IBM Corporation IC Manage IMEC In2Fab Infineon Technologies Intel Corporation Jedat Keirex Technology LSI Corporation Magma Design Automation Marvell Semiconductor MatrixOne Mentor Graphics Micro Magic, Inc. Micrologic Design Automation Multiprobe Nangate A/S Nannor Technologies National Semiconductor NXP Semiconductors OCP-IP OEA International ON Semiconductor Pinebush Technologies Pulsic Limited Pyxis Technology R3 Logic, Inc. Renesas Technology Corp. Sagantec Samsung Electronics SEMI Sequence Design, Inc. Shanghai JT-Hyron Software Silicon Frontline Technology SiliconBlue Technologies SoftJin Technologies SpringSoft SRC STARC Stratosphere Solutions Sun Microsystems SynCira Corporation Synopsys Takumi Technology TechOnLine Teklatech A/S Tektronix Tela Innovations TeraRoute LLC Texas Instruments The SPIRIT Consortium UMC Virage Logic