UC Berkeley CS61C : Machine Structures

Transcription

1 inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control Exhausted TA Ben Sussman Qutrits Bring Quantum Computers Closer: An Australian group has built and tested logic gates that convert qubits into qutrits (three-level quantum states)! But who cares: new iphones soon? Ben hopes so CS6C L27 Single-Cycle CPU Control ()

2 Review: A Single Cycle Datapath We have everything except control signals RegDst Rd RegWr busw 5 imm6 npc_sel Rt Rs Rt 5 5 Rw Ra Rb RegFile 6 Extender busa busb instr fetch unit zero Instruction<3:> <2:25> Rs ALUctr = ALU Data In <6:2> Rt MemWr <:5> Rd WrEn Adr <:5> Data Imm6 MemtoReg CS6C L27 Single-Cycle CPU Control (2) ExtOp ALUSrc

3 Recap: Meaning of the Control Signals npc_sel: +4 PC < PC + 4 n =next br PC < PC {SignExt(Im6), } Later in lecture: higher-level connection between mux and branch condition 4 PC Ext Adder Adder npc_sel Mux PC Inst Address CS6C L27 Single-Cycle CPU Control (3) imm6

4 Recap: Meaning of the Control Signals ExtOp: zero, sign ALUsrc: regb; MemWr: write memory MemtoReg: ALU; Mem immed RegDst: rt ; rd ALUctr: ADD, SUB, OR RegWr: write register RegDst RegWr busw Rd 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp Extender busa busb ALUSrc ALUctr MemtoReg MemWr ALU Data In WrEn Adr Data CS6C L27 Single-Cycle CPU Control (4)

5 RTL: The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instructionʼs address CS6C L27 Single-Cycle CPU Control (5)

6 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions Inst Instruction<3:> 4 PC Ext Adder Adder npc_sel PC Mux Inst Address imm6 CS6C L27 Single-Cycle CPU Control (6)

7 The Single Cycle Datapath during Add op rs rt rd shamt funct R[rd] = R[rs] + R[rt] RegDst= Rd RegWr= busw npc_sel=+4 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp=x Extender busa busb instr fetch unit zero 6 ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr=ADD MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (7)

8 Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump Inst 4 PC Ext npc_sel=+4 Adder Adder PC Mux Inst Address imm6 CS6C L27 Single-Cycle CPU Control (8)

9 Single Cycle Datapath during Or Immediate? op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst= Rd RegWr= busw npc_sel= 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp= Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (9)

10 Single Cycle Datapath during Or Immediate? op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst= Rd RegWr= busw npc_sel=+4 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp=zero Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr=OR MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control ()

11 The Single Cycle Datapath during Load? op rs rt immediate R[rt] = Data {R[rs] + SignExt[imm6]} RegDst= Rd RegWr= busw npc_sel= 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp= Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control ()

12 The Single Cycle Datapath during Load op rs rt immediate R[rt] = Data {R[rs] + SignExt[imm6]} RegDst= Rd RegWr= busw npc_sel=+4 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp=sign Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr=ADD MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (2)

13 The Single Cycle Datapath during Store? op rs rt immediate Data {R[rs] + SignExt[imm6]} = R[rt] RegDst= Rd RegWr= busw npc_sel= 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp= Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (3)

14 The Single Cycle Datapath during Store op rs rt immediate Data {R[rs] + SignExt[imm6]} = R[rt] RegDst=x Rd RegWr= busw npc_sel=+4 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp=sign Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr=ADD MemtoReg=x = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (4)

15 The Single Cycle Datapath during Branch? op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst= Rd RegWr= busw npc_sel= 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp= Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (5)

16 The Single Cycle Datapath during Branch op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst=x Rd RegWr= busw npc_sel=br 5 Rt imm6 Rs Rt 5 5 Rw Ra Rb RegFile 6 ExtOp=x Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rt Rd Imm6 ALUctr=SUB MemtoReg=x = ALU Data In <6:2> <:5> MemWr= WrEn Adr <:5> Data CS6C L27 Single-Cycle CPU Control (6)

17 Instruction Fetch Unit at the End of Branch if (Zero == ) then PC = PC SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Zero imm6 4 PC Ext 3 26 op rs rt immediate Adder Adder MUX npc_sel ctrl Mux CS6C L27 Single-Cycle CPU Control (7) 2 Inst PC Adr 6 Instruction<3:> What is encoding of npc_sel? Direct MUX select? Branch inst. / not branch Letʼs pick 2nd option npc_sel zero? MUX x Q: What logic gate?

18 Administrivia Sorry about Proj woes Grading is rough stuff. Donʼt blame Ben, heʼs innocent. HW6 Due imminently! Students have claimed it takes a very long time Remember MODULAR DESIGN. This could save you a lot of time. HW7 Out Now! Get started soon. Proj3 is on its way, will be out soon after the weekend. CS6C L27 Single-Cycle CPU Control (8)

19 Step 4: Given Datapath: RTL Control Instruction<3:> Inst Adr <26:3> Op <:5> Fun Rt <2:25> <:5> <:5> <6:2> Rs Rd Imm6 Control npc_sel RegWrRegDstExtOpALUSrcALUctr MemWr MemtoReg DATA PATH CS6C L27 Single-Cycle CPU Control (9)

20 inst A Summary of the Control Signals (/2) Register Transfer add R[rd] R[rs] + R[rt]; PC PC + 4 ALUsrc = RegB, ALUctr = ADD, RegDst = rd, RegWr, npc_sel = +4 sub R[rd] R[rs] R[rt]; PC PC + 4 ALUsrc = RegB, ALUctr = SUB, RegDst = rd, RegWr, npc_sel = +4 ori R[rt] R[rs] + zero_ext(imm6); PC PC + 4 ALUsrc = Im, Extop = Z,ALUctr = OR, RegDst = rt,regwr, npc_sel = +4 lw R[rt] MEM[ R[rs] + sign_ext(imm6)];pc PC + 4 ALUsrc = Im, Extop = sn, ALUctr = ADD, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 sw MEM[ R[rs] + sign_ext(imm6)] R[rs];PC PC + 4 ALUsrc = Im, Extop = sn, ALUctr = ADD, MemWr, npc_sel = +4 beq if ( R[rs] == R[rt] ) then PC PC + sign_ext(imm6)] else PC PC + 4 npc_sel = br, ALUctr = SUB CS6C L27 Single-Cycle CPU Control (2)

21 A Summary of the Control Signals (2/2) See func We Don t Care :-) Appendix A op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr<2:> x Add x Subtract Or Add x x Add x x x Subtract x x x? x x R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump CS6C L27 Single-Cycle CPU Control (2)

22 Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw npcsel = beq Jump = jump ExtOp = lw + sw ALUctr[] = sub + beq (assume ALUctr is ADD, : SUB, : OR) ALUctr[] = or where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op ~op, ori = ~op 5 ~op 4 op 3 op 2 ~op op lw = op 5 ~op 4 ~op 3 ~op 2 op op sw = op 5 ~op 4 op 3 ~op 2 op op beq = ~op 5 ~op 4 ~op 3 op 2 ~op ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op ~op add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func ~func How do we implement this in gates? CS6C L27 Single-Cycle CPU Control (22)

23 Controller Implementation opcode func AND logic add sub ori lw sw beq jump OR logic RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr[] ALUctr[] CS6C L27 Single-Cycle CPU Control (23)

24 Peer Instruction Instruction<3:> npc_sel Instruction Rd Rt Fetch Unit Clk RegDst Mux Rs Rt Rt Rs Rd Imm6 RegWr ALUctr Zero busa MemWr MemtoReg Rw Ra Rb busw -bit Registers busb Clk WrEn Adr Data In imm6 6 Data Clk ALUSrc Extender ExtOp A. MemToReg=ʻxʼ & ALUctr=ʻsubʼ. SUB or BEQ? B. ALUctr=ʻaddʼ. Which signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C. Donʼt Care signals are useful because we can simplify our PLA personality matrix. F / T? Mux ALU <2:25> <6:2> <:5> <:5> Mux ABC : SRF : SRT 2: SEF 3: SET 4: BRF 5: BRT 6: BEF 7: BET CS6C L27 Single-Cycle CPU Control (24)

25 Summary: Single-cycle Processor 5 steps to design a processor. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Processor Control Input Datapath Output CS6C L27 Single-Cycle CPU Control (25)

26 Bonus slides These are extra slides that used to be included in lecture notes, but have been moved to this, the bonus area to serve as a supplement. The slides will appear in the order they would have in the normal presentation CS6C L27 Single-Cycle CPU Control (26)

27 J-type The Single Cycle Datapath during Jump 3 op Jump= Instruction<3:> npc_sel= Instruction Rd Rt Fetch Unit RegDst = Clk Mux RegWr = Rs Rt ALUctr = Rt Rs Rd Imm6 TA MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb Clk WrEnAdr imm Extender target address New PC = { PC[3..28], target address, } Mux ALUSrc = ALU Data In Clk <2:25> <6:2> Data <:5> jump <:5> Mux <:25> ExtOp = CS6C L27 Single-Cycle CPU Control (27)

28 The Single Cycle Datapath during Jump J-type 3 op Jump= Instruction<3:> npc_sel=? Instruction Rd Rt Fetch Unit RegDst = x Clk Mux RegWr = Rs Rt ALUctr =x Rt Rs Rd Imm6 TA MemtoReg = x busa Zero MemWr = Rw Ra Rb busw -bit Registers busb Clk WrEnAdr imm Extender target address New PC = { PC[3..28], target address, } Mux ALUSrc = x ALU Data In Clk <2:25> <6:2> Data <:5> jump <:5> Mux <:25> ExtOp = x CS6C L27 Single-Cycle CPU Control (28)

29 Instruction Fetch Unit at the End of Jump J-type New PC = { PC[3..28], target address, } Jump npc_sel Zero 3 op Inst Adr target address Instruction<3:> jump npc_mux_sel 4 imm6 Adder Adder Mux PC Clk How do we modify this to account for jumps? CS6C L27 Single-Cycle CPU Control (29)

30 Instruction Fetch Unit at the End of Jump J-type New PC = { PC[3..28], target address, } Jump npc_sel Zero 3 op target address Inst Adr jump Instruction<3:> 4 npc_mux_sel TA 26 Query Can Zero still get asserted? imm6 Adder Adder Mux 4 (MSBs) Mux PC Clk Does npc_sel need to be? If not, what? CS6C L27 Single-Cycle CPU Control (3)