Equipment Market Segmentation

Size: px
Start display at page:

Download "Equipment Market Segmentation"

Transcription

1 Global Economic Symposium Equipment Market Segmentation Robert Wright July 14, 2000

2 Equipment Market Segmentation Static Models Equipment capital - Single Fab Product & Technology node breakout 130nm Equipment Market (# of tools) Cost Resource Model Contributions Modeling Assumptions 200mm Equipment Annual equipment capital $: OIC (asic), LEL (mpu), LEM (dram) Equipment Segmentation 300mm Equipment Annual equipment capital $: OIC, LEL, LEM Equipment Segmentation 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 2

3 130nm 300mm static model (single fab) LEL Fab Equipment Capital Equipment Capital calculation: Required Tools $939,500K Additional Tools $187,900K Installation $169,110K Total Capital $1,296,510K Equipment Group Segmentation Lithography $487M Interconnect $255M Furnace/Implant $ 63M 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 3

4 Equipment Capital per FAB ($M) Product & Technology Node breakout Scenario A (ITRS) Mature Manufacturing Year Technology Node (nm) LEM 200MM MM 1,398 1,653 2,007 LEL 200MM MM 1,297 1,656 1,913 OIC 200MM MM 1,215 1,553 1,733 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 4

5 Cost Resource Model contributions Tool Requiremen Fab Total Product Cost Wafer Cost by Tool Group Wafer Tool ID Tools Capital Product Factor Cost Cost Factor $ CMP_Ins(C)_F 2 5, _Cu_33 Tool Depreciation 1,137 Litho_248 Tool Depreciation 403 CMP_Ins_F 2 5, _Cu_33 Tool Maintenance 398 Litho_248 Tool Maintenance 141 CMP_Met 8 20, _Cu_33 Direct Personnel 151 Litho_248 Tool Leasing 0 CMP_Met_F 1 2, _Cu_33 Indirect Personnel 88 Litho_248 Direct Personnel 30 CVD_Ins(C)_F 3 10, _Cu_33 Direct Space 221 Litho_248 Indirect Personnel 15 CVD_Ins 2 7, _Cu_33 Indirect Space 8 Litho_248 Direct Space 44 CVD_Ins_F 1 3, _Cu_33 Direct Material 662 Tool Sum econmod2 Fab Litho_248 Indirect Space 1 CVD_Ins_Thin 5 12, _Cu_33 Indirect Material 278 Category Factor FY01 Litho_248 Direct Material 37 CVD_Met(C)_F 1 4, _Cu_33 Total Wafer Cost 2,943 Capital (K$) Req d Tools 939,500 Litho_248 Indirect Material 27 CVD_MetW(C)_F 1 4,000 Capital (K$) Add l Tools 187,900 Litho_248 Group Total 698 CVD_Met 7 28,000 Capital (K$) Installation 169,110 CMP Tool Depreciation 39 Dry_Etch(A)_F 2 7,000 Capital (K Total 1,296,510 CMP Tool Maintenance 14 Dry_Etch(C)_F 2 7,000 Space Summary econmod2 Fab Expense (K$ Maintenance 90,756 CMP Tool Leasing 0 Dry_Etch 17 59,500 Category Space Type FY01 Expense (K$ Depreciation 259,302 CMP Direct Personnel 10 Dry_Etch_F 4 14,000 Required (Sq Ft) Clean Room 92,980 Expense (K$ Total 350,058 CMP Indirect Personnel 4 Dry_Strip_F 2 2,000 Required (Sq Ft) Non Clean Room 371,920 CMP Direct Space 15 Dry_Strip 1 1,000 Required (Sq Ft) Non Manufacturing 31,200 CMP Indirect Space 0 Dry_Strip_F 1 1,000 Required (Sq Ft) Total 496,100 CMP Direct Material 0 Dry_Strip_F 4 4,000 Specified (Sq Ft) Clean Room 92,980 CMP Indirect Material 33 Electroplate 5 12,500 Specified (Sq Ft) Non Clean Room 371,920 CMP Group Total 116 Furn_FastRmp_F 4 6,000 Specified (Sq Ft) Non Manufacturing 31,200 Etch Tool Depreciation 106 Furn_Nitr 6 9,000 Specified (Sq Ft) Total 496,100 Etch Tool Maintenance 37 Furn_Nitr_F 2 3,000 Occupancy (Sq Ft) Clean Room 16,272 Etch Tool Leasing 0 Furn_OxAn 8 12,000 Occupancy (Sq Ft) Non Clean Room 18,596 Etch Direct Personnel 12 Furn_OxAn_F 1 1,500 Occupancy (Sq Ft) Non Manufacturing 1,560 Etch Indirect Personnel 9 Furn_Poly_F 2 3,000 Occupancy (K$) Total 36,428 Etch Direct Space 24 Furn_TEOS_F 2 3,000 Capital (K$) Building 395,976 Etch Indirect Space 1 Implant_HiE_F 1 4,000 Depreciation (K$) Building 15,839 Etch Direct Material 0 Implant_LoE_F 3 9,000 Etch Indirect Material 39 Insp_PLY 7 24,500 Etch Group Total /19/2000 5:09 PM j:\stndpres\template\intst.ppt - 5

6 Wafer Cost $ Product & Technology Node breakout Mature Manufacturing Year Technology Node (nm) LEM 200MM 1,331 1,647 1,682 1, MM 3,008 3,418 3,956 LEL 200MM 1,395 1,564 1,682 2, MM 2,943 3,562 3,998 OIC 200MM 1,404 1,690 1,847 2, MM 2,963 3,677 4,077 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 6

7 Fab Equipment Demand 130nm LEL Scenario A NEW Fabs UPGRADE UPGRADE _Cu_33 Capital Expense per year 4,549,640 6,423,129 7,680,562 7,149,038 9,798,234 2,196,956 Tool Requirements Tools by Cumulative Tool ID FAB Capital CMP_Ins(C)_F CMP_Ins_F CMP_Met CMP_Met_F CVD_Ins(C)_F CVD_Ins CVD_Ins_F CVD_Ins_Thin CVD_Met(C)_F CVD_MetW(C)_F CVD_Met Dry_Etch(A)_F Dry_Etch(C)_F Dry_Etch Dry_Etch_F Dry_Strip_F Dry_Strip /19/2000 5:09 PM j:\stndpres\template\intst.ppt - 7

8 130nm 300mm LEL Scenario A Equipment Market Segmentation Tool Demand - All Fabs Time CMP CVD Etch/Strip Electroplate Furnace Implant Inspect Lithography LowK_Track Measure RTP 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 8

9 Process Complexity Node, nm Logic product Interconnect - Technology Al Cu / oxide Cu / low k Cu / low k Cu / low k - # of levels # mask levels - FEOL Interconnect # mask levels - I-Line DUV DUV DUV # mask levels - Total % increase 11% 10% 17% 7% 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 9

10 Lithography Model Assumptions Tool Purchase Cost ($M) Tool Throughput 200mm 300mm 200mm 300mm I-Line Mask Purchase Cost ($K) Modeled tpt is degraded Mask Life (Wafers per Mask) 157 Critical 40 LEL 4, Binary 30 OIC Critical 28 LEM 10, Binary Critical Binary 11 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 10

11 200mm Equipment Capital Scenario A All Products New & Upgrades 40,000 Equipment Capital ($M) 35,000 30,000 25,000 20,000 15,000 10,000 5, Time 250nm 180nm 130nm 100nm 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 11

12 200mm Equipment Market, Capital $ Scenario A, 130nm LEL Year 2003 (Degraded Case-Litho) 6% CVD / PVD Etch / Strip 2% 41% Furnace/RTP 6% Implant Inspection 12% 1% Lithography LowK Track 21% 6% 4% 1% Measure Test Wet Clean 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 12

13 200mm Equipment Capital Scenario B All Products New & Upgrades Equipment Capital ($M) 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5, Time 250nm 180nm 130nm 100nm 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 13

14 300mm Equipment Capital by year ($M) Scenario A node (nm) LEL 130 4,550 6,423 7,681 7,149 9,798 2, ,647 21,245 22,685 LEM 130 6,758 9,938 9,667 3,294 5, ,754 29,831 22,598 OIC ,252 1,784 5,366 6, ,693 Total 11,308 16,362 19,600 46,628 71,335 61,091 Equipment ($M) 80,000 70,000 60,000 50,000 40,000 30,000 20,000 10, OIC 100 OIC 130 LEM 100 LEM 130 LEL 100 LEL /19/2000 5:09 PM j:\stndpres\template\intst.ppt - 14

15 300mm Equipment Market, Capital $ Scenario A, 130nm LEL Year 2005 (Degraded Case-Litho) CVD / PVD 4% 1% 5% 52% Etch / Strip Furnace/RTP Implant Inspection Lithography 10% 16% 6% 1% 3% 2% LowK Track Measure Test Wet Clean 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 15

16 300mm Equipment Market, Capital $ Scenario A, 130nm LEL Year 2005 (Base Case Litho throughput) CVD / PVD 16% 8% 2% 6% 24% Etch / Strip Furnace/RTP Implant Inspection Lithography 26% 9% 2% 4% 3% LowK Track Measure Test Wet Clean 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 16

17 300mm Equipment Capital by year ($M) Scenario B 100,000 90,000 Equipment Capital ($M) 80,000 70,000 60,000 50,000 40,000 30,000 20,000 10, OIC 70 OIC 100 OIC 130 LEM 70 LEM 100 LEM 130 LEL 70 LEL 100 LEL 130 Time 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 17

18 300mm Equipment Market, Capital $ Scenario B, 130nm Year 2005 (Degraded Case-Litho) 100% Clean Test % of Capital by Tool Group 80% 60% 40% 20% 0% LEL LEM OIC Product RTP PVD Metrology LowK_Track Lithography Inspect Implant Furnace Electroplate Etch / Strip CVD CMP 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 18

19 Summary Analysis limited to time period of Some trends are not fully developed during this range Cost Resource Model provides the capability to create equipment profiles in a static environment Dynamic simulation is needed to model factory effects over time The Segmentation Model provides new equipment requirements and markets for multiple technology nodes, products and wafer sizes. 07/19/2000 5:09 PM j:\stndpres\template\intst.ppt - 19

ISMI Industry Productivity Driver

ISMI Industry Productivity Driver SEMATECH Symposium Taiwan September 7, 2010 Accelerating Manufacturing Productivity ISMI Industry Productivity Driver Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,

More information

Semiconductor Manufacturing Market Outlook: Fundamentals Point to Growth

Semiconductor Manufacturing Market Outlook: Fundamentals Point to Growth Semiconductor Manufacturing Market Outlook: Fundamentals Point to Growth 3Q03 Semiconductor and Electronics Manufacturing Forecast San Jose, California 8 July 2003 Presenters: Klaus-Dieter Rinnen Mary

More information

Applications for Mapper technology Bert Jan Kampherbeek

Applications for Mapper technology Bert Jan Kampherbeek Applications for Mapper technology Bert Jan Kampherbeek Co-founder & CEO Today s agenda Mapper technology Principles of operation Development status and performance Specification summary Mapper applications

More information

Innovation Leadership in Expanding Markets

Innovation Leadership in Expanding Markets Innovation Leadership in Expanding Markets Gary Dickerson CEO and President SEPTEMBER 27, 2017 External Use Forward-Looking Statements and Other Information This presentation contains forward-looking statements,

More information

Bank of America S-MID Cap Conference Boston, MA. March 26,2008

Bank of America S-MID Cap Conference Boston, MA. March 26,2008 Bank of America S-MID Cap Conference Boston, MA March 26,2008 Safe Harbor Statement Safe Harbor Statement under the U.S. Private Securities Litigation Reform Act of 1995; certain matters in this presentation,

More information

FBR Capital Markets 12 th Annual Spring Investor Conference

FBR Capital Markets 12 th Annual Spring Investor Conference FBR Capital Markets 12 th Annual Spring Investor Conference ASML continues to execute its leadership strategy Craig De Young VP Investor Relations and Corporate Communications New York City - May 28-29,

More information

반도체공정 - 김원정. Lattice constant (Å)

반도체공정 - 김원정. Lattice constant (Å) 반도체물리 - 반도체공정 - 김원정 Semiconductors Lattice constant (Å) 1 PN junction Transistor 2 Integrated circuit Integrated circuit originally referred to a miniaturized electronic circuit consisting of semiconductor

More information

B. Riley & Co. 16 th Annual Investor Conference. Jeffrey Andreson, CFO

B. Riley & Co. 16 th Annual Investor Conference. Jeffrey Andreson, CFO B. Riley & Co. 16 th Annual Investor Conference Jeffrey Andreson, CFO May 2015 Forward-Looking Statements This communication contains forward-looking statements within the meaning of the safe harbor provisions

More information

CMP Users Group 450mm Technology Development

CMP Users Group 450mm Technology Development CMP Users Group 450mm Technology Development June 9, 2014 Key Messages Development Continues with all Suppliers Technical Results are Excellent with a Few Capabilities Identified as Challenges Wafer Supply

More information

Intel Corporation Silicon Technology Review

Intel Corporation Silicon Technology Review Intel Corporation Silicon Technology Review Ken David Director, Components Research SEMI Strategic Business Conference April 2003 Agenda Corporate Mission Leadership in Technology Leadership in Integration

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules EE 432 VLSI Modeling and Design 2 CMOS Fabrication

More information

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends EE24 - Spring 2008 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday 2-3pm 2 CMOS Scaling Rules Voltage, V

More information

3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA

3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA 3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion

More information

SEMI Networking Day Italy

SEMI Networking Day Italy SEMI Networking Day Italy 20 th September 2012 proven technology for a new world OEM Group Today Who we are OEM Group is a global company that serves both traditional semiconductor fabs, as well as emerging

More information

G450C Briefing and Supply Chain Collaboration on 450mm Transition. SEMI Northeast Forum Sept. 11,2013

G450C Briefing and Supply Chain Collaboration on 450mm Transition. SEMI Northeast Forum Sept. 11,2013 G450C Briefing and Supply Chain Collaboration on 450mm Transition SEMI Northeast Forum Sept. 11,2013 G450C Background Building 450mm wafer / equipment development environment Consists of 5 member companies

More information

CMOS TECHNOLOGY- Chapter 2 in the Text

CMOS TECHNOLOGY- Chapter 2 in the Text CMOS TECHOLOGY- Chapter 2 in the Text CMOS Technology- Chapter 2 We will describe a modern CMOS process flow. In the simplest CMOS technologies, we need to realize simply MOS and MOS transistors for circuits

More information

Behavioral modeling of crosswafer chip-to-chip process induced non-uniformity. W. CLARK COVENTOR, Villebon sur Yvette, France

Behavioral modeling of crosswafer chip-to-chip process induced non-uniformity. W. CLARK COVENTOR, Villebon sur Yvette, France Behavioral modeling of crosswafer chip-to-chip process induced non-uniformity W. CLARK COVENTOR, Villebon sur Yvette, France Variability Concerns Variability is a major concern of any semiconductor process

More information

UBS Technology Conference 2011 Franki D Hoore - Director European Investor Relations London, March 10, 2011

UBS Technology Conference 2011 Franki D Hoore - Director European Investor Relations London, March 10, 2011 UBS Technology Conference Franki D Hoore - Director European Investor Relations London, March 10, / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of

More information

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture : Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday -3pm CMOS Scaling Rules Voltage, V / α tox/α

More information

TABLE OF CONTENTS III. Section 1. Executive Summary

TABLE OF CONTENTS III. Section 1. Executive Summary Section 1. Executive Summary... 1-1 Section 2. Global IC Industry Outlook and Cycles... 2-1 IC Insights' Forecast Methodology... 2-1 Overview... 2-1 Worldwide GDP... 2-1 Electronic System Sales... 2-2

More information

Sub-Wavelength Holographic Lithography SWHL. NANOTECH SWHL Prof. Dr. Vadim Rakhovsky October, 2012

Sub-Wavelength Holographic Lithography SWHL. NANOTECH SWHL Prof. Dr. Vadim Rakhovsky October, 2012 Sub-Wavelength Holographic Lithography SWHL NANOTECH SWHL Prof. Dr. Vadim Rakhovsky October, 2012 EXECUTIVE SUMMARY SWHL is a new, alternative low cost approach to lithography SWHL is suitable for all

More information

Olivier Vatel. Accelerated innovation through strategic collaboration: a view from an equipment supplier CTO. July 10, 2018 SE L1

Olivier Vatel. Accelerated innovation through strategic collaboration: a view from an equipment supplier CTO. July 10, 2018 SE L1 1 SE-77-3018-L1 SCREEN Semiconductor Solutions Co., Ltd. Accelerated innovation through strategic collaboration: a view from an equipment supplier Olivier Vatel SCREEN Semiconductor Solutions Co., Ltd.

More information

Olivier Vatel. Accelerated innovation through strategic collaboration: a view from an equipment supplier CTO. March 1, 2018 SE L1

Olivier Vatel. Accelerated innovation through strategic collaboration: a view from an equipment supplier CTO. March 1, 2018 SE L1 Accelerated innovation through strategic collaboration: a view from an equipment supplier Olivier Vatel SCREEN Semiconductor Solutions Co., Ltd. CTO March 1, 2018 1 SE-77-3018-L1 SCREEN Semiconductor Solutions

More information

Agenda. Membership Status, Usage UCB Dept Trends. Web Page Highlights. New Equipment / Capabilities. FY 16/17 Rates Overview

Agenda. Membership Status, Usage UCB Dept Trends. Web Page Highlights. New Equipment / Capabilities. FY 16/17 Rates Overview Professor Ming C. Wu Dr. Bill Flounders Faculty Director Executive Director Agenda Membership Status, Usage UCB Dept Trends Web Page Highlights New Equipment / Capabilities FY 16/17 Rates Overview Summary

More information

High speed full wafer monitoring of surface, edge and bonding interface for 3D-stacking

High speed full wafer monitoring of surface, edge and bonding interface for 3D-stacking Sematech Workshop on 3D Interconnect Metrology Sematech Workshop on 3D Interconnect Metrology, July 13 2011 High speed full wafer monitoring of surface, edge and bonding interface for 3D-stacking Lars

More information

Technology and Manufacturing

Technology and Manufacturing Technology and Manufacturing Executive Vice President Field Trip 2006 - London, May 23rd Field Trip 2006 - London, May 23rd Technology Technology Development Centers and Main Programs CMOS Logic Platform

More information

Agenda Membership Status, Internal / External Usage Trends

Agenda Membership Status, Internal / External Usage Trends Professor Ming C. Wu Dr. Bill Flounders Faculty Director Executive Director Agenda Membership Status, Internal / External Usage Trends Staffing Status NanoLab High School Intern Program (3 min video) New

More information

SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics Corp., (SEC) 12/2/2016 SLIM Presentation 1

SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics Corp., (SEC) 12/2/2016 SLIM Presentation 1 SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics Corp., (SEC) 12/2/2016 SLIM Presentation 1 Introductions Prof. Rob Leachman, UCB IEOR Dept., technical author and SLIM project

More information

The Cornerstone Project:

The Cornerstone Project: The Cornerstone Project: UK Silicon Photonics Fabrication Capability based on DUV Photolithography Dr Stevan Stanković University of Southampton Outline Introduction What is CORNERSTONE? What is offered?

More information

Reflectivity metrics for optimization of anti-reflection coatings on wafers with topography

Reflectivity metrics for optimization of anti-reflection coatings on wafers with topography Reflectivity metrics for optimization of anti-reflection coatings on wafers with topography Mark D. Smith, Trey Graves, John Biafore, and Stewart Robertson KLA-Tencor Corp, 8834 N. Capital of Texas Hwy,

More information

Credit Suisse European Technology Conference

Credit Suisse European Technology Conference Credit Suisse European Technology Conference Franki D Hoore Director European Investor Relations May 12, 2010 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform

More information

Global and China Semiconductor Equipment Industry Report, Apr. 2012

Global and China Semiconductor Equipment Industry Report, Apr. 2012 Global and China Semiconductor Equipment Industry Report, 2011-2012 Apr. 2012 STUDY GOAL AND OBJECTIVES This report provides the industry executives with strategically significant competitor information,

More information

EUV Lithography and Overlay Control

EUV Lithography and Overlay Control YMS Magazine DECEMBER 2017 EUV Lithography and Overlay Control Efi Megged, Mark Wylie and Cathy Perry-Sullivan L A-Tencor Corporation One of the key parameters in IC fabrication is overlay the accuracy

More information

Technology & Manufacturing

Technology & Manufacturing Technology & Manufacturing Kevin Ritchie Senior Vice President Technology and Manufacturing Group Development & Manufacturing Strategy Process Technology Leadership Flexible Development Options Internal

More information

Mirroring functional Dual HDD Back-Up System - Prevention of data loss due to tool crash - (SCSI/IDE SATA conversion function equips)

Mirroring functional Dual HDD Back-Up System - Prevention of data loss due to tool crash - (SCSI/IDE SATA conversion function equips) Mirroring functional Dual HDD Back-Up System - Prevention of data loss due to tool crash - (SCSI/IDE SATA conversion function equips) Contact KYODO INTERNATIONAL INC. http://www.kyodo-inc.co.jp/ 2-10-9

More information

Joint Research with imec Belgium Targeting Measurement for 10-nm Generation

Joint Research with imec Belgium Targeting Measurement for 10-nm Generation 173 Corporations from around the world collaborate at imec on basic research into microelectronics and nanotechnology. Special Report Joint Research with imec Belgium Targeting Measurement for 10-nm Generation

More information

FDC multivariate anomaly detection through SVM algorithm implementation Daniele Vinciguerra. APC/SPC Manager - STMicroelectronics

FDC multivariate anomaly detection through SVM algorithm implementation Daniele Vinciguerra. APC/SPC Manager - STMicroelectronics FDC multivariate anomaly detection through SVM algorithm implementation Daniele Vinciguerra APC/SPC Manager - STMicroelectronics Motivation Typical tasks in astronomy Can you group all detected objects

More information

Multi-Level Overlay Techniques for Improving DPL Overlay Control

Multi-Level Overlay Techniques for Improving DPL Overlay Control Multi-Level Overlay Techniques for Improving DPL Overlay Control Charlie Chen 1, C Pai, Dennis u 1, Peter Pang 1, Chun Chi u 1, Robert (Hsing-Chien) Wu, Eros (Chien Jen) Huang, Marson (Chiun-Chieh) Chen,

More information

OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS

OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS Table 1a Product Generations and Chip Size Model Technology Nodes Near-term Years... 2 Table 1b Product Generations and Chip Size Model Technology

More information

Addressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03

Addressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 Addressable Test Chip Technology for IC Design and Manufacturing Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 IC Design & Manufacturing Trends Both logic and memory

More information

2002 Semiconductor Equipment Market Share Analysis (Executive Summary) Executive Summary

2002 Semiconductor Equipment Market Share Analysis (Executive Summary) Executive Summary 2002 Semiconductor Equipment Market Share Analysis (Executive Summary) Executive Summary Publication Date: 2 May 2003 Authors Mark Stromberg Klaus Rinnen Jim Walker Robert Johnson Dean Freeman Takashi

More information

Embedded UTCP interposers for miniature smart sensors

Embedded UTCP interposers for miniature smart sensors Embedded UTCP interposers for miniature smart sensors T. Sterken 1,2, M. Op de Beeck 2, Tom Torfs 2, F. Vermeiren 1,2, C. Van Hoof 2, J. Vanfleteren 1,2 1 CMST (affiliated with Ugent and IMEC), Technologiepark

More information

Status of PEMC Steve Arthur 8/18/2016

Status of PEMC Steve Arthur 8/18/2016 Status of PEMC Steve Arthur 8/18/2016 CNSE : Joe Piccirillo, PY Hung, Sean Valente, Tom Gorczyca GE : Ron Olson, Mike Hartig, Yang Sui, Andy Minnick, Matt Edmonds, Tim VandenBriel, Kevin Shatley, Justin

More information

TMT Conference 2011 Bank of America

TMT Conference 2011 Bank of America TMT Conference 2011 Bank of America London Franki D Hoore, Director European Investor Relations June 7, 2011 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform

More information

Piper Jaffray Europe Conference London

Piper Jaffray Europe Conference London Piper Jaffray Europe Conference London Franki D Hoore Director Investor Relations June 22, 2010 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995:

More information

Market Update. Peter Jenkins Vice President, Marketing. 24 November 2014

Market Update. Peter Jenkins Vice President, Marketing. 24 November 2014 Market Update Peter Jenkins Vice President, Marketing 24 Forward looking statements This document contains statements relating to certain projections and business trends that are forward-looking, including

More information

21 rue La Nouë Bras de Fer Nantes - France Phone : +33 (0) website :

21 rue La Nouë Bras de Fer Nantes - France Phone : +33 (0) website : 21 rue La Nouë Bras de Fer - 44200 Nantes - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr August 2012- Version 1 Written by: Maher SAHMIMI DISCLAIMER : System

More information

Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly

Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry Dr. Thomas de Paly October 06, 2009 Opportunity Meets Vision Vision To be the first truly global semiconductor foundry,

More information

FY2011 Financial Forecast and Basic Management Policy

FY2011 Financial Forecast and Basic Management Policy FY2011 Financial Forecast and Basic Management Policy Hiroshi Takenaka, President & CEO May 12, 2010 25 FY2010 Review 26 FY2010 Initial Financial Estimates vs. Results (Billions of yen) Net sales Initial

More information

3D Process Modeling - A Novel and Efficient Tool for MEMS Foundry Design Support

3D Process Modeling - A Novel and Efficient Tool for MEMS Foundry Design Support 3D Process Modeling - A Novel and Efficient Tool for MEMS Foundry Design Support Gisbert Hölzer, Roy Knechtel X-FAB Semiconductor Foundries, AG Stephen Breit, Gerold Schropfer Coventor, Inc. Overview A

More information

VLSIresearch - Critical Subsystems and Components Service Overview

VLSIresearch - Critical Subsystems and Components Service Overview VLSIresearch - Critical Subsystems and Components Service Overview The market for Critical Subsystems and Components for use in the semiconductor and related manufacturing equipment has emerged to become

More information

Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba

Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba Challenges in Manufacturing of optical and EUV Photomasks Martin Sczyrba Advanced Mask Technology Center Dresden, Germany Senior Member of Technical Staff Advanced Mask Technology Center Dresden Key Facts

More information

DSA: How far have we come and how much further is left to go? Darron Jurajda

DSA: How far have we come and how much further is left to go? Darron Jurajda DSA: How far have we come and how much further is left to go? Darron Jurajda Semiconductor Business Unit Director, Brewer Science Outline Background of DSA at Brewer Science DSA historical progress Hype

More information

PRODUCTS COMPETENCE IN THIN AND ULTRA-THIN WAFER PROCESSING AND HANDLING BASED ON TRANSFER ELECTROSTATIC CARRIER (T-ESC ) TECHNOLOGY

PRODUCTS COMPETENCE IN THIN AND ULTRA-THIN WAFER PROCESSING AND HANDLING BASED ON TRANSFER ELECTROSTATIC CARRIER (T-ESC ) TECHNOLOGY PRODUCTS COMPETENCE IN THIN AND ULTRA-THIN WAFER PROCESSING AND HANDLING BASED ON TRANSFER ELECTROSTATIC CARRIER (T-ESC ) TECHNOLOGY . CONTENTS Technology 04 Basics 04 T-ESC Solutions 04 Process Applications

More information

Photonics Integration in Si P Platform May 27 th Fiber to the Chip

Photonics Integration in Si P Platform May 27 th Fiber to the Chip Photonics Integration in Si P Platform May 27 th 2014 Fiber to the Chip Overview Introduction & Goal of Silicon Photonics Silicon Photonics Technology Wafer Level Optical Test Integration with Electronics

More information

Approaches to the Metrology Challenges for DSA Hole

Approaches to the Metrology Challenges for DSA Hole Approaches to the Metrology Challenges for DSA Hole Masafumi Asano, Kazuto Matsuki, Tomoko Ojima, Hiroki Yonemitsu, Ayako Kawanishi, Miwa Sato 2015 Toshiba Corporation Introduction Outline Metrology for

More information

Lecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia

Lecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia Lecture 4a CMOS Fabrication, Layout and Simulation R. Saleh Dept. of ECE University of British Columbia res@ece.ubc.ca 1 Fabrication Fabrication is the process used to create devices and wires. Transistors

More information

EUV. Frits van Hout Executive Vice President & Chief Program Officer. 24 November 2014

EUV. Frits van Hout Executive Vice President & Chief Program Officer. 24 November 2014 EUV Frits van Hout Executive Vice President & Chief Program Officer 24 Forward looking statements This document contains statements relating to certain projections and business trends that are forward-looking,

More information

Implementation of Automated Equipment Monitoring in a Highly Flexible Semiconductor Production Line. Semicon 2012, Dresden TechARENA

Implementation of Automated Equipment Monitoring in a Highly Flexible Semiconductor Production Line. Semicon 2012, Dresden TechARENA Implementation of Automated Equipment Monitoring in a Highly Flexible Semiconductor Production Line Semicon 2012, Dresden TechARENA Günter Leditzky October, 10th, 2012 ams AG Agenda ams AG Overview Focus

More information

Enabling DFM Flow Peter Rabkin Xilinx, Inc.

Enabling DFM Flow Peter Rabkin Xilinx, Inc. Enabling DFM Flow Peter Rabkin Xilinx, Inc. Open DFM Workshop San Jose CA v 9, 2006 2006 All Rights Reserved Fabless Litho-DFM Requirements Design Tolerance Req s Systematic & automated litho compliance

More information

3D INTEGRATION, A SMART WAY TO ENHANCE PERFORMANCE. Leti Devices Workshop December 3, 2017

3D INTEGRATION, A SMART WAY TO ENHANCE PERFORMANCE. Leti Devices Workshop December 3, 2017 3D INTEGRATION, A SMART WAY TO ENHANCE PERFORMANCE OVERAL GOAL OF THIS TALK Hybrid bonding 3D sequential 3D VLSI technologies (3D VIA Pitch

More information

Technology Platform Segmentation

Technology Platform Segmentation HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE FOR MULTIMEDIA CONVERGENCE Technology Platform Segmentation HP LP 2 1 Technology Platform KPIs Performance Design simplicity Power leakage Cost

More information

Keynote Speaker. Matt Nowak Senior Director Advanced Technology Qualcomm CDMA Technologies

Keynote Speaker. Matt Nowak Senior Director Advanced Technology Qualcomm CDMA Technologies Keynote Speaker Emerging High Density 3D Through Silicon Stacking (TSS) What s Next? Matt Nowak Senior Director Advanced Technology Qualcomm CDMA Technologies 8 Emerging High Density 3D Through Silicon

More information

Unit Growth and New Technology: Defining Factors for Capital Spending in the HDD Industry

Unit Growth and New Technology: Defining Factors for Capital Spending in the HDD Industry Unit Growth and New Technology: Defining Factors for Capital Spending in the HDD Industry Thomas Coughlin & Ed Grochowski Coughlin Associates www.tomcoughlin.com Outline Demand for digital storage drives

More information

TECHFORUM September 2018

TECHFORUM September 2018 DTU Danchip DTU DANCHIP National Center for Micro- and Nanofabrication DTU Cen TECHFORUM September 2018 14-11-2018 Agenda Short news and updates Laser micromaching tool Light rail CEN development New cleanroom

More information

Investor Relations 2018 Leader of Single Wafer Deposition

Investor Relations 2018 Leader of Single Wafer Deposition EUGENE TECHNOLOGY Investor Relations 2018 Leader of Single Wafer Deposition 1. Overview 1 Highlight CONTENTS 2 3 Company Overview History 4 Market / Dividend 2. Business 5 6 Business Area Core Competence

More information

Doug Schramm a, Dale Bowles a, Martin Mastovich b, Paul C. Knutrud b, Anastasia Tyurina b ABSTRACT 1. INTRODUCTION

Doug Schramm a, Dale Bowles a, Martin Mastovich b, Paul C. Knutrud b, Anastasia Tyurina b ABSTRACT 1. INTRODUCTION Algorithm Implementation and Techniques for Providing More Reliable Overlay Measurements and Better Tracking of the Shallow Trench Isolation (STI) Process Doug Schramm a, Dale Bowles a, Martin Mastovich

More information

Photoresist Qualification using Scatterometry CD

Photoresist Qualification using Scatterometry CD Photoresist Qualification using Scatterometry CD Roie Volkovich *a, Yosef Avrahamov a, Guy Cohen a, Patricia Fallon b, Wenyan Yin b, a KLA-Tencor Corporation Israel, Halavian St., P.O.Box 143, Migdal Haemek

More information

Driving the Technology Frontier; Implications on this Cycle Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference

Driving the Technology Frontier; Implications on this Cycle Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Driving the Technology Frontier; Implications on this Cycle Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Craig De Young VP Investor Relations and Corporate Communications March

More information

LITHOGRAPHY CHALLENGES FOR LEADING EDGE 3D PACKAGING APPLICATIONS

LITHOGRAPHY CHALLENGES FOR LEADING EDGE 3D PACKAGING APPLICATIONS LITHOGRAPHY CHALLENGES FOR LEADING EDGE 3D PACKAGING APPLICATIONS Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh Ultratech, Inc. 3050 Zanker Road, San Jose, CA 95134 USA mranjan@ultratech.com

More information

Development of innovative ALD materials for high density 3D integrated capacitors

Development of innovative ALD materials for high density 3D integrated capacitors Development of innovative ALD materials for high density 3D integrated capacitors Malte Czernohorsky General Trend: System miniaturization Integration of passive components Capacitors Inductors Resistors

More information

Kaufman Brothers 13 th Annual Investor Conference

Kaufman Brothers 13 th Annual Investor Conference Kaufman Brothers 13 th Annual Investor Conference Craig DeYoung, VP Investor Relations New York, New York September 14, 21 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities

More information

Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing. Elvino da Silveira

Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing. Elvino da Silveira Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing Elvino da Silveira Agenda Introductions & Trends Consumer products driving AMOLED Adoption! Lithography Challenges Devices

More information

Agate. XwinSys. Non-Destructive Inspection and Metrology Analysis for the Semiconductor

Agate. XwinSys. Non-Destructive Inspection and Metrology Analysis for the Semiconductor Agate Non-Destructive Inspection and Metrology Analysis for the Semiconductor Hybrid Configuration of X-Ray Analysis, Automated 3D Microscope and 2D Image Processing XwinSys Agate NON-DESTRUCTIVE ANALYSIS

More information

Natixis Technology Conference

Natixis Technology Conference Natixis Technology Conference Marcel Kemp Director Investor Relations - Europe March 24, 2016 Forward looking statements This document contains statements relating to certain projections and business trends

More information

Monolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc.

Monolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc. Monolithic 3D Integration using Standard Fab & Standard Transistors Zvi Or-Bach CEO MonolithIC 3D Inc. 3D Integration Through Silicon Via ( TSV ), Monolithic Increase integration Reduce interconnect total

More information

Integrated Circuit Fabrication

Integrated Circuit Fabrication Integrated Circuit Fabrication Professor Dean Neikirk Department of Electrical and Computer Engineering The University of Texas at Austin world wide web: http://weewave.mer.utexas.edu Integrated circuits

More information

Pushing 193i lithography by Joint optimization of Layout and Lithography

Pushing 193i lithography by Joint optimization of Layout and Lithography Pushing 193i lithography by Joint optimization of Layout and Lithography Peter De Bisschop Imec, Leuven, Belgium Semicon Europe Messe Dresden, Germany Lithography session October 12, 2011 Semiconductor-Industry

More information

Global and China Semiconductor Equipment Industry Report, Jan. 2014

Global and China Semiconductor Equipment Industry Report, Jan. 2014 Global and China Semiconductor Equipment Industry Report, 2013-2014 Jan. 2014 STUDY GOAL AND OBJECTIVES This report provides the industry executives with strategically significant competitor information,

More information

Bringing 3D Integration to Packaging Mainstream

Bringing 3D Integration to Packaging Mainstream Bringing 3D Integration to Packaging Mainstream Enabling a Microelectronic World MEPTEC Nov 2012 Choon Lee Technology HQ, Amkor Highlighted TSV in Packaging TSMC reveals plan for 3DIC design based on silicon

More information

Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing. Elvino da Silveira

Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing. Elvino da Silveira Maximizing Cost Efficiencies and Productivity for AMOLED Backplane Manufacturing Elvino da Silveira Agenda Introductions & Trends Consumer products driving AMOLED Adoption! Lithography Challenges Devices

More information

I N V E S T O R S P R E S E N T A T I O N

I N V E S T O R S P R E S E N T A T I O N I N V E S T O R S P R E S E N T A T I O N Rafi Amit, CEO Moshe Eisenberg, CFO November 2018 SAFE HARBOR The information presented today contains forward-looking statements that relate to anticipated future

More information

SEMI F Compliance Certificate EPRI PQ Star sm Test Program Certification Date: 10/06/05

SEMI F Compliance Certificate EPRI PQ Star sm Test Program Certification Date: 10/06/05 SEMI F47-0706 Compliance Certificate EPRI PQ Star sm Test Program Certification Date: 10/06/05 PQ Star Reference Number SEMIF47.120 Manufacturer: Siemens Product: DC Contactor Model Numbers: 3RT1044-1BB40,-3BB40

More information

Sampling Approaches to Metrology in Semiconductor Manufacturing

Sampling Approaches to Metrology in Semiconductor Manufacturing Sampling Approaches to Metrology in Semiconductor Manufacturing Tyrone Vincent 1 and Broc Stirton 2, Kameshwar Poolla 3 1 Colorado School of Mines, Golden CO 2 GLOBALFOUNDRIES, Austin TX 3 University of

More information

City of Dunedin, FL Department of Finance Government Services Center Five Year Cost Comparison 8/4/2010

City of Dunedin, FL Department of Finance Government Services Center Five Year Cost Comparison 8/4/2010 Government Services Center Five Year Cost Comparison Option #1 Option #2 Net Cost Comparison Debt Service Operating Cost Revenue Net Cost/(Revenue) Debt Service Operating Cost Revenue Net Cost/(Revenue)

More information

The world s first industry-led consortium (501.c.6 non-profit) for the manufacturing of advanced smart sensors and integrated devices

The world s first industry-led consortium (501.c.6 non-profit) for the manufacturing of advanced smart sensors and integrated devices The world s first industry-led consortium (501.c.6 non-profit) for the manufacturing of advanced smart sensors and integrated devices 1 ICAMR: A New Era of International Collaboration Innovation Networks

More information

Known-Good-Die (KGD) Wafer-Level Packaging (WLP) Inspection Tutorial

Known-Good-Die (KGD) Wafer-Level Packaging (WLP) Inspection Tutorial Known-Good-Die (KGD) Wafer-Level Packaging (WLP) Inspection Tutorial Approach to Inspection Wafer inspection process starts with detecting defects and ends with making a decision on what to do with both

More information

3DIC & TSV interconnects

3DIC & TSV interconnects 3DIC & TSV interconnects 2012 Business update Semicon Taiwan 2012 baron@yole.fr Infineon VTI Xilinx Synopsys Micron CEA LETI 2012 Copyrights Yole Developpement SA. All rights reserved. Semiconductor chip

More information

In-situ metrology for pad surface monitoring in CMP

In-situ metrology for pad surface monitoring in CMP Application note In-situ metrology for pad surface monitoring in CMP The CMP process Chemical Mechanical Planarization (CMP) is one of the most critical processes in the semiconductor, hard disk and LED

More information

High Throughput Maskless Lithography

High Throughput Maskless Lithography High Throughput Maskless Lithography Sokudo lithography breakfast forum July 14 th 2010 Bert Jan Kampherbeek, VP Market Development and co-founder Agenda MAPPER s Objective MAPPER s Status MAPPER s Roadmap

More information

Transforming Electronic Interconnect. Tim Olson Founder & CTO Deca Technologies

Transforming Electronic Interconnect. Tim Olson Founder & CTO Deca Technologies Transforming Electronic Interconnect Tim Olson Founder & CTO Deca Technologies Changing Form X-ray images courtesy of Nick Veasey & flickr.com Shipments in millions Changing Form Smartphone Sales Have

More information

Technology & Manufacturing. Kevin Ritchie Senior vice president, Technology & Manufacturing

Technology & Manufacturing. Kevin Ritchie Senior vice president, Technology & Manufacturing Technology & Manufacturing Kevin Ritchie Senior vice president, Technology & Manufacturing 27 in review Manufacturing strategy continues to deliver financial results Accelerating analog leadership Increased

More information

Physical stuff (20 mins) C2S2 Workshop 7/28/06

Physical stuff (20 mins) C2S2 Workshop 7/28/06 Physical stuff (20 mins) C2S2 Workshop 7/28/06 Clive Bittlestone TI Fellow Nagaraj NS DMTS, Roger Griesmer SMTS Carl Vickery SMTS Gopalarao Kadamati MGTS Texas Instruments Texas Instruments 2004,2005,2006

More information

Consolidating Architecture Overviews

Consolidating Architecture Overviews by Gerrit Muller HBV-NISE e-mail: gaudisite@gmail.com www.gaudisite.nl Abstract This presentation provides guidelines and means to capture architecture overviews. Main challenge is to maintain the overview

More information

Renesas recovery; Actual, what was learned and what the industry could do better

Renesas recovery; Actual, what was learned and what the industry could do better Renesas recovery; Actual, what was learned and what the industry could do better Shuichi INOUE Renesas Electronics Corporation SEMATECH Symposium June 26, 2012 Tokyo 2012 Renesas Electronics Corporation.

More information

More Course Information

More Course Information More Course Information Labs and lectures are both important Labs: cover more on hands-on design/tool/flow issues Lectures: important in terms of basic concepts and fundamentals Do well in labs Do well

More information

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 10: Three-Dimensional (3D) Integration

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 10: Three-Dimensional (3D) Integration 1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 10: Three-Dimensional (3D) Integration Instructor: Ron Dreslinski Winter 2016 University of Michigan 1 1 1 Announcements

More information

CLEAN ROOM TECHNOLOGY

CLEAN ROOM TECHNOLOGY CLEAN ROOM TECHNOLOGY Justin Mathew Applied Electronics and Instrumentation College Of Engineering, Trivandrum April 28, 2015 Justin Mathew (CET) Clean Room Technology April 28, 2015 1 / 18 Overview 1

More information

Process Control & Inspection, Assembly Programming, Reverse Engineering & Design. Products for the Electronics Industry

Process Control & Inspection, Assembly Programming, Reverse Engineering & Design. Products for the Electronics Industry Process Control & Inspection, Assembly Programming, Reverse Engineering & Design Products for the Electronics Industry COMPANY OVERVIEW Introduction Product Philosophy Agenda TECHNOLOGY AND HARDWARE PLATFORMS

More information

High Density, High Reliability Carbon Nanotube NRAM. Thomas Rueckes CTO Nantero

High Density, High Reliability Carbon Nanotube NRAM. Thomas Rueckes CTO Nantero High Density, High Reliability Carbon Nanotube NRAM Thomas Rueckes CTO Nantero Nantero Overview Founded in 2001 to develop nonvolatile memory using carbon nanotubes (CNT) for high density standalone and

More information