Peering into Moore s

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1 Peering into Moore s Crystal Ball: Transistor Scaling beyond the 15nm node Kelin J. Kuhn Intel Fellow Director of Advanced Device Technology Portland Technology Development Intel Corporation Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

2 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

Consistent 2-year scaling 65nm WIDE - 0.57 m 2 45nm WIDE 0.346 m 2 22nm WIDE 32nm WIDE 0.171 m 2 0.092 m 2 90nm TALL 1.

3 Consistent 2-year scaling 65nm WIDE m 2 45nm WIDE m 2 22nm WIDE 32nm WIDE m m 2 90nm TALL 1.0 m2 90 nm 65 nm 45 nm 32 nm 22 nm projected 90: 7 65: 8 45: 9 32: 9 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

4 Changes in Scaling THEN Scaling drove down cost Scaling drove performance Performance constrained Active power dominates Independent design-process NOW Scaling drives down cost Materials drive performance Power constrained Standby power dominates Collaborative design-process 130nm 90nm 65nm 45nm 32nm Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

Consistent SRAM Density Scaling Bit tcell

10 2X bitcell area scaling 90nm 65nm 45nm

5 Consistent SRAM Density Scaling Bit tcell Ar rea ( m 2 ) X bitcell area scaling 90nm 65nm 45nm 32nm Process generation 22nm K. Zhang, ISCC, 2009; M. Bohr IDF 2010 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

6 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

Ultra-thin body with RSD Extension of planar technology (less disruptive to manufacturing) Benefits Improved RDF (low doped channel) Compatible

7 Ultra-thin body with RSD Extension of planar technology (less disruptive to manufacturing) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent Potential for channel body bias control Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

8 Ultra-thin body with RSD Capacitance (Increased fringe to contact/facet) Rext: (Xj/Tsi limitations) Challenges Variation: (film thickness changes affects VT and DIBL) Strain: (strain transfer from S/D into the channel) Manufacturing: (requires both thin Tsi and thin BOX) Performance: (transport challenges withthintsi) thin Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

9 Barral CEA-LETI / L2MP / SOITEC IEDM 2007 Ultra-thin body Cheng IBM VLSI 2009 Lg=25nm Tsi=6nm Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

10 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal sub- threshold h slope (gates tied together) Improved RDF (low doped channel) Excellent channel Can be on control bulk or SOI Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

11 MuGFET with RSD Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal sub- threshold h slope (gates tied together) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, A

12 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Possibility for independent d gate operation Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, B

13 MuGFET Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring Hsi/Wsi/epi) Challenges Gate wraparound (Endcap coverage) Small fin pitch (2 generation scale?) Fin/gate fidelity on 3 D (Patterning/etch) Fin Strain engr. Topology Rext: (Effective strain (Polish / etch (Xj/Wsi transfer from a fin challenges) limitations) into the channel) Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

14 Kawasaki Toshiba / IBM IEDM 2009 MuGFET Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

15 Nanowire Benefits Nearly ideal sub- threshold h slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

16 Nanowire Benefits Nearly ideal sub- threshold h slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, A

17 Nanowire Integrated wire fabrication (Epitaxy? Other?) Mobility degradation (scattering) Gate conformality (dielectric and metal) Wire stability (bending/warping) Challenges Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring a myriad of new sources) Fin Strain engr. (Effective strain transfer from wire into the channel) Rext: (Xj/Wsi limitations) Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish / etch challenges) 13 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010

18 Dupre CEA-LETI IEDM 2008 Nanowire FETs Bangsaruntip IBM IEDM 2009 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

19 Hashemi/Hoyt MIT IEDM 2008 EDL/ESSDRC 2009 Nanowire FETs Moselund Ecole Polytechnique, Switzerland IEDM 2007 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

20 Vertical Architectures Vertical orientation may enable new circuit concepts Benefits 50% reduction in plan view density Possibility for different N/P materials/orientations Reduced vertical interconnect t capacitance Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

Vertical Architectures Rext: (Xj/Wsi limitations) Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish /

be processed over existing bottom layer) Contacts (Diffusion-diffusion, Gate-gate contacts extremely

g RDF but acquiring a myriad of new sources) Lithography (May double the number of FE critical layers) Strain

21 Vertical Architectures Rext: (Xj/Wsi limitations) Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish / etch challenges) Gate conformality (dielectric and metal) Challenges Thermal processing (Top layer may need to be processed over existing bottom layer) Contacts (Diffusion-diffusion, Gate-gate contacts extremely challenging) Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating g RDF but acquiring a myriad of new sources) Lithography (May double the number of FE critical layers) Strain engineering (more challenging than single layer) Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

22 Batude CEA LETI - IEDM 2009 stacked 110/100 Vertical Jung Samsung - IEEE TED D stacked 6T Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

TFET (Tunneling Field-Effect Transistor) Principle of operation Band-to-band- tunneling through source barrier,

Low drive currents Ambipolar conduction Unidirectional conduction Potentially high hot-e - effects Technology

engineering, perhaps with broken-gap Source Tunneling barriers Vg Gate P + i-inas N Drain Courtsey M.

23 TFET (Tunneling Field-Effect Transistor) Principle of operation Band-to-band- tunneling through source barrier, modulated by gate field Advantages Steep (< 60 mv/dec) sub-threshold slope Large Ion/Ioff ratio Disadvantages Low drive currents Ambipolar conduction Unidirectional conduction Potentially high hot-e - effects Technology Intercept Unlikely candidate for Si, Ge, or Si 1-x Ge x systems (drive currents too low) Need III-V band-gap engineering, perhaps with broken-gap Source Tunneling barriers Vg Gate P + i-inas N Drain Courtsey M. Luisier (Purdue) M. Luisier and G. Klimeck, EDL, 2009 Vd Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

24 Sensitivity to Source Doping Variation 1E+21 1E+20 1E+19 1E+18 1E+17 1E E+15 1E+14 TFET Source Doping Gradient Grad 0 Grad 1 Grad X (nm) Ids (A/um) 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1E E-14 1E-15 1E-16 1E-17 TFET TSi = 5nm, Lg = 20nm, Vds = 0.5V Grad0 Grad1 Grad Vgs (V) TFET behavior is very sensitive to the source doping shape 1E+21 1E+20 1E+19 1E+18 1E+17 MOS Source Doping Gradient Grad0 Grad1 Grad X (nm) (A/um) Ids 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 MOS TSi = 5nm, Lg = 20nm, Vds = 0.5V Grad0 Grad1 Grad Vgs (V) MOS behavior has little sensitive to the source doping shape Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

1.00E -02 1.00E -03 1.00E -04 1.00E -05 1.00E -06 1.

8 1 Best Demonstrated TFETs 32nm MOS @ Vds = 0.

Require band-gap engineering i with hetero-junction layers

, IEDM 09 [1] K. Jeon, et al., VLSI (11.4.1.-1) 2010 [2] W.

Mayer et al., IEDM Tech Dig., p.163 (2008) [4] T.

25 1.00E E E E E E E Best Demonstrated TFETs 32nm Vds = 0.8V Still MUCH lower drive currents than conventional MOS Require band-gap engineering i with hetero-junction layers Sub-threshold slope still poor [1] S. Mookerjea et al., IEDM 09 [1] K. Jeon, et al., VLSI ( ) 2010 [2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007) [3] F. Mayer et al., IEDM Tech Dig., p.163 (2008) [4] T. Krishnamohan et al., IEDM Tech Dig., p.947 (2008) Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

26 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

27 Transistor Performance Trend Drive Current (ma/um) nm 1.0 V, 100 na I OFF 45nm 65nm 90nm 130nm PMOS Strain Hi-k-MG Other Classic scaling Gate Pitch (nm) 100 Strain is a critical ingredient in modern transistor t scaling Strain was first introduced at 90nm, and its contribution has increased in each subsequent generation Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

28 Strain in modern devices Stress memorization Wei, VLSI 2007 Mayuzumi, IEDM 2007 Ghani, IEDM 2003 Yang, IEDM 2008 Auth, VLSI 2008 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

ORIENTATION (100) surface top down (110)

Surface / <100> (a 45 degree wafer) Both

<111> and <100> <100> Kelin Kuhn / Int l

29 ORIENTATION (100) surface top down (110) surface top down (100) <110> <110> <100> Standard wafer / direction <100> (100) Surface / <110> channel <111> <110> (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. (110) <110> Non-standard (110) Surface Three possible channel directions <110> <111> and <100> <100> Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

ORIENTATION (100) surface top down (110) surface top down (100) <110> <100> Standard wafer / direction <100> (100) Surface / <110> channel <111> <110> (100) Surface / <100> (a 45 degree wafer) Both

30 ORIENTATION (100) surface top down (110) surface top down (100) <110> <100> Standard wafer / direction <100> (100) Surface / <110> channel <111> <110> (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. (110) <110> Non-standard (110) Surface <110> <100> (100) BEST NMOS (110) <110> BEST PMOS Three possible channel directions <110> <111> and <100> Yang AMD/IBM EDST 2007 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, A

Orientation and Strain: More complex for non-(100) orientations (100) <110> (001) Surface (k =0) (001) Surface Vg=-1V (001) Surface Vg=-1V, Sxx=-1GPa (110) (110) Surface (k =0) (110) Surface

31 Orientation and Strain: More complex for non-(100) orientations (100) <110> (001) Surface (k =0) (001) Surface Vg=-1V (001) Surface Vg=-1V, Sxx=-1GPa (110) (110) Surface (k =0) (110) Surface Vg=-1V (110) Surface Vg=-1V, Sxx=-1GPa <110> BULK 1 D CONFINED 1 D CONFINED STRAINED Kuhn/Packan, Kelin Intel, Kuhn IEDM / Int l 2008 Symp. on Adv. Gate Stack Technology/ Sept. 29th,

32 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

33 Planar Resistive Elements R CONTACT R SILICIDE R INTERFACE R EPI R ACCUMULATION R SPREADING Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

34 Planar Resistive Elements Racc: Sub-melt Laser Anneal 1E+17 R CONTACT tration (atoms/cm3) Concent 1E+22 1E+21 1E+20 1E+19 1E+18 Phosphorus #0 - No Laser #4-91%, 60us #5-88%, 60us #6-85%, 60us #7-54%, 200us Depth (nm) Depth (nm) Kuhn, IWJT q R SILICIDE 1E+21 R INTERFACE 1E+20 Racc: Solid-phase Epi Regrowth (cm-3) R EPI 1E+19 R ACCUMULATION 1E+18 B in Si 1E R SPREADING Depth (nm) Kuhn, IWJT Concentration Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, A

35 Planar Rinterface: Resistive Reduction Elements Racc: Sub-melt in Laser Anneal 1E+17 Co Mn Fe 27;4 V 25;4 26;4 0.7 Ti 23;4 R CONTACT 22;4 Cr 24;4 R SILICIDE q B R interfaceq exp 1E+22 Schottky Barrier Height N D i (e.v.) ns tration (atoms/cm3) 1E+21 1E+20 Schottky theory Experiment 5 th period transition metals #0 - No Laser #4-91%, 60us #5-88%, 60us #6-85%, 60us #7-54%, 200us 4 th period transition 1E+19 6 th period transition metals Ni 28;4 Concent Y 39;5 1E+18 Zr 40;5 Phosphorus Kuhn, IWJT metals Pd 46;5 Rh 0 10 Ru 45; ;5 Mo Nb 42;5 Depth (nm) 41;5 Gd 64;6 Lanthanides Dy 66;6 Er 68;6 Yb 70;6 Hf 72;6 Ta 73;6 W 74;6 Os 76;4 Re 75;6 Ir 77;6 Pt 78;6 Desired for PMOS Si Mid- Gap 0.1 1E+21 R INTERFACE 1E Racc: Solid-phase Epi Regrowth (cm-3) Desired for NMOS R EPI 1E+19 Schottky Barrier Height Reduction is a critical area for 1E+18 development. Techniques R ACCUMULATION under investigation include B in Si exotic alloys, implants, and Fermi-unpinning 1E+17 layers R SPREADING Depth (nm) Kuhn, IWJT Concentration Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, B

Planar Resistive Elements Rcontact: Decreased Resistance of the Contact Metal R CONTACT Kuhn, IWJT 20010 R SILICIDE R INTERFACE Copper Contacts

36 Planar Resistive Elements Rcontact: Decreased Resistance of the Contact Metal R CONTACT Kuhn, IWJT R SILICIDE R INTERFACE Copper Contacts R EPI Topol, VLSI 2006 R ACCUMULATION R SPREADING Kuhn, IWJT Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, C

37 Schottky barrier S/D an option? Metallic SD Hole barrier set by SBH Electron leakage set by Eg-SBH Larson Spinnaker TED 2006 Conventional In a metal SB-MOS, S/D forms an atomically abrupt Schottky-barrier having the height b. The extreme limit for metal in the S/D regions (with associated improvements in Rext) Unconventional operation (field emission device in the ON state) Needs complementary devices (midgap silicide or two silicides) Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

38 Metallic SD Hole barrier set by SBH Schottky barrier S/D an option? Electron leakage set by Eg-SBH Larson Spinnaker TED 2006 Zhu IEEE TED May 2009 In a metal SB-MOS, S/D forms an atomically abrupt Schottky-barrier having the height b. The extreme limit for metal in the S/D regions (with associated improvements in Rext) Unconventional operation (field emission device in the ON state) Needs complementary devices (midgap silicide or two silicides) Two possible conduction paths: Thermionic over the barrier good SS slope Tunneling through the barrier poor SS slope Conventional 29A Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

39 Schottky barrier S/D an option? Electron leakage set by Eg-SBH Benefits Low bulk resistance contacts to the channel Very abrupt junctions No random s/d dopant fluctuation effects Minimize s/d carrier-carrier scattering effects Challenges Poor experimental drive currents Requires bandedge Schottky barriers Ambipolar conduction (high drain-body leakage for bulk devices) Metallic SD Conventional Early contact formation limits midsection process temperatures Larson Spinnaker Need alternative approach for s/d stressors TED 2006 Hole barrier set by SBH Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, B

40 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

41 Planar Capacitive Elements Cfringe to Contact Cfringe to facet Cjunction Cfringe to diffusion (of/if) Cxud - device component of Cov (XUD-based) Gated-edge junction Cchannel component of Cgate Area junction Kuhn, Intel, IEDM SC Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010

42 Planar Capacitive Elements Cfringe to Contact Cfringe to facet Cfringe to diffusion (of/if) Cxud - device component of Cov (XUD-based) Cjunction SiBCN (Low-K) SPACER Ko TSMC VLSI 2008 Gated-edge junction Cchannel component of Cgate Area junction SPACER REMOVAL Liow NUS Singapore EDL 2008 Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 Kuhn, Intel, IEDM SC A

43 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

44 Looking Forward Low risk Enhancements in strain technology Enhancements in HiK/MG technology Medium Risk Optimized substrate and channel orientation Reduction in MOS parasitic resistance Reduction in MOS parasitic capacitance High risk UTB devices MuGFETS Nanowires 3 D Stacked Devices Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

45 Q&A Kelin Kuhn / Int l Symp. on Adv. Gate Stack Technology/ Sept. 29th,

CMOS Scaling for the Next Decade and Emerging Technologies: SEMATECH Perspective. Accelerating the next technology revolution

US Korea NanoForum April 2009 Accelerating the next technology revolution CMOS Scaling for the Next Decade and Emerging Technologies: SEMATECH Perspective Prashant Majhi Front End Processes, SEMATECH Copyright