Development of innovative ALD materials for high density 3D integrated capacitors

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1 Development of innovative ALD materials for high density 3D integrated capacitors Malte Czernohorsky

2 General Trend: System miniaturization Integration of passive components Capacitors Inductors Resistors

3 Source: Yole Développement 2012 Thin Film IPD Report

4 Applications of capacitors Capacitance density RF filtering & matching Bypassing, decoupling Chargepumping & storage SiP 10µF/mm² 1µF/mm² 100nF/mm² 10nF/mm² 1nF/mm² 100pF/mm² max. max. RF transceivers power amplifiers Audio filters Microcontroller Baseband ICs GPUs, CPUS, Si-Interposer ASICs BEoL DC/DC converters Sensors, Medical Source: CNT /Yole 250nF/mm² in package 20nF/mm² on CMOS BEoL BEoL FEoL SoC

5 How to increase capacitance density? 2D 3D Dielectric Bottom Electrode 2. Use High-k Materials Conventional: SiO 2 (k=3.9) Ta 2 O 5 (k=26) HfO 2 /ZrO 2 (k<40) TiO 2 (k=80), STO (>100) C = ε 0 k A d 1. Thickness tuning Operating conditions Reliability! 3. Enhance surface area 3D integration Structures with high aspect ratio

6 How to increase capacitance density? 1 Stack capacitor 9nm ZAZ 65 nm, UBM Techinsights 2. Use High-k Materials Conventional: SiO 2 (k=3.9) Ta 2 O 5 (k=26) HfO 2 /ZrO 2 (k<40) TiO 2 (k=80), STO (>100) C = ε 0 k A d 1. Thickness tuning Operating conditions Reliability! ZrO 2 -based 26 nm, Chipworks 3. Enhance surface area 3D integration Structures with high aspect ratio

7 Focus of capacitor research at Fraunhofer IPMS-CNT Capacitance density RF filtering & matching Bypassing & decoupling Chargepumping & storage SiP 10µF/mm² 1µF/mm² 100nF/mm² 10nF/mm² 1nF/mm² 100pF/mm² max. max. RF transceivers power amplifiers ~20-40 nf/mm 2 Audio filters Microcontroller Baseband ICs GPUs, CPUS, Si-Interposer ASICs BEoL DC/DC converters Sensors, Medical ~250 nf/mm 2 Source: CNT /Yole 250nF/mm² in package 20nF/mm² on CMOS BEoL BEoL FEoL SoC

8 Integrated 3D capacitor fabrication using 300mm wafer processing METAL ELECTRODES ASM A412 TM Large Batch Furnace HIGH-K DIELECTRIC Jusung Eureka 3000 TE Dielectric BE 35 nm TiN nm ZAZ 10 nm TiN Si- Substrat TiN: TiCl 4 / NH 3 Bottom electrode (BE): ALD Top electrode (TE): pcvd, C ZrO 2 : TEMAZr / O 3 Al 2 O 3 : TMA / O 3 ZrO 2 -Al 2 O 3 -ZrO 2 laminates (ZAZ)

9 Test chip patterning Patterning Litho: Vistec SB3050DW variable shaped e-beam direct write (50kV) HM-Etch: AMAT Enabler CCP Si-Etch: AMAT MERIE CCP TiN-Etch: Wet chemistry Test Chip 3D MIM test module CD/Pitch variation Demonstrator module 4 mm² with ~80 million trenches Planar test module planar vs. 3D benchmark

10 Material optimization of the dielectic Decrease of surface roughness and defect density by lamination Conformal ALD deposition in trench

11 Time to Breakdown (s) Current Density (A/cm²) TiN 500 C Material optimization of the metal nitride electrode nm ZAZ C 400 C nm ZAZ 450 C 400 C 10-8 ZAZ Voltage (V) 15 nm ZAZ 400 C 450 C 18 nm ZAZ 400 C 450 C 10 years Electric Field (MV/cm) 22 nm ZAZ 11 nm TiN Failures at high temperatures Leakage and lifetime improvement by lowering TE to 400 C

12 Uniformity tuning (batch vs. single wafer) ALD Batch process (3.0% 1s ) ALD single wafer (2.6% 1s) ,19 19,41 19,62 19,84 20,06 20,27 20,49 20,71 20,93 21,14 21, ,20 19,39 19,57 19,75 19,93 20,12 20,30 20,48 20,66 20,85 21,03 Batch ALD for layers with higher thickness Non-ideal ALD process TEMAHf/O 3 for HfO 2 Small CVD component observed

13 uniformity / %1σ Uniformity of HfO 2 batch ALD deposition temperature / C Lower the deposition temperature improves uniformity Avoids decomposition of ALD precursor (TEMAHf)

14 Patterning of 3D structures in silicon CD Variations for high-density Structures CD (nm) Resist open AR 6:1 Silicon etch Starting Erosion Pattern Collapse Pattern Collapse

15 C (nf/mm 2 ) Pitch (nm) CD (nm) Patterning of 3D structures in silicon Aspect Ratio Increase Pattern Collapse Pitch CD Pattern collapse decreases capacitance Fl 04 optimum setup Maximum capacitance of 240nF/mm Planar Flav01 Flav02 AR 6:1 AR 13:1 AR 15:1 AR 20:1 Pattern collapse Flav03 Flav04 Flav05 Flav06 Flav07 Flav08 Flav09 Flav10

16 Alternative approach for 3D patterning 3D Pillar structure High aspect ratio (1:60) Inspired by nature Courtesy of

17 Step coverage in 3D structures Conformal ALD deposition in trench (aspect ratio 1:60) ALD Batch process Step coverage in 3D structures up to 80% Comparable to ALD single wafer process HfO 2 Figure 1: SEM micrographs of the HfO 2 /Al 2 O 3 nanolaminate ALD reference process deposited in IPDiA s 3D capacitor structures with a layer thickness of 45 nm on the surface and 37 nm at the top (a) and 37 nm at the bottom of the trench (b) proving an excellent step coverage. 3D structures

18 Electrical characterisation - Aspect ratio 6:1 <5% (273 ppm) <3% 100 nf/mm 2 Reliability pass for 10 years (3.5V) 10-9 (A/µF) 100 nf/mm 2 Reliability pass for 10 years (3.5V)

19 Setup for electrical charaterization D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 18 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 17 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 16 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 15 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 14 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 13 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 12 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 11 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 10 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 9 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 8 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 7 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 6 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 5 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 4 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 3 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 1 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D FLAT Figure 1: Single MIM short loop design used for the process studies (a) and layout on the wafer (b). The MIM stack consists of TiN/Al 2 O 3 /TiN and is covered by an Al top contact (c).

20 Yield optimization Capacitance distribution with excellent uniformity Voltage linearity is below 2% over the voltage range (>10V) Breakdown voltage distribution with good uniformity

21 Conclusions Capacitors for both SiP and SoC systems developed with optimized electrical properties of dielectric, barrier layers and reduced deposition temperature for top electrode 250 nf/mm 2 capacitors for buffer application with operation voltage of 3.5 V by 3D structures with high-k dielectrics with a 10 years reliability pass at continuous 3.5 V Possible scaling towards >1µF/mm² and for various voltage ranges High-K Dielectrics for higher operating voltages (V use >10V)

22 Thank you. The Audience High-K Group / ALD Team Part of this work has received funding from the European Union's Seventh Framework Program managed by REA-Research Executive Agency (FP7/ ) under grant agreement n FP7-SME