High Speed Optical Link Based on Integrated Silicon Photonics

Transcription

1 High Speed Optical Link Based on Integrated Silicon Photonics Dr. Haisheng Rong Photonics Research Lab Intel Corporation PKU, Summer School July 04, 2012

2 Agenda Motivation Electronic & Photonic Evolution Intel s Research Program Integrated SiP link Challenges & Summary 2

3 Estimating the Exaflood, Discovery Institute, 1/08; Amassing Digital Fortunes, a Digital Storage Study, CEA, 3/08 A Wealth of Data to Move Personal Media Business Medical Social Media Science Human Genomics 7 EB/yr, 200% CAGR Ave. Files on HD 54GB Retail Customer DB 600 TB Clinical Image DB ~1PB HD video forecast 12 EB/yr Physics (LHC) 300 EB/yr More than 15B connected devices by 2015 Kiosks Medical Imaging Network Appliances Digital Signage Test & Measurement Security Surveillance In-Vehicle Infotainment 3 How do you connect all these?

4 Example: Advanced Video Technology 3D Displays High Dynamic Range 24Hz 48Hz 60Hz 120Hz (3D) HDR Increase (color depth) Today: Full HD 1080p Tomorrow : Quad HD 2160p Gbps 4.78 Gbps 2.39 Gbps 9.56 Gbps 2.39 Gbps 9.56 Gbps 4.78 Gbps Gbps 2.99 Gbps Gbps 5.97 Gbps Gbps 5.97 Gbps Gbps Gbps Gbps 4 Future: Ultra High Definition (4320p, 30bpp, 60Hz) needs 60 Gbps! Hard to do this electrically.

5 Challenges for Cu Interconnects Platform requirements taking it to the breaking point Copper cables have issues with distance, bend radius, weight, thickness, and airflow interruption 5

6 What if we could Eliminate Distance & Bandwidth Constraints Using Optical Links? Optical links Board-Board Multiprocessing Rack Level Interconnect Optical links Multi-terabyte Memory Bank Shared Memory Optical links New opportunities to: Increase performance Reduce system costs Reduce thermal density Improve energy efficiency Enable new form factors-id Optical links Could Revolutionize future platform architectures But. Have to be low cost to enable 6

7 Moving to Optical Interconnects Optical Copper Metro & Long Haul km Chip to Chip 1 50 cm Billions Rack to Rack 1 to 100 m Board to Board cm Millions Volumes Thousands Decreasing Distances Need to Drive optical to high volumes and low costs 7

8 Electronics: Economics of Moore s Law SCALING + WAFER SIZE + HIGH VOLUME = LOWER COST Integration & increased functionality 8

9 A Half Century of Integration 1959 Today Silicon ~50 years First Silicon IC (Noyce and Kilby) Billions of Transistors We have gone from 2 transistors to 2 billion This Moore s Law scaling has led to transformative technologies 9 Mainframes -> Servers -> PCs -> Laptops -> Handhelds Internet, e-commerce, social media Silicon manufacturing has made this all possible

10 A Half Century of Innovation 1960 Today Lasers 50 years First Laser (Ted Maiman) Countless apps Practical usages not known upon invention Laser has impacted industries from medicine to manufacturing to entertainment and more All long distance communications driven by lasers 10 Costs limits use of optical for everyday devices

11 Bringing Si Manufacturing to Optical Comms Si Manufacturing Optical Communications High volume, low cost Highly integrated Scalable Very high bandwidth Long distances Immunity to electrical noise OPTICAL ANYWHERE, INCREDIBLE POTENTIAL 11

12 The Opportunity of Silicon Photonics Enormous ($ billions) CMOS infrastructure, process learning, and capacity Draft continued investment in Moore s law Potential to integrate multiple optical devices Micromachining could provide smart packaging Potential to converge computing & communications To benefit from this optical wafers must run alongside existing product. 12

13 Silicon as an Optical Material Photon Energy (ev) eV 0.41 Wavelength (µm) µm 3.0 Transparent in >1.2 µm High index Low light emission efficiency Low cost material No electro-optical effect CMOS compatible No detection in µm High Thermal conductivity 13 Silicon traditionally NOT optical material of choice 13

14 The Path to Siliconizing Photonics Lasers Data Encoders Light detectors 1 st Continuous Wave Silicon Raman Laser (Feb. 05) Silicon Modulators 1GHz ( Feb 04) 10 Gbps (Apr 05) 40 Gbps (July 07) 40 Gbps PIN Photodetectors (Aug. 07) Hybrid Silicon Laser (Sept. 06) Basic Light Routing Waveguides, multiplexers, demultiplexers, couplers 340 GHz Gain*BW Avalanche Photodetector (Dec 08) 14 Numerous scientific breakthroughs in silicon photonic building blocks

15 Intel s Second Generation: Silicon Modulator input 1x2 MMI pn phase shifters 2x1 MMI output Metal contact Phase shifter waveguide SEM picture of p-n phase shifter - Based on traveling wave design - Optimized optical & electrical RF 15

16 40 Gbps Data Transmission 40 Gbps Normalized Modulator Output (db) Optical Roll-off (1mm phase shifter) On-chip termination External termination Frequency (GHz) Optical 3 db roll off ~30 GHz (parasitic effect included) 6 db electrical roll-off ~ 40 GHz (no parasitic effect included) Measured phase efficiency = 3.3 V-cm 16

17 Photo-detection Silicon does not absorb IR well Using SiGe to extend to 1.3µm+ Must overcome lattice mismatch Ge Bulk Films of Si and Ge Strained Si 1-x Ge x on Si Relaxed Si 1-x Ge x on Si Si a Ge ~.565 nm a Si ~.543 nm misfit dislocation Misfit dislocations typically create threading dislocations which degrade device performance - dark current (I dk ) goes up. Must simultaneously achieve required speed, responsivity, & dark current 17

18 Waveguide Photo-detector Design N-Ge i-ge SEM Cross-Section 18

19 SiGe WG PIN - High Speed Performance Relative Responsivity (db) GHz Optical Bandwidth Bandwidth (GHz) um x 50um 4.4um x 100um Voltage (V) 7.4um x 50um, -2V 4.4um x 100um, -2V Frequency (Hz) 40 Gb/s Eye Diagram 95% Quantum Efficiency Operating at λ ~1.56um < 200nA of dark current 19

20 Hybrid Silicon Lasers The Indium Phosphide emits the light into the silicon waveguide The silicon acts as laser cavity: Silicon waveguide routes the light End Facets or gratings are reflectors/mirrors Light bounces back and forth and gets amplified by InP Laser performance determined by InP and Si waveguide - No alignment needed - Multiple lasers with ONE bond - Light inside the waveguide 20

21 Hybrid Laser Fabrication Overview III-V material (unprocessed) is bonded everywhere or only on small parts of a wafer/die Alignment during bonding is not critical III-V is processed after bonding, with mask alignment to underlying silicon markers (1) Wafer Bonding Process (2) III-V Backside Process

22 DBR Lasers on Hybrid Laser Platform Tapers transition from hybrid (active) WG to silicon (passive) WG Gratings in silicon WG form wavelength selective mirrors

23 Hybrid silicon evanescent modal gain Silicon waveguide dimensions control MQW overlap and modal gain Changing waveguide width allows for varying confinement factors within a die or PIC MQW

24 Lithographically defined first order gratings Fabricated using 193-nm laser stepper lithography (HVM compatible) Period Top Down View Grating width Gap length Cross section 0.3um 0.5um 1.5um etch width etch depth

25 Single Wavelength Hybrid Laser grating mirrors in silicon, enabling wavelength-specific laser light output The Device ~1000um Optical Spectrum Line width Measurement ~150 um 25

26 Common Building Block Economy of Scale Integrated SiP Tx and Rx Building Blocks Challenges: - Integrate all building blocks onto Si platforms - Optimize processes for integration (vs. discrete) - Low cost packaging, assembly, and system testing - Do all these using PC-Board techniques and passive optical alignment

27 The 50G Integrated Silicon Photonics Link Transmitting and Receiving Light with Silicon Optical Fiber Integrated Transmitter Chip Integrated Receiver Chip Transmit Module Receiver Module 28

28 Integrated Silicon Photonics Link 4λx12.5 Gb/s Elements are combined together, along with drivers and packaging to form a CWDM link 29

29 Integrated Transmitter Chip Electrical data in Up to 12.5 Gbps/channel Integrates Hybrid Silicon Lasers With Modulators for data encoding and a Multiplexer to put 4 optical channels onto 1 fiber Alignment Pin 50Gbps out on one optical fiber Connector 30 Parallel channels are key to scaling bandwidths at low costs

30 Integrated Receiver Chip Integrates a coupler to receive incoming light with a demultiplexer to split optical signals and Ge-on-Si photodetectors to convert photons to electrons Alignment Pin Coupler Electrical data out Up to12.5 Gbps per channel Gbps in on one optical fiber Connector 31 Receives 4 optical channels at 12.5Gbps and converts to electrical data

31 Measured Data 4 hybrid Silicon Laser Outputs 12.5Gbps data output per channel Transmit Receive De-Multiplexer separates wavelengths Electrical Output From Receiver 32 We ran link for more than a day with no errors (>1 Petabit) Translates to Bit-Error-Rate (BER) of < 3e , Intel Corporation. All Rights Reserved

32 4λx10Gbps SiP Tx & Rx Packages Optical Fiber Integrated 4λ x10g SiP Tx Chip Transmitter Package Receiver Package Integrated 4λ x 10G SiGe PD Rx CMOS Driver IC Passive Optical Connector Receiver IC Socketable Edge Connector Tx & Rx packages enable both separable (passive) optical and electrical connectors 33

33 What Could You Download in <1 second? 34

34 What Could You Download in <1 second? 35 1 Tbps could download the entire printed collection of the Library of Congress in about 1½ minutes!

35 The Path to Tera-scale Data Rates Today: 12.5 Gbps x 4 = 50Gbps 25 Gbps x 4 = 100Gbps Scale UP 40G, 100G Scale OUT 12.5 Gbps x 8 = 100Gbps Speed Width Rate 12.5 x4 50G 12.5 x8 100G 25 x16 400G 40 x25 1T Future Terabit+ Links 36 x16, x32 Could enable cost-effective high speed I/O for data-intensive applications

36 CMOS Integration Challenges Film topology Thermal budgets Yield metrology Contaminating the fab Coupling to devices Heat dissipation Complexity Optical wafers must run alongside product, introducing challenges 37

37 Example: Topology Depth of focus (DOF) shrinks as litho improves Many optical devices are much taller than transistors New planarization techniques and specific process flows required for advanced litho DOF vs. Litho Technology (µm) Transistor on 90nm 8µm Taper µm Rib 0.5 µm 0.35µm 0.2µm 0.1µm gate 0.3µm Strip 38 Silicon Wafer 38

38 Example: Thermal Budgets 1050 C Temperature Melting Point of InP 1054 C Gate Oxide 950 C S/D Activation Melting Point of Ge 940 C Annealing of Si nc 800 C C Gate Contacts Processing Steps 450 C Thermal budget dictates process step order Cannot use high temperatures at later steps without damage Al / Cu 200 C Packaging Optical Polymers 200 C This determines what can be integrated in the fab vs. backend 39

39 Example: Yield metrology Electronics: CMOS fabs monitor thousands of parameters across wafer in line Tight control e.g. CMOS gate width held to 10 s of angstroms Significant per-wafer cost savings from screening out yield early Screening wafers for early defect detection Integrated vertical coupling approaches Optical In-line wafer level optical probing is very immature Most optical device testing is performed after wafer dicing For HVM, techniques for screening optical wafers must be developed 40

40 Challenges: Optical Integration with CPU Package topside Connection? Monolithic Integration? PROCESSOR FIBERS ORGANIC PACKAGE SOCKET FR4 MOTHERBOARD Board connection? Challenges: Power: CPU s operate with Temperatures near ~85 C Packaging: Compatibility with existing HVM packages connector cost Testing: Testing co-packaged optical /electrical CPU modules Packaging, thermals and testing key to enabling optical in platform 41

41 Summary SiP is a key enabling technology for high BW interconnects Developed first fully integrated Si photonics based Tx & Rx Demonstrated CWDM based Si Photonic 50Gb/s On path to develop fully integrated silicon photonic links to address various interconnect applications 42 Acknowledgements Intel Corp. - SiP team and LAD team Aurrion Inc. For InP processing and hybrid laser developments Micron For Silicon Photonics processing

42 Thank You! 43 To learn more

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44 Silicon Photonics Future Filter ECL Drivers Modulator Multiple Channels CMOS Circuitry TIA TIA Passive Alignment Photodetector 45