Design Flow for a ASIC design in the rad hard CERN-IBM library

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Brent Berry
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1 Design Flow for a ASIC design in the rad hard CERN-IBM library May 21, :11 pm A. Kluge 1.0 License Server cadstat or cadstat17 summarizes the use of the licenses. With lmremove name_of_license user_host_entries(from cadstat; 3 entries) one can give back licenses. i.e.: lmremove pmoreira sybyl pcvlsi16.cern.ch:0.0 Resore or archive any files with /usr/dsm/dsm. Use df. to find out where the homedir is mounted. 2.0 Necessary init files.cdsenv is created automatically.cdsinit* is created automatically.simrc* is used for simwave.synopsys_dc.setup (see below) cds.lib se.ini 3.0 Using Synopsis - design_analyzer to create a technology dependent verilog netlist Copy the technology files: cmos6sf25.db,cmos6sf25.lib, cmos6sf25s.sdb, cmos6sf25s.slib from the directory: /vlsicad/vlsilibs/ibm_cern/cmos6sf/9910a/synopsis into the working directory. cp /vlsicad/vlsilibs/ibm_cern/cmos6sf/9910a/synopsis/cmos6sf25*. Create.synopsys_dc.setup file in the home directory. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

2 /* Library and Search Path variables */ link_library = { cmos6sf25.db } target_library = { cmos6sf25.db } symbol_library = { cmos6sf25s.sdb } search_path = search_path + "/vlsicad/vlsilibs/ibm_cern/cmos6sf/9910a/synopsis" bus_naming_style = "%s_%d" define_name_rules default_name_rules -allowed "A-Za-z0-9_" -last_restricted "_" -first_restricted "_" -map {{"\*cell\*","u"},{"*-return","ret"}}; /* General */ company = "". Start: design_analyzer &. Analyze => design.v. Elaborate threeff into the library WORK. Select threeff, Attributes => Wire load => 100k. (might cause an overestimation) Attributes => Operating conditions => worst. Select clk in the symbol view, Attributes => Clocks > Specify > Period > 8 ns (125 MHz). Select output ports of threeff > Attributes > Operating Environment > Output Delay > 2ns AND click clk. Analysis > Check Design and clk timing check. Resolve multiple references to a subdesign by: selecting the design view and selecting the top view and choose edit > uniquify > hierarchy. (not necessary for threeff). Select threeff > tools > design optimization. Click verify design and allow boundary optimization > OK. Analysis > Report > Timing > OK. File > Save as > threeff.db File > Save as > threeff_synopsis.v In command window type: write_sdf threeff_synopsis.sdf Now simulation with verilog theoretically possible but compatibility problems with sdf file occur. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

3 4.0 From the Synopsis VERILOG netlist to the placed and routed design Create a cds.lib file in the working directory with a new library: ibmdesignflow_test. 4.1 Import the VERILOG netlist from synopsis into icfb and export it as.def file. opendesignkit & in the.cshrc file setenv CDS_INSTALL /vlsicad/micsoft/ic4.43 setenv SE_DIR /vlsicad/micsoft/dsmse5.2 setenv CDSDIR $CDS_INSTALL/tools Load the technology file into the work library Technology File > Attach to Design Library: ibmdesignflow_test; Technology Library: cmos6sf25techlib. Import VERILOG > threeff_synopsis.v -v Options =(/vlsicad/micsoft/ibm_ep_kit.23_8/designkits/cmos6sf25deskit_v1.0.1/ cmos6sf25/verilog/cmos6sf25_verilogin.v) not sure if it imports the functional view of the library cells -y Options does but only for the old version /vlsicad/vlsilibs/ibm_cern/cmos6sf/ 9910a/verilog/vdd_2.5v/ Reference library:cmos6sf25corelib cmos6sf25padlib cmos6sf25techlib target library: ibmdesignflow_test library ext:.v import as schematics and functional Verilog cell modules: import? Call the schematic view of threeff=> Tools/Floorplan; (version ic4.43 needed) Floorplan => Hierarchy Browser > OK > Select the threeff box => Hierarchy > Generate physical hierarchy; This generates a Autolayout view of the design, it must be exported as a.def file. File > Export; Library: ibmdesignflow_test, cell name threeff, view name autolayout, def file name: threeff_icfb.def, target p&r engine: silicon ensemble In the generated def file: include: COMPONENTS 4 ; - CORNER1 CORNERlogo ; - CORNER2 CORNER ; - CORNER3 CORNER ; - CORNER4 CORNER ; Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

4 END COMPONENTS Copy the lines where gnd! and vdd! are described in the NETS command between the following lines: SPECIALNETS<space>2<space> ; copied lines END SPECIALNETS remove gnd and vdd from normal nets, decrease net count by 2. and save the file as threeff_icfb_special.def. 4.2 Create an abstract from an new component Copy layout into desing library. Tools; Abstract; C3. Draw a rectangle with the layer prbndry dg above the component. (It might be necessary to apply Tools; Layout first.) Autoboundary is available but did not work. Abstract; Set Cell Props: Cell Type: Macro,Cell class: block, cell symmetry, x, y, r90. Abstract; Abgen; Rules library: cmos6sf25techlib In Abstract; Abstract; creat obstruction: layers in M1, M2 and MZ to prevent routing in the block. Export cell as lef file: Create lefout.list file: ibmdesignflow_test csbpadfin_3m abstract analog.lef add site info + symmetry info add SITE io_site add symmetry x y r90 add on pin vdd use power add on pin gnd use gnd all io cells must have 350 um width in the lef file; router connects properly but places component wrongly (manual move in layout necessary) Remove from analog.lef layer and via definition: LAYER RX......END Viagen_M2MZ Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

5 4.3 Place and route the design using standalone silicon ensemble (se) If def file is imported then verilog netlist cannot be exported from def, (problems when using clock tree generator, since it changes the netlist, must be reimported into cadence for LVS) A ctlf file is created for all non standard components from a tlf file. program tlfc file.tlf -o file.tlfc compile the tlf file. An online tutorial is available via the help button in se. cp /vlsicad/micsoft/ibm_ep_kit.23_8/designkits/cmos6sf25deskit_v1.0.1/ cmos6sf25/se/*. (copies also the se.ini file) Comment (#) set v db.design.dir "dbs" ; in se.ini Call silicon ensemble version 5.2 sedsm -m=(memory space in mega byte) but first change.cshrsc file to: setenv SE_DIR /vlsicad/micsoft/dsmse52.qsr4 setenv CDS_INST_DIR $SE_DIR setenv LM_LICENSE_FILE 5280@ set path = ( /vlsicad/micsoft/dsmse52.qsr4/tools.sun4v/dsm/bin /vlsicad/micsoft/ DSMSE52.qsr4/tools.sun4v/bin /vlsicad/micsoft/ibm_ep_kit/designkits/bin $SYN- OPSYS/$ARCH/syn/bin /appl/ihs ~/bin ~ /scripts /usr/ucb /usr/sue/bin /usr/sbin /opt/ SUNWspro/bin /usr/ccs/bin /usr/bin /usr/openwin/bin /usr/dt/bin /usr/local/bin /usr/ local/bin /usr/local/bin/x11 /cern/pro/bin. /bin ) Execute 1_read_lib.mac Import analog.lef. Import the three_icfb_special.def (design.def) file from icfb. or the verilog netlist of the design (especially then when a verilog output file of the placed and routed design is required) Floorplan => Initialize. Assign IO to core Distance (i.e. 40 microns), assign row utilization (i.e. 92% for the the threeff design 50% used), check flip every other row and abut rows, press OK. Move analog block and delete overlapping rows (check rows, select and delete) Place IO (First Random, creates a file ioconstraint.file which can be modified) Execute io_filler.mac Execute macro add_cap_cells.mac (to add CAPL and CAPR) Route => Plan Power. Add Rings; Horizontal Core ring width (i.e 100 microns), Vertical Core ring width (i.e 100 microns) (Core for logic core, block for custom blocks). Add stripes; number 2, width 10 spacing 2 (if bigger cells might be placed in between) Connect Ring; Check Stripe only. Place Cells => Variable: QPLACE.LLC.PREWIRE.KEEPOUT = true => OK. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

6 Place => Clock Tree Generation Place Filler Cells with the execution of the macro: core_filler.mac Route Connect rings => check follow pins only => OK. Connect to power pins manually in layout or in silocon ensemble Route => Clock all => OK. Route => Wroute => OK Save as routed. Export as threeff_routed.def. Report => Report RC => threeff_icfb.rspf design_routed.def can be imported into icfb. Export as threeff_routed.sdf for post placement simulation.(?? which timing delay model) 5.0 Import.def file into icfb import def, library name: ibmdesignflow_test, cell name threeff, view name: layout, def file name: threeff_routed.def, target p&r engine: silicon ensemble, reference library cmos6sf25corelib cmos6sf25techlib cmos6sf25padlib Open layout and replace view fromabstract to layout: Floorplan => Replace View => Layout => all => OK => save. Open new view top_threeff and place threeff there. Add CAPR and CAPL to close guard ring between power strips. Connect power pins to rings manually, use connect contact to create vias and f4 to select lines only when stretching. Attach pins on layout in order to facilitate LVS. Perform DRC, LVS (extraction: flat) and DRACULA (ask Paulo for that) Create GDSii stream by export stream; save or load Template file: StreamOutTemplate; Output file: threff.gdsii Create gdsii stream for layers: TCAPA, GBORG GAA (are not exported in previous stream but are needed to reread and check again. User defined data: layer defined map: strminout.map strminout.map contains: TCAPA drawing 52 0 GAA drawing 51 0 GBORC drawing Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

7 Output file: threeff_slayer.gdsii To check gdsii files, read both files into 2 new libraries. Open a new cell view and put both layers into it and check again. Read in threeff.gdsii into library ibmdesignflow_test_in; dump technology library into an ASCII file first, then import: template file: StreamInTemplate; input file: threeff.gdsii; library name: ibmdesignflow_test_in; Open another library for the special layer gdsii and repeat import process, it might be necessary to include the strminout.map file. Open a new cell and insert both layouts on top of each other (use q to align) and perfrom DRC and LVS (extraction: flat). 6.0 Create a combined sdf using pearl. Use macro write_sdf.cmd to write convert the spdf file to sdf which can be used for verilog backannotation. Call pearl with pearl -gui (source ~/.cshrc_dsm) Use macro read_sdf.cmd cmd>clock -domain c1 -cycle_time 12 I/Out 0 6 cmd>findclockpath cmd>help cmd>timingverify cmd>blockdevice... cmd>showdelayannotationsummary -show_all > tmp cmd> findslownodes cmd> showpossibility cmd> findpathsfrom clk rise_time not specified in CERNLIB1.tlf (cmd> clock -cycle_time 16n clk 1n 1n) cmd> writesdfdelays -precision 3 -ns threeff_pearl.sdf (encodercimt_pearl.sdf) or cmd> writesdfdelays -precision 3 -ns -version 2.1 threeff_pearl_sdf2.1.sdf (encodercimt_pearl.sdf) Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

8 7.0 Read back sdf file from pearl into design_analyzer Attention: if a E_dff_SR_SC is used for instance instead of a AND gate in front of a normal flip flop the timing report does not see violations if the SE signal comes too late! read_sdf -max_type sdf_max -worst threeff_pearl_2.1_manuallychanged.sdf (change in gcf file: T has no influence, V no or little, P has big influence) 8.0 VERILOG simulation (standalone) command is: /vlsicad/cad_solaris/artist97a/tools/verilog/bin/verilog -y /vlsicad/vlsilibs/ibm_cern/ CMOS6SF/9910a/verilog/vdd_2.5v/ /homedir/akluge/glink/behavioral/encodercimt/ test_encodercimt.v +libext+.v+ +maxdelays +gui +s(for interactive mode) to invoke simulator with graphical user interface. It works for both pre synthesis and post syntesis simulation. No backannotation has been performed with this command. Simulation is also possible within icfb, however the options noted above must be set in setup > simulation > more. With the command: $sdf_annotate("/homedir/akluge/glink/ encodercimt_routed_bus.sdf",ecmit,,,,,"from_mtm"); backannotation was conducted. and SET VAR BUS.CHARACTER.SUBSTITUTION.PAIR "<>" ; however errors occur since the E_DFF_SR_SC flip flops are not correctly backannotated. 9.0 Analog simulation (Should also work with new version Make sure version 97a is running.) Open a new cell view schematic test_threeff for the simulation setup. Instantiate the device under test and instantiate vdc, vdd and gnd for supply voltages froma analog_lib. Instantiate vpulse gnd res, and vdd, and vdc for input signals and biasing. (time example 100n after tab) Connect pins for outputs and inputs. Name signals. Check and save. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

9 Make sure.cdsinit exists in run directory. Copy the CornerN* files. Tools => Analog Artist. Setup => Simulator/Dir/Host. Change ~/simulation for./simulation. Replace cdsspice for HSpice => OK. Setup => Temperature => 25/125/... Setup => Model Path => Click delete existing => OK. Setup => Environment => Include file CornerNP0 (for typical sigma = 0, for worst CornerNP-2 sigma = -2) Analyses: check transient and fill out from x to x by x. Technology file => attach to => CERNLIB1 Session => Save state as NP0. In case in the schematics variables have been used for instance for vdd => Variables => Edit... Start simulation by clicking on the green traffic light. Tools => Calculator => vt, click on signals in schematic. Check display stack, click app so that all signals are in the top field. Click erplot (erase plot), in the wave view click last but one field to separate signals views. Use cursor A and B to measure time Extract the capacitive parasitics Make sure display.wrf exists start icfb in the old version. Open the layout/abstract view. Make sure Instance is selected => Select all components. Floorplan => Replace view => Layout Save. Tools => Layout Verify => Extract Rules Lib cmos6sf25techlib. Set switches: cntr + Cap Extract (not for LVS), 3metals, mztop, either farinter or closeinter (make sure diva.rul file exists) New view: extracted. extraction: flat verify LVS => Run => Info => Logfile. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

10 Open schematic view and make sure extracted view is still open. Start Analog Artist => setup => environment.. as above but add extracted to the switch view list as first entry. Click edit on the device under test in the schematic view of the test setup and see that default is extracted. Run simulation as above SEU_TEST In Setup Simulation: instead of library directory: /vlsicad/vlsilibs/ibm_cern/cmos6sf/9910a/verilog/vdd_2.5 or /vlsicad/micsoft/ibm_ep_kit.23_8/designkits/cmos6sf25deskit_v1.0.1/cmos6sf25/verilog/vdd_2.5v /homedir/toifl/ibm/cernlibseu Other options:+notimingchecks In testfixture include: initial begin include "seu_program.v" end initial begin $shm_probe(test,"ac"); file1=$fopen ("generated_seu_program.v"); #100; $fclose (file1); 12.0 Backannotate with new design kit If clock tree generation has been used in se, then export verilog from se into cadence. Include in simulation option (-a): +neg_tchk Check: continous assignment use libary: /vlsicad/micsoft/ibm_ep_kit.23_8/designkits/cmos6sf25deskit_v1.0.1/ cmos6sf25/verilog/vdd_2.5v Backannotation does not work properly. Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

11 If verilog is used in standalone no errors occur: /vlsicad/micsoft/ic4.43/tools/verilog/bin/verilog /homedir/akluge/glink/gol_tx_rx.run1/ testfixture.new -f verilog.inpfiles -l simout.tmp +tms_incl+ +delay_mode_path +sxl_keep_minimum +caxl -a +libext+.v+ +incdir +hdlfilesdir +sdf_verbose +sdf_nocheck_celltype +neg_tchk +gui -s -y /vlsicad/micsoft/ibm_ep_kit.23_8/design- Kits/cmos6sf25DesKit_v1.0.1/cmos6sf25/verilog/vdd_2.5v -y /homedir/toifl/ibm/serializerandpll -v /homedir/toifl/verilog/syn/hamming.v -v /homedir/akluge/glink/ glink_my_common/vdd.v -v /homedir/akluge/glink/glink_my_common/vss.v 13.0 Using the pixel chip model Kens library is in: /homedir/kwyllie/ibm/kostaslib/verilog/ Standard lib is in: /vlsicad/micsoft/ibm_ep_kit.23_8/designkits/cmos6sf25deskit_v1.0.1/cmos6sf25/verilog/vdd_2.5v Design Flow for a ASIC design in the rad hard CERN-IBM librarymay 21,

Place & Route: Using Silicon Ensemble

Place & Route: Using Silicon Ensemble Introduction In a typical digital design flow, hardware description language is used to model a design and verify desired behavior. Once the desired functionality