# Austin Herring Recitation 002 ECE 200 Project December 4, 2013

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1 1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh map for S was as follows: C in AB-> This K-map revealed that S, in sum-of-products form, cannot be simplified beyond its four basic minterms and that in product-of-sums form it cannot be simplified beyond its four basic maxterms either. Because the costs for AND/OR gates (and NAND/NOR gates for that matter), in terms of both time and money, are equivalent, it did not matter if minterms or maxterms were used from this point forward. Ultimately, it was decided that the minterm expression would be used: S = ABC in + AB C in + A BC in + A B C in Next, the K-map for C out was created: C in AB-> Using these three prime implicants, a minimized sum-of-products expression for C out was created: C out = AB + AC in + BC in The K-map also revealed that the minimized product-of-sums form would also contain three terms, and, per the reasoning above, either of these expressions could be used equivalently going forward. Again the sum-of-products form was chosen. After deriving these expressions for S and C out, the idea of factoring out terms (so that S might become, for example, A(BC in + B C in ) + A (BC in + B C in )) was played with, but this ultimately only increased the number of operations which would have to be performed in sequence, eliminating possibilities for parallelism and thus increasing runtime. In light of this, the best way to create these circuits was to directly translate them to gates from the derived expressions. To begin with, S needed to have the complements available for all three inputs, so three NOT gates were required directly on the inputs as they came in. From there, S needed four three-input AND gates with inputs A, B, and C in ; A, B, and C in ; A, B, and C in ; and A, B, and C in, and the outputs of these AND gates needed to be OR d together. Because there were no four-input OR gates available, this could have been done one of two ways: three of the outputs could have been OR d together with a three-input OR gate and then that output could have been OR d with the last AND output with a two-input OR gate; or two of the AND outputs could have been OR d together at a time with two two-input OR gates, and the results from these ORs could have been put through a final two-input OR gate. The second case turned out to be the faster option, because the final two-input OR gate did not have to wait for a three-input OR gate, which takes longer than the two two-input OR gates, which can act in parallel. At this point, the circuit for S looked as follows:

2 At this point, it was realized that if each input into the AND gates was NOT d, these combinations of gates could be replaced for the quicker, yet equivalent, NOR gates. To do this, each input line to the ANDs would require that NOT gate and another NOT gate so that the overall expression would remain equivalent. For example, the topmost gate would require inputs (A), (B), and (C in ). Therefore once the ANDs were replaced with NORs, one NOT would remain: A, B, and C in. This meant that the inputs to the AND gate simply had to be switched from the straight version to the NOT d version. It turns out this is the case for all four AND gates: switch the NOT d inputs to the straight inputs and the straight inputs to the NOT d versions. Then switching the ANDs to NORs leads to an equivalent expression. Finally, the two sets of OR gates on the right-hand side could be converted to NORs and a NAND, which are faster, by placing a NOT gate after the output of the first two ORs and two more NOT gates before the inputs to the final OR gate. Therefore the two OR gates acting in parallel became NOR gates, and, by DeMorgan s theorem, the final NOR became a NAND, all while still remaining equivalent. Next, as was first done with S, C out was translated directly to circuitry from its minimized expression. It required three two-input AND gates which had inputs A and B; A and C in ; and B and C in. Finally, these three AND outputs were OR d together using a three-input OR gate. The circuit then looked as follows:

3 The time for C out could be decreased by NOT ing the output of each AND gate and then NOT ing these three signals again before they reach the OR gate at the right. Therefore all three AND gates and, by DeMorgan s theorem, the OR gate could be replaced by NAND gates, which are quicker than the older gates. b. Final Schematic

4 c. Calculation of Cost S: 1-input NOT: 3 x \$0.01 = \$ input NOR: 4 x \$0.03 = \$ input NOR: 2 x \$0.02 = \$ input NAND: 1 x \$0.02 = \$0.02 Total = \$0.21 C out : 2-input NAND: 3 x \$0.02 = \$ input NAND: 1 x \$0.03 = \$0.03 Total = \$0.09 Total cost = \$ \$0.09 = \$0.30 d. Calculation of Speed The circuit for S can be thought of as acting in four phases in which several actions occur in parallel. Because all of the components acting in parallel in a given phase are of the same gate type, the time for each phase is simply the amount of time for the gate used in that phase. The first phase is when the inputs are all NOT d. The second phase is the NOR ing of the inputs and their complements together to create the minterms. The third phase is the NOR ing of the NOR outputs. The final phase is NAND ing the last two NOR outputs. Phase 1: time to NOT a variable = 8 ns Phase 2: time to NOR three inputs = 12 ns Phase 3: time to NOR two inputs = 8 ns Phase 4: time to NAND two inputs = 8 ns Total time = = 36 ns Similarly, the C out circuitry occurs in two phases, the first NAND stage and the second NAND stage: Phase 1: time to NAND two inputs = 8 ns Phase 2: time to NAND three inputs = 12 ns Total time = = 20 ns e. How Design Is Fastest As discussed above in part 1a, the fastest way to create the circuits using AND and OR gates was to directly translate the minimized expressions into circuits (because factoring out variables only increased the number of operations, the number of gates, and the time). However, after creating the circuits with AND and OR gates, it was possible to speed it up by switching all of those gates out for NANDs and NORs. Therefore it would be impossible to create a quicker circuit using AND and OR gates. It is also

5 impossible to eliminate any of the NAND and NOR gates from the final design (or the initial NOT gates), so the provided circuit must be the quickest possible made of NANDs and NORs. As for the other component types, the only two which are quicker than S on their own are the 2x4 decoder and the 4x1 multiplexer, both at 35 ns. (None are quicker than C out, so there is no way to calculate C out more quickly with these other components.) However, both of these components would require at least one NOT gate to be used for the S output, which would place the overall time at 43 ns, greater than that for the provided design. 2. Cheapest Circuit a. How Design Was Obtained Examining the truth table for S, it was noticed that when A and B are both 0, S is equivalent to C in ; when they are 0 and 1, respectively, S is equivalent to C in ; when they are 1 and 0, S is equivalent to C in ; and when they are both 1, S is equivalent to C in. This meant that a 4x1 multiplexer could be used, with A and B as the select lines and the specified versions ( straight or NOT d) of C in as the input lines, to create circuitry for S. As described above in 1a, the minimized expression for C out is AB + AC in + BC in. For the purposes of cost, factoring out one of the variables turns out to be beneficial; the new expression retained the same number of operations, but instead of requiring a final three-input OR gate, all of the gates became twoinput gates, which reduced the cost. Therefore C out, for creating this circuit, was thought of as: AB + C in (A + B) This expression was translated into gates for the circuit below. b. Final Schematic

6 c. Calculation of Cost S: 1-input NOT: 1 x \$0.01 = \$0.01 4x1 multiplexer: 1 x \$0.10 = \$0.10 Total = \$0.11 C out : 2-input AND: 2 x \$0.01 = \$ input OR: 2 x \$0.01 = \$0.02 Total = \$0.04 Total cost = \$ \$0.04 = \$0.15 d. Calculation of Speed S occurs in two phases: C in is first NOT d, and then all three inputs are run through the multiplexer. Phase 1: time to NOT a variable = 8 ns Phase 2: time for 4x1 multiplexer = 35 ns Total time = = 43 ns C out occurs in what are essentially three phases. In the first, A and B are run through the AND and OR gates to which they are attached. In the second phase, C in is AND d with A + B. Finally, AB and C in (A + B) are OR d. Phase 1: time to AND/OR two inputs = 10 ns Phase 2: time to AND two inputs = 10 ns Phase 3: time to OR two inputs = 10 ns Total time = = 30 ns e. How Design Is Cheapest To create equivalent circuitry for S and C out with decoders, either a 3x8 decoder or two 2x4 decoders would be required, and both of these options cost \$0.20, more than the cost of the provided design. Similarly, the 8x1 multiplexer immediately costs more than the provided design at \$0.20. Therefore the only possible way to create a cheaper design would be through the use of AND, OR, NAND, and NOR gates. Any NAND or NOR gate can be converted to an AND/OR followed by a NOT at the same cost, however, so, in reality, the only way to create a cheaper design would be to use ANDs and ORs. C out is already in terms of ANDs and ORs, and it is already as cheap as it can be. Though it could be created in different ways for the same cost, it is impossible to eliminate any more gates; the expression AB + C in (A + B) cannot be manipulated in any way to eliminate literals or expressions through factoring. This leaves only S to possibly be simplified further. None of the expressions provided for S so far have directly equivalent circuits which are cheaper than the provided design. For example,

7 (ABC in + AB C in ) + (A BC in + A B C in ) ABC in + (AB C in + A BC in + A B C in ) A(BC in + B C in ) + A (BC in + B C in ) are all more expensive designs when they are translated to gates. However, through algebraic manipulation of the expression ABC in + AB C in + A BC in + A B C in, first by factoring C in out of the middle expressions and C in out of the outer ones and then by distributing OR over AND in the expressions that were just factored, it is possible to create the expression: C in (A + B )(A + B) + C in (A + B )(A + B) This expression would normally require NOT gates for the three inputs, costing \$0.03; four two-input OR gates for the expressions of A and B, costing \$0.04; two three-input AND gates, costing \$0.04; and one final two-input OR gates for the AND d expressions, costing \$0.02. This would mean a total cost of \$0.12. However, A + B is a term this expression shares with C out, eliminating the need for one of the two-input OR gates and bringing the cost down by \$0.01. This is the cheapest possible way to represent S using AND and OR gates, and it brings the cost down to \$0.11, the same as the provided design. However, because the provided design is much simpler as well as slightly faster than the AND/OR design, it is still the overall better choice. 3. Best Circuit a. How Design Was Obtained For the best possible circuit, the circuitry for the cheapest option of S will be re-used. However, C out will not use circuitry from either the fastest of cheapest design. Instead, it will try to straddle the line between the two by using the first circuit provided for C out in part 1a, the expression AB + AC in + BC in translated into gates. b. Final Schematic

8 c. Calculation of Cost S as above: Total = \$0.11 C out : 2-input AND: 3 x \$0.01 = \$ input OR: 1 x \$0.02 = \$0.02 Total = \$0.05 Total cost = \$ \$0.05 = \$0.16 d. Calculation of Speed S as above: Total time = 43 ns C out : Phase 1: time to AND two inputs: 10 ns Phase 2: time to OR three inputs: 15 ns Total time = 25 ns e. How Design Is Best The design provided here provides an excellent balance between cost and timing. The S option is the cheapest one available for only a small sacrifice in timing. There are only a few ways to build circuits for S that are faster than (or the same speed as) this design, but, because most of them use NAND and NOR gates, they are more expensive. For comparison, the design is only 7 nanoseconds slower than the fastest design, but it nearly halves the price of that design (\$0.11 versus \$0.21). Moreover, this design is very simple, being made up of only a single NOT gate and a multiplexer. The outputs can be determined in seconds while looking at it, and it would likely be easier to put together and less prone to failure. The choice made for C out is the best because it, again, shows a balance between speed and cost. While the fastest design takes only 20 nanoseconds, it costs \$0.09; and while the cheapest design costs only \$0.04, it takes 30 nanoseconds. For just a single cent more, at \$0.05, the provided design can speed up the cheapest design to 25 nanoseconds. While this is not quite as fast as the 20 nanosecond design, it is about the half the cost of that design, which is a fair trade off for about 5 nanoseconds slower. Because these designs can provide both outputs relatively fast, all while doing it for only one cent more than the cheapest possible circuit combination, this is likely the best circuit design and the one that the company should go with.

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