Final Report For CIF Project Redevelopment of Course Materials for EE 4750
|
|
- Gregory Terry
- 6 years ago
- Views:
Transcription
1 Final Report For CIF Project Redevelopment of Course Materials for EE 4750 Submitted by Gang Feng Department of Electrical Engineering Summary EE4750 (Advanced Digital Design) and EE4720 (Computer Architecture) are the two courses that electrical engineering (EE) students must take in order to graduate in computer emphasis. Due to some historical reasons, there are a lot of materials overlapping between the two courses. In addition, the curriculum rearrangement in the last a couple of years and the advance of new technology in digital circuit area make it imperative (in my opinion) to add much more new contents to EE4750. As such, I propose to redevelop the course materials centered at the adoption of a new circuit development board that uses the latest FPGA (field programmable gate array) technologies. Completed Works Lecture Notes 1) Review materials for EE4750 Attachment 1 includes the review materials for EE4750 that will be covered during the first two lectures. These materials make sure the students have the required knowledge of digital circuit for this course. 2) VHDL lecture notes using ModelSim In previous semesters, VHDL was taught using Altera s software Quartus or Maxplus+II. During this project, these lecture notes were redeveloped using the ModelSim software. Figure 1 shows an example that includes the simulation result obtained from ModelSim. Figure 1. A slide developed using ModelSim software 1
2 3) ModelSim simulation lecture notes A power point file has been developed to teach how to use the ModelSim software. Figure 2 is an example of the slides. Figure 2. A slide developed for teaching ModelSim software 4) A quick-start instruction sheet has been developed to help the students learn how to use Xilinx Project Navigator software. See Attachment 2. 5) VHDL test bench lecture notes A power point file has been developed to teach how to write VHDL test bench. An example slide is shown in Figure 3. Figure 3. A slide developed for teaching VHDL test bench 6) A power point file has been developed to teach how to use Spartan-3 memory modules. See example slide in Figure 4. 2
3 Figure 4. A slide developed for teaching Spartan-3 memory modules 7) A power point file has been developed to teach how to design 8051 CPU using VHDL and Xilinx Spartan-3 board. An example slide is shown in Figure 5. Notice the 8051 CPU design schematic has been tested on the Spartant-3 board. Figure 5. A slide developed for teaching how to design an 8051 CPU using VHDL 8) A power point file has been developed to teach how to use the RS-232 port on the Spartan-3 board. See Figure 6 for example slide. Notice that the schematic has been tested on the board. 9) A power point file has been developed to teach how to use the external fast asynchronous memory on the Spartan-3 board. See Figure 7 for example slide. Notice that the schematic has been tested on the board. 3
4 Figure 6. A slide developed for teaching how to use the RS-232 port on Spartan-3 board Figure 7. A slide developed for teaching how to use the asynchronous memory on Spartan-3 board 10) A power point file has been developed to teach how to write test bench in Verilog. See Figure 8 for example slide. 11) Several files have been developed to teach how to use the VGA display on Spartan-3 board. See Figure 9 for example slide. 4
5 Figure 8. A slide developed for teaching how to write test bench in Verilog Figure 9. A slide developed for teaching how to use the VGA display on Spartan-3 board NOTE: (1) A total number of 20 Power Point files have been redeveloped based on the ModelSim software and Xilinx Spartan-3 board. Each file contains as many as 30 slides. These documents take a total of 60MB disk space. It s impossible to include all of these materials in this report, but all of these documents are available to any UWP employee upon request. (2) The original plan for this CIF project includes development of materials regarding FPGA based DSP implementation. However, after careful consideration, I feel such materials do not quite fit in this course. Instead, I decided to develop some materials for how to design asynchronous digital circuit. See Attachment 3. 5
6 Lab Project and Homework Assignments 1) Lab projects #2 and #3 have been redeveloped due to change lecture notes and development board to be used. See Attachment 4. 2) Homework assignments have been redeveloped due to change of lecture notes and textbook. See Attachment 5. Sharing of Work with Colleagues The developed materials will be shared with the colleagues in EE department during a department meeting in September All of these materials will be posted on a share drive accessible to EE faculty members (pending the availability of disk space). Conclusion This report demonstrates a successful completion of the CIF project. As a matter of fact, this project took much more time than what was originally planned in the proposal. I expected the materials developed in this project significantly improve the quality of teaching EE4750. Acknowledgement I would like to thank the CIF committee for giving me this opportunity to work on this project. 6
7 Attachment 1: Review Materials # Boolean Identities (1) X + X = 1, XX = 0, X+X = X, XX = X (2) X(Y+Z) = XY + XZ (distribution law), X + YZ = (X+Y)(X+Z) = X + XZ+ XY + YZ = X(1+Z+Y) + YZ (3) Prove XY + X Z = (X+Z)(X +Y) = XY+X Z+YZ = XY + X Z + YZ(X+X ) = XY+XYZ+X Z+X ZY=XY+X Z (Consensus theorem) (4) DeMorgan s laws: (X1+X2+ + Xn) = X1 X2 Xn (X1X2 Xn) = X1 + X2 + + Xn. (5) X 0 = X, X 1 = X, (X Y) = X Y = X Y = XY + X Y = X Y. Example: Simplify (A+BC)(D+E ) + A (B + C )(D+E ) # K-MAP Location of minter determined by the arrangement of variables: (Answer: D + E ) Minterm: A product term that consists of all variables. Prime Implicant : A product term obtained by combining the maximum number of 1 s 7
8 Essential Prime Impicant : If a 1 is covered by only one prime implicant, it is essential. Simplification of logic functions with 5 or more variables Partial truth table of a 6-variable function: A B C D E F G X X X X X x x x x x x x x x X x x x x X x x 1 G(A, B, C, D, E, F) = m0 + m2 + m3 + Em5 + Em7 + Fm9 + m11 + m15 + (don t cares) = Σm(0, 2, 3, 11, 15) + Σd(1, 10, 13) + E(m5 + m7) + Fm9 Form a KMAP of variables A, B, C and D, and enter the variables E and F inside the map. Suppose a 4-varaible map has variables P1, P2, entered into some squares. Find a sum-of-products expression of the form F = MS0 + P1 MS1 + P2 MS2 + where, 8
9 MS0: minimum sum by setting P1 = P2 = = 0 MS1: minimum sum by setting P1 = 1, Pi = 0 ( i 1) and replacing all 1 s in the map with don t cares. MS2: minimum sum by setting P2 = 1, Pi = 0 ( i 2) and replacing all 1 s in the map with don t cares. With the previous example, the above method would give us G= A B + ACD + EA D + FAD # Typical Combinational Circuits Full Adder X Y C in Co ut Su m X Y + Cin Cout Sum 4-1 MUX 9
10 # Latches & Flip-Flops Latches (1) Clocked SR latch (2) D latch Q + = D 10
11 FFs: State changes occur only at active edges (rising or falling edge) (1) DFF (2) SRFF (same as SR latch except a triangle is added) (3) JKFF (falling edge triggered) O >CLK O.W. (4) TFF (rising edge triggered) >CLK O.W. # State Machine Mealy machine vs. Moore Machine 11
12 State machine design Example 1: Sequence detector Use DFFs to design a sequence detector to identify input sequence
13 13
14 Example 2: convert BCD digit to excess-3 coded decimal digit 14
15 Assumption: Only one bit is inputted in each cycle (starting from the LSB); one bit is outputted in each cycle. Hint: At each cycle, there are two different states: (1) there is a carry from previous cycle; (2) there is no carry from previous cycle. 15
16 Attachment 2: Xilinx Project Navigator Quick Start 1. File New Project. Choose the folder where you want to save the project. 2. In the Project Navigator window (upper left), right click on the project title; this allows you to add existing files and create new sources. 3. You should see all of those files in the project navigator window. Click on any of this source file, the lower left window shows all the process that you can operate on that source file. 4. Now click Create Schematic Symbol. The symbol created can be included in an upper level schematic design file. 5. When making schematic file, you can include symbols of instances or basic logic gates. The pins of each block must be connected to wires (use Add wire icon). The wires can be named using the Add net name icon. Same for single-bit signal and bus. The bus index is given by (x:y). A portion of the bus can be referenced by specifying the index range. NOTE: (i) (ii) The GND and VCC symbols are available in the "General" category in the "Symbols" pane in the schematic editor. Click on schematic file and then click on the View VHDL Functional Model allows you to view the VHDL model of a schematic. 6. Once all files have been put together, you can click Assign Package Pin in Process View window. This allows you assign the I/O to specific pins. The best way to do this is type the location directly. Notice this step will generate Constraints file. After creating this file, if you need to change a pin name in the schematic, you need to edit the Constraints file (click Edit Constraints (Txt) ). Alternatively, you can delete the old file and click Assign Package Pin to create a new one. NOTE: (i) (ii) If a bus is used in schematic design, it is required to assign all of them or none of them to ports. Without performing pin assignments, the pin will be automatically assigned. The Pad Report is available under Place and Route directory in Process View. 7. After the pins are assigned, you can generate the programming file by clicking Configure Device (impact). This pops up a window; use the default Boundary scan, and it should automatically locate two chips in tandem. Choose the corresponding bit stream file for each chip (chip can be bypassed if programming is not needed). Click Operation menu in the impact window and choose Program (you must click on the corresponding device before doing this). The chip should be programmed successfully. Sometimes it may take two tries for a success. When programming the board, the jumpers should not be changed. 8. Any file belonging to a project can be compiled, simulated and tested individually. For instance, after you click on certain file, the process view (lower left) can show what processes you can operate on, including ModelSim (for simulation), Assign Package Pin, Configure Device, etc. 16
17 Attachment 3: Xilinx Project Navigator Quick Start # Asynchronous Sequential Circuit Analysis Sync. Seq. Circuit (state machine): state transition is controlled by clock signal. Async. Seq. Circuit: (1) State transition is solely controlled by inputs. (2) An input change should not be applied before the circuit stabilizes due to a previous input change (just like a state machine requires a maximum clock cycle). Example 1: Async. Seq. circuit with an SR latch (not SRFF). Goal: Given a sequence of inputs (we always assume the input changes one at a time), how can we find the sequence of outputs? (1) Next state and output equations: Q1 + = S1 + R1 Q1 = X1X2 + (X1 + X2)Q1 Q2 + = S2 + R2 Q2 = X1X2 + (X1 + X2 )Q2 Z1 = Q1Q2 + X1 (Q1 + Q2) Z2 = Q1Q2 + X2 (Q1 + Q2 ) (2) Compute State Transition Table: Next state is computed using the equations derived in step 1. Present total state: X1X2Q1Q2; Internal State: Q1Q2. A total state might be stable or unstable. 17
18 If present internal state is the same as next internal state, the corresponding total state is stable. Circled states are stable states; others are unstable states. A change of input corresponds to change of column without any row change; if the new state is unstable, a row change takes place until a stable state is reached. Since before a stable state is reached, the circuit might go thru some unstable state, the state table is often called flow table. There is not necessarily at least one stable in each column (as illustrated by the CYCLE example) (3) Flow table and Output table: (This figure illustrates the concepts of internal states and total states) Flow table Output table With the input sequence: The output sequence is The corresponding timing diagram can be drawn based on the above analysis: 18
19 Example 2: Asynchronous Gate Network. Most important thing is to open the loops; define the output before the delay as next state; delayed outputs become present state. Two methods: (1) Open lower-left corner, middle, and the final output (2) Open lower-right corner, and final output. The corresponding equations (for the following circuit) are: 19
20 (Notice that figure (c) is internal state transition table, rather than total state table) Input sequence in the example is: 00, 01, 11, 10. Example 3: How to open the loop? 20
21 Requirement: Use the minimum number of cuts to open all the loops ( a loop exists if the output of a gate can be fed back to the input of the same gate through some path). Answer: cut at c, d, a or c, d, b. # Cycles and Race Conditions: Example 4: Cycle For the following circuit, if Q1Q2 are at 00 state, and X changes from 0 to 1, the circuit would cycle through a series of unstable states. It would never reach a stable state unless X changes back to 0. Example 5: Race condition If X changes to 0 when Q1Q2 = 10, it requires Q1Q2 changes back to 01. There is a race condition since one latch might change faster than the other. The following figure illustrates all possibilities. 21
22 Noncritical race vs. Critical Race If the resulting stable state is the same no matter in what order the latches change, it is called a noncritical race. If it is possible to end up in two or more different stable states depending on the order in which the flip-flops change state, it is a critical race. Example 6: Critical Race (Suppose initial state is 00, X changes to 1, requiring both Q1 and Q2 change) # Derivation of Primitive Flow Tables o o o o o Primitive flow table: exactly one stable total state per row. The table can be reduced to fewer rows. For most problems it is necessary to start with constructing the primitive flow table, rather than constructing reduced table directly. Assumptions: (1) only one input variable changes at a time (2) Each input change must reach a stable state. 22
23 EXAMPLE 7 An asynchronous network has two inputs and one output. The input sequence XI X2 = 00,01, 11causes the output to become 1. The next input change then causes the output to return to 0. No other input sequence will produce a 1 output. Step 1: Step 2: Notice that when input change from 10 to 11, it can not go to state 4. Step 3: (The output is always associated with stable state. There should be only one stable state in each row.) The corresponding state diagram: 23
24 EXAMPLE 8 Design an edge-triggered clocked T flip-flop, which has two inputs, T and P. The flipflop will change state if T = 1 when the clock (P) changes from 1 to 0. Under all other input conditions, Q should remain constant. We will assume that T and P do not change simultaneously. (Note that the output (Q) only changes when the input changes from TP = 11 to 10) 24
25 Attachment 4: Lab Project Assignments EE 475 Lab Project #2: Synchronous Serial Peripheral Interface Design 1 Specification Presentation on Oct. 26, 2007; Report Due Oct. 29, 2007 Design a synchronous serial peripheral interface (SPI) as described on page in the textbook (Digital Systems Design using VHDL by Roth & John). To accomplish this design, carefully read the description in the textbook to make sure you fully understand the requirements. The whole system should be described in VHDL except for the top-level design, which can be described using schematic. The whole system should be broken down to small components, each of which can be put in a single VHDL file. A recommended schematic is shown in Figure 1. MOSI Sysclk CLK rate generator SPR(1:0) SCK_in SPSHR SPDR ENm LDm RDm DB Master MISO SCK SPSHR SPDR ENs LDs RDs DB Slave MOSI MISO SCK SPI Controller DB SPCR SPSR DB WR RD INT Addr(1:0) Figure 1. A schematic for SPI Most signals in this schematic are self-explanatory except a few: ENm : master enable; MOSI and SCK from master should output Hi-Z if disabled. LDm: Load master; the data on the data bus (DB) is written in SPSHR if LDm is 1. RDm: Read master; the data in SPDR is sent to the DB if RDm is 1. There is a similar set of signals (ENs, LDs, and RDs ) for the slave. 25
26 Addr(1:0), WR, and RD are used to write to or read from the registers SPCR, SPSR, SPSHR, and SPDR.. You are encouraged to implement your own unique design. 2 Testing and Demo Each component must be tested using a test bench to make sure the logic is correct. The overall schematic should be tested using behavior modeling and post place & route modeling, respectively. Notice the behavioral modeling conceptually verifies the design, while the post place & route modeling simulate the design using the actual gate delays. The design should be downloaded to FPGA. The on-board LEDs, seven-segment displays, push buttons and switches can be used in your design for demonstration purpose. During check off, you are supposed to present the following: (1) Behavioral modeling simulation result (2) Post place & route modeling simulation result (3) Demo on the development board Successful accomplishment of the behavioral modeling is needed for you to get a grade C or better. Your final grade depends on how much you can accomplish and how unique your design can be. 3 Report (1) Objective (2) Procedure: Explain how you approach and complete the lab. Please include an ASM chart for the master and slave components, the simulation results, and schematic. The simulation results should be briefly explained. (3) Discussion: Discuss any experience you achieved from this project. (4) The report should be written as formal as possible, e.g., any Figure/Table must have a caption, partition a section into several subsections if there is too much information, etc. EE 475 Lab #3: 8051 CPU Design 1 Objective Presentation: Nov. 16, 2007, Report Due Nov. 19, 2007 The objective of this laboratory project is to design a CPU that implements a subset of the Intel 8051 microprocessor instruction set. 2 Specifications Follow the flow chart discussed in class to design the 8051 CPU (Different implementations are allowed if you have better ideas). Basic requirements: 26
27 (1) All the instructions shown in the flow chart must be implemented (2) The op code must be compatible with Intel 8051 processor (3) A ROM must be used to store the program code (4) A RAM must be used to support instructions accessing internal RAM (5) Simulation of each category of instruction (6) The program code should be generated by compiling an 8051 assembly program using any valid 8051 compiler. Additional requirements: (7) Implement an additional category of instructions. For instance, MOVX instructions (an external RAM block is needed), PUSH/POP operations (SP register must be implemented as well), LCALL / RET operations, etc. (8) Demo your design on the development board Successful accomplishment of basic requirements is needed for a grade of C or better. Your final grade depends on how much you can accomplish and how unique your design can be. 3 Report (5) Objective (6) Procedure: Explain how you approach and complete the lab. Include an ASM chart for the additional category of instructions, and the simulation results of typical instructions. (7) Discussion: Discuss any experience you achieved from this project. (8) The report should be written as formal as possible, e.g., any Figure/Table must have a caption, partition a section into several subsections if there is too much information, etc. (9) Attach the assembly program used to test your design. 27
28 Attachment 5: Homework Assignments EE 4750 HW #1 Due Sept. 17, 2007 Textbook Chapter 1 Problems: 1, 2, 4(b), 9, 10, 11(a)(b), 14(a)(b), 19, 22 NOTE: Ignore the NOR-gate implementation for 11(b) and 14(b). EE 4750 HW #2 Due Sep. 26, 2007 Textbook Chapter 2 Problems: 5, 6, 8, 11, 25. (Simulations required for problems 5, 6, 11). EE 4750 HW #3 Due Oct. 10, 2007 Textbook Chapter 2 Problems: 12, 23, 30, 32, 39 (Simulation results are required for each problem). EE 4750 HW #4 Due Oct. 17, 2007 Textbook Chapter 3 Problems: 5(a), 9, 14 Textbook Chapter 6 Problems: 2, 5, 10 28
29 EE 4750 HW #5 Due Oct. 31, 2007 Use CORE generator to generate the following memory modules and then make a test bench and perform simulation for each module: 1. Distributed RAM (1K bytes); Read and Write; non-registered 2. Distributed RAM (1K 16-bit words); Read only; non-registered 3. Block RAM (2K bytes); Read and Write; non-registered input 4. Block RAM (2K bytes); Read only; non-registered input EE 4750 HW #6 Due Nov. 12, 2007 Rework HW#3 in Verilog; Simulations are required. EE 4750 HW #7 Due Nov. 31, 2007 Textbook Chapter 10 Problems: 1, 3, 11, 18 29
SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review
More informationDIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More information< W3150A+ / W5100 Application Note for SPI >
< W3150A+ / W5100 Application Note for SPI > Introduction This application note describes how to set up the SPI in W3150A+ or W5100. Both the W3150A+ and W5100 have same architecture. W5100 is operated
More informationLast Name Student Number. Last Name Student Number
University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Midterm Examination ECE 241F - Digital Systems Wednesday October 13, 2004, 6:00pm [5]
More informationFPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed
More informationEvolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationSoftware Engineering 2DA4. Slides 2: Introduction to Logic Circuits
Software Engineering 2DA4 Slides 2: Introduction to Logic Circuits Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital
More informationRedundant States in Sequential Circuits
Redundant States in Sequential Circuits Removal of redundant states is important because Cost: the number of memory elements is directly related to the number of states Complexity: the more states the
More informationR07
www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More information: : (91-44) (Office) (91-44) (Residence)
Course: VLSI Circuits (Video Course) Faculty Coordinator(s) : Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Chennai 600036 Email Telephone : srinis@iitm.ac.in,
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationEPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
More informationThe QR code here provides a shortcut to go to the course webpage.
Welcome to this MSc Lab Experiment. All my teaching materials for this Lab-based module are also available on the webpage: www.ee.ic.ac.uk/pcheung/teaching/msc_experiment/ The QR code here provides a shortcut
More informationEE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 621213 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS SEMESTER III SUBJECT CODE: EC2203 UNIT 5 : Synchronous and Asynchronous Sequential
More informationEND-TERM EXAMINATION
(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationdiscrete logic do not
Welcome to my second year course on Digital Electronics. You will find that the slides are supported by notes embedded with the Powerpoint presentations. All my teaching materials are also available on
More informationLab Manual for COE 203: Digital Design Lab
Lab Manual for COE 203: Digital Design Lab 1 Table of Contents 1. Prototyping of Logic Circuits using Discrete Components...3 2. Prototyping of Logic Circuits using EEPROMs...9 3. Introduction to FPGA
More informationPART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A
More informationEECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15
1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,
More informationSummer 2003 Lecture 21 07/15/03
Summer 2003 Lecture 21 07/15/03 Simple I/O Devices Simple i/o hardware generally refers to simple input or output ports. These devices generally accept external logic signals as input and allow the CPU
More information2 nd Year Laboratory. Experiment: FPGA Design with Verilog. Department of Electrical & Electronic Engineering. Imperial College London.
Department of Electrical & Electronic Engineering 2 nd Year Laboratory Experiment: FPGA Design with Verilog Objectives By the end of this experiment, you should know: How to design digital circuits using
More informationBUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationCS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationCS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset
More information6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals
More informationSynthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationDesign a three-input, two-output sequential digital circuit which functions as a digital locking mechanism. LOCK ALARM
Department of Computing Course 112 Hardware First Year Laboratory Assignment Dates for the session 2005-2006: Hand out Date: 10 th January 2006 Hand in deadline (electronic and written report): 17.00 Monday
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationFinal Exam Solution Sunday, December 15, 10:05-12:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationENGR 3410: MP #1 MIPS 32-bit Register File
ENGR 3410: MP #1 MIPS 32-bit Register File Due: October 12, 2007, 5pm 1 Introduction The purpose of this machine problem is to create the first large component of our MIPS-style microprocessor the register
More informationE85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design
E85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design Objective The purpose of this lab is to learn to use Field Programmable Gate Array (FPGA) tools to simulate
More informationDigital Design and Computer Architecture
Digital Design and Computer Architecture Introduction Lab 4: Thunderbird Turn Signal In this lab, you will design a finite state machine in SystemVerilog to control the taillights of a 1965 Ford Thunderbird
More informationEET2141 Project 2: Binary Adder Using Xilinx 7.1i Due Friday April 25
EET2141 Project 2: Binary Adder Using Xilinx 7.1i Due Friday April 25 Introduction This Xilinx project introduces the characteristics of the ripple carry adder. From the last project, you learned that
More informationstructure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationHere is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA
More informationSerial versus Parallel Data Transfers
Serial versus Parallel Data Transfers 1 SHIFT REGISTERS: CONVERTING BETWEEN SERIAL AND PARALLEL DATA Serial communications Most communications is carried out over serial links Fewer wires needed Less electronics
More informationLecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration
TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction
More informationProgrammable Logic Design I
Programmable Logic Design I Introduction In labs 11 and 12 you built simple logic circuits on breadboards using TTL logic circuits on 7400 series chips. This process is simple and easy for small circuits.
More informationEECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationQuestion Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
More informationEECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationThe Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven
More informationOutline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
More informationGood Evening! Welcome!
University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers
More informationFPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder
More informationPROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available
More informationTopics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design
Topics of this Slideset CS429: Computer Organization and rchitecture Dr. Bill Young Department of Computer Science University of Texas at ustin Last updated: July 5, 2018 at 11:55 To execute a program
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationExperiment VERI: FPGA Design with Verilog (Part 1)
Experiment VERI: Department of Electrical & Electronic Engineering 2nd Year Laboratory Experiment VERI: FPGA Design with Verilog (Part 1) (webpage: www.ee.ic.ac.uk/pcheung/teaching/e2_experiment /) Objectives
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More informationEECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
More informationGate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,
More informationMemory Supplement for Section 3.6 of the textbook
The most basic -bit memory is the SR-latch with consists of two cross-coupled NOR gates. R Recall the NOR gate truth table: A S B (A + B) The S stands for Set to remember, and the R for Reset to remember.
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester
More informationENGR 3410: MP #1 MIPS 32-bit Register File
ENGR 3410: MP #1 MIPS 32-bit Register File Due: Before class, September 23rd, 2008 1 Introduction The purpose of this machine problem is to create the first large component of our MIPS-style microprocessor
More informationECE 152A LABORATORY 2
ECE 152A LABORATORY 2 Objectives : 1. Understand the trade-off between time- and space-efficiency in the design of adders. In this lab, adders operate on unsigned numbers. 2. Learn how to write Verilog
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004
Goals ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004 1. To review the use of Verilog for combinational logic design. 2. To become familiar with using the Xilinx ISE software
More informationLABORATORY # 6 * L A B M A N U A L. Datapath Components - Adders
Department of Electrical Engineering University of California Riverside Laboratory #6 EE 120 A LABORATORY # 6 * L A B M A N U A L Datapath Components - Adders * EE and CE students must attempt also to
More informationCSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More informationLab 1: Introduction to Verilog HDL and the Xilinx ISE
EE 231-1 - Fall 2016 Lab 1: Introduction to Verilog HDL and the Xilinx ISE Introduction In this lab simple circuits will be designed by programming the field-programmable gate array (FPGA). At the end
More informationDigital Systems Design with PLDs and FPGAs Kuruvilla Varghese Department of Electronic Systems Engineering Indian Institute of Science Bangalore
Digital Systems Design with PLDs and FPGAs Kuruvilla Varghese Department of Electronic Systems Engineering Indian Institute of Science Bangalore Lecture-32 Simple PLDs So welcome to just lecture on programmable
More informationUsing Programmable Logic and the PALCE22V10
Using Programmable Logic and the PALCE22V10 Programmable logic chips (like the PALCE22V10) provide a convenient solution for glue logic and state machine control required by your design. A single PAL chip
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationIE1204 Digital Design L7: Combinational circuits, Introduction to VHDL
IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
More information