Case Studies of All-Surface Inspection in a 3DI-TSV R&D Environment. Rolf Shervey Sr. Applications Engineer Rudolph Technologies, Inc.

Transcription

1 Case Studies of All-Surface Inspection in a 3DI-TSV R&D Environment Rolf Shervey Sr. Applications Engineer Rudolph Technologies, Inc.

2 Equipment in Albany Explorer Inspection Cluster AXi 935 for top surface E30 for wafer edge-bevel B30 for wafer backside Installed in 1 st half of 2008

3 All Surface Inspection Case Studies Defect inspection (pre- and post-bond) Defects at bond interface can break wafers Edge bevel chips/slip can create cleave lines during bonding AXi 935 All-Surface System is used to inspect top, bottom, and edge bevel: Identify defects that will break wafers & impact yield pre-bonder post-bonder before wafer thinning (grinding) 3

4 FRONT-SIDE INSPECTION

5 Misaligned via pattern in BF inspection Images courtesy of SEMATECH AXi inspection of metal viapatterned wafers found misalignment of via pattern. 5

6 All Surface Inspection Case Studies Missing vias Following M1 oxide deposition, missing vias in the alignment marks used for lithography were observed Subsequent inspection revealed multiple missing vias Used the Rudolph Axi935 allsurface inspection tool to gather statistics. Missing vias are ~10X more probable on square vias than on round or octagonal vias Suggests that stress plays a role One single missing VSPM via (1/395,472) was observed on 2 wafers subjected to 150 C anneal Slide courtesy Larry Smith - SEMATECH ½ of a VSPM alignment mark Image and inspection data from Rudolph AXi Missing 46EBL052SJA3; Via Defect 46EBL052SJA3; defect% Density defect% 4x4 (8x8) TSV arrays, 4,5,6 µm diameter; square, octagonal, and round 8x8_5um_P25um_round 8x8_5um_P25um_round 8x8_5um_P20um_round 8x8_5um_P20um_round 8x8_5um_P15um_round 8x8_5um_P15um_round 4x4_4um_P8um_round 4x4_4um_P8um_round 4x4_5um_P10um_round 4x4_5um_P10um_round 4x4_6um_P12um_round 4x4_6um_P12um_round 4x4_4um_P8um_oct 4x4_4um_P8um_oct 4x4_5um_P10um_oct 4x4_5um_P10um_oct 4x4_6um_P12um_oct 4x4_6um_P12um_oct 4x4_4um_P8um_square 4x4_4um_P8um_square 4x4_5um_P10um_square 4x4_5um_P10um_square 4x4_6um_P12um_square 4x4_6um_P12um_square 0% 1% 2% 3% 4% 5% 6% only after CMP 0% 1% 2% 3% 4% 5% 6% 6

7 All Surface Inspection Case Studies Slide courtesy Larry Smith - SEMATECH Missing via failure analysis Top ~3 microns of copper missing in the TSV Stress related Copper anneal modified AXi 935 useful to detect, quantify, and inspect TSV defects Missing via Delamination? 7

8 EDGE-BEVEL INSPECTION

9 E30 System Overview Edge Top Camera Edge Normal Camera Darkfield and Brightfield inspection and metrology Multiple EBR line metrology in zones 1-4 Brightfield color image defect capture driven by darkfield sensitivity Advanced defect binning based on defect attributes Color, intensity, size, area, location, contrast strength, illumination type Bin specific defects can be further classified by an Edge ADC engine High throughput capable up to 100WPH 9

10 Wafer Edge Zones and Defects of Interest 6mm Zone 1 Pattern side Top Edge Bevel Transition Zone 2 Top Bevel ~ ~ Zone 3 Apex Wafer Edge Exclusion (WEE) ~ ~ Zone 1 Typical Inspection Criteria Zones Multi-film 2, 3 & 4 EBR Typical / EEW Inspection Zone Metrology5 Criteria EBR centricity with 0.1 mm resolution Backside Rinse EBR Bottom metrology of Wafer Supported in zones 2-4 Coating Problems, Chips, Cracks, Mechanical Zone Blisters, Residues, Coating Problems Damage 5 Typical Inspection Criteria Particles, Visual defects > 5µm Resolution Mechanical > 4umDamage, Stains Delamination, Peeling, Particles Blisters, > 3µm Delamination, Peeling, Particles > 2µm > 1µm Distance from Apex with 0.1 mm resolution Up to 3600 measurement points possible Wafer Bevel ~ 2-4mm (profile shape dependent) Zone 4 Bottom Bevel 10

11 All Surface Inspection Case Studies Bonded wafer pair re-entry to CMOS fab SEMI M1.15 defines wafer diameter, thickness, notch, bevel edge (100s of parameters ) Bonded, thinned, and edge-trimmed wafers challenge SEMI M1.15 Other SEMI standards affected SEMI E47.1 (FOUP) SEMI M31 (FOSB) SEMI E15.1 Load ports SEMI M1 Notch SEMI T7 Wafer identification Potential issues: Pre-aligner Wafer indexer/mapper Double stack, cross-slot errors Edge bevel scattering Carrier damage to BWP Slide courtesy Andy Rudack - SEMATECH 11

12 Bonded Wafer Pair Metrology & Defect Inspection SEMATECH Phase I Bonded Wafer Pair Mechanical Testing: Edge inspection on E30 successfully completed May 29,

13 Thinned Top Wafer (via wafer) Edge-Top (ET) inspection of edge trimmed via wafer. E30 proven to detect critical defects in subcontracted edge trim process. Scallop marks (chips) detected in the trim line Bottom wafer (handle wafer) has grind tracks from saw (top wafer) 13

14 Application software for edge trim monitoring adapted from EBR metrology Edge Top Camera Stitch and compress the Edge Top images into a single composite image open space wafer Acquire individual brightfield Edge Top images around full circumference Find the EBR lines Rudolph s existing EBR metrology software for the edge can be adapted to monitor edge trim process. 14

15 TSV METROLOGY DEVELOPMENT PARALLEL EXPERIMENTS AT RUDOLPH S DEVELOPMENT FACILITIES

16 Optical inspection Defects of Interest Cover Glass Bottom Defect Cover Glass Top Defect Cover Glass Cover Glass Thickness Silicon Via Depth Silicon Thickness Via Bottom Defect Via Wall Defect Via Bottom Diameter Via Top Diameter 16

17 Via Wall and Bottom Defect Inspection Defect Images 10X Via Bottom 17

18 Via Top and Bottom Diameter Measurement Results Via Too Small and Via Too Large Vias reported as Too Small due to defects in the vias Vias reported as Too Large are actually larger than the limits 18

19 NEAR-INFRARED (NIR) INSPECTION EXPERIMENTS* ON RUDOLPH AXI PLATFORM *NOTE: EXPERIMENTS ONLY, NO COMMERCIAL PLANS AT THIS TIME. Experiments conducted in conjunction with SEMATECH 3DIC Group

20 NIR Prototype Optics Bonded wafer pair interface Must image through top wafer, up to 775 micron thick (opaque in visible) Silicon is transparent in NIR/SWIR Prototype NIR optics were installed on SEMATECH AXi 935 system NIR SWIR

21 Configurations Design of Experiments 1. Nominal: Existing CMOS camera / strobe lamp A. Current camera B. Available, current design, high-intensity xenon-tungsten stroboscopic illumination. Broadband light: 400nm 1300nm+ 2. Existing CMOS camera / halogen source A. Current camera (same as 1, A.) B. Constant-on illumination source: requires start/stop vs. continuous motion inspection. Throughput hit. 3. IR camera / halogen A. NIR-specific camera (InGaAs, InSb or similar IR FPA). High cost. B. (Same as 2, B.) 4. IR camera / strobe lamp A. (same as 3, A.) B. This would have the advantage of strobe-based, continuous motion inspection. 21

22 Slide courtesy of SEMATECH This is what we might expect to see in NIR with a misalignment. 22

23 #1: CMOS Camera / Xe Strobe Light Source Advantages 1. Current camera & available stroboscopic light source. Could be used for high-speed inspection. 2. Hardware costs are lower. Disadvantages 1. Dark image / low photon quantity. 2. Extra image processing used to boost signal has a possible throughput impact & technical challenges. 5X Raw image through 775um Si 23

24 #2: CMOS Camera / Halogen (DC) Light Source Advantages 1. Current camera. 2. Hardware costs are still lower than IR camera. 3. Image processing may not be required. Disadvantages 1. Start/stop inspection only, because light source is constant on. 2. Some integration costs to develop & qualify new light source. 5X Raw image through 775um Si 24

25 #3: IR Camera / Halogen Source Advantages 1. Best quantity of light. 2. Good overall image quality. 3. Image processing may not be required. Disadvantages 1. Pixel scale is 3.6x CMOS camera. 20X on CMOS = 1.8um on IR camera) 2. High cost camera. 3. Some integration costs to develop & qualify new light source. 20X Raw image through 775um Si 25

26 #4: IR Camera / 4400 strobe Not able to acquire images in this configuration because of camera timing configuration. Needs further development before experiments can be performed. Theoretical Advantages 1. Good quantity of light middle ground. 2. Retain high-speed, stroboscopic & continuous motion capabilities. 3. Image processing may not be required. Theoretical Disadvantages 1. Pixel scale is 3.6x CMOS camera. 20X on CMOS = 1.8um on IR camera) 2. High cost camera. 26

27 Results Wafer bonding defects of interest (DOI) shown should be captured by standard inspection algorithm. What the camera sees processed image 27

28 Conclusions & Future Work on NIR This kind of metrology is currently being done by destructive cross-section SEMs, or by manual IR microscope review. Would it be interesting to have in-line and production worthy automated metrology capability to measure for overlay alignment and process-specific adder defects so that improvements can be driven into the bonding and related processes, and potential yield killers caught earlier in this very deep TSV manufacturing process? What is the required Cost-of-Ownership for this tool? 28

29 Summary 1. The AXi 935 All-Surface Inspection platform has demonstrated capability for bonded wafer pair metrology, including bonded, thinned, and edge trimmed wafers 2. The Rudolph AXi E30/B30 All-Surface Inspection System has proven to be a useful tool for supporting 3D interconnect and TSV research. 3. Rudolph gained important insights into 3DIC/TSV manufacturing market needs and benefited from the unique environment & working relationship with SEMATECH during the conduct of these experiments. 29

30 Acknowledgements SEMATECH 3D Team Tawfeeq Alzaben Sitaram Arkalgud Raymond Caramto Jose Colon John Hudnall Gary Knodler Jerry Mase Steve Olson Andrew C. Rudack Pratibha Singh Larry Smith Susan Smith Travis Smith Chris Taylor Weng-Hong Teh Bryan Thomas Jamal Qureshi 30

31 Rudolph s Total Solution for 3DIC/TSV Manufacturing Process Via Etch or Drill Via Filling/ RDL Plating Post Back grind unsupported thin wafer Micro bump/ Pillar bump Back side UBM/ RDL Plating Post bond (W2W or D2W) Post bond Inspection / Metrology Specific criteria Via depth, Via CD, sidewall defect TSV post height, RDL plating thickness, RDL CD Bump height and co planarity, size, location, missing, RDL CD RDL CD, plating defect, backside surface defect Alignment, voids Alignment, bond quality Solution NSX 320 With laser sensor (>20u) High res 3D (<20u) WS 3880 NSX 320 With ultra thin wafer handler WS 3880 NSX320 With backside inspection option NSX 320 With Near IR camera TBD E30/B30 Edge and backside defects 31

32 Thank You! Rudolph Technologies Confidential 32 32