3D SoC and Heterogeneous Integrations

Transcription

1 3D SoC and Heterogeneous Integrations

2 Content Introduction ST positioning Why 3D-Integration? CMOS Imager Sensor: the TSV success story! 3D SOC technology & applications Via Middle FE integrations Back-side processing Examples and prototyping with F2F and F2B technologies 3D Heterogeneous Integrations Heterogeneous integration strategy trends New driving applications Summary 2

3 Lessons from consumer/wireless industries... Heart Touching drives Service Service drives products Products=Systems to develop Source: GSA,

4 Why move to 3D Integration? Form factor & Cost Performances Flexibility Opportunity to form new devices

5 5 3D integration: «Horizontal» approach? or «Vertical» approach? Interposer (Module Approach) 3D (Multidies Stacking) + Harvester + Battery +. Source: J. Lau, ITRI, 2011 Source: P. Magarshack, STMicroelectronics, 2011

6 TSV Wafer Level a 2.5D success story Module size Evolution: from 2002 to 2011 TSV technology TSV Permanent Glass Handler Pixel Array CMOS: 70µm Glue TSV features Via last diameter: 70µ thickness: 70µ TSV for CMOS Imager Sensor Technology transferred from Leti Form Factor as main driver Die surface gain: 33% Die thickness gain: 50% Mass production in 12 fab 6

7 ST - 3D Integration Activities

8 3D SoC Prototyping Digital on Analog partitionning Dig/Analog partitioning 65nm node Face to Face flow Bottom die Top die 3D key process Face to Face Cu pillar bonding Bottom die Analog Top die Digital TSV in bottom die: 65nm node, Via 10µ/80µ thick Bottom die: Back-side process, temp. bond/debond Die stacking + packaging: die to die Full functionality demonstrated on first assembly lots

9 9 FE Via middle Portable TSV integration Standard front end + middle end process Via patterning Via isolation & metallisation CMP BEOL process Completed Front side TSV process TSV features via middle diameter: 10 6µ thickness: 80 50µ In 65nm FE 28nm and beyong Cu pillar process RDL + passivation Back-side isolation Grinding & TSV recess Carrier bonding

10 TSV Middle / BEOL construction analysis - Thermo mechanical behavior? - Reliability challenges - Impact on CMOS performances 10

11 11 300mm Back-Side process steps Cu RDL Ti barrier Compatible with Face to Face or Face to Back integrations Oxide Si Cu TSV Si carrier Cu pillar or Cu post Temporary bonding Coarse grinding Selective Cu nail recess Oxide deposition CMP RDL + Passivation Cu post

12 Technology driver: Wide I/O stacking on CMOS Wide IO memory SDRAM prototyping activity Is stacked on top of C65 or 28 SoC backside (F2B) Is connected through Cu-Pillars and TSV-Middle 10 to 6 µ Interface 4 x 128 bits = 512 MHz Bandpass > 10 GBy/sec to support HD Video Memory face SoC back Wide IO DRAM: face down Package molding Package Substrate SoC: face down SoC signal, SDRAM test, and supply IOs Metal stack Central array of µbumps ~1100 TSVs Peripheral µbumps test M1 VDDQ supply µ-buffer supply IO signal supply Central matrix SDRAM supply IO Metal stack SoC signal, DRAM test, and supply IOs Package Balls 12

13 Heterogeneous integration strategy trends Source: D. Lamouche, STMicroelectronics, 2011 R&D investment product inventions

14 New driving applications Image Sensors Performances (autofocus, sensitivity, stabilization, ) Human/Machine interface by touch screens interfaces. (Haptic) Accelerometers & gyroscope for gaming (ST-Agrate) Health care sensors 14

15 Summary STMicroelectronics R&D committed for 3D Integration platform developments. Memory on Logic (Wide I/O) is our Technology Driver, using 65nm FE, extendible to 28nm. 3D-SOC driven by cost & performances Via Middle for Memory on Logic: F2B process integration ready Via Middle for Digital/Analog partitionning: F2F process integration ready 3D Heterogeneous driven by new functionalities Development for image sensors, human/machine interface, sensors 15

16 Aknowledgements Special thanks to: N.Hotellier 1, A. Farcy 1, L.L. Chapelon 1, G.Druais 1, Y.Dodo 1, S.Cheramy 2, J.P. Colonna 2, N.Sillon 2, Y. Guillou 3, J.Pruvost 4, E.Saugier 4, P. Ancey 1, C. Aumont 1, P. Coudrain 1 1 STMicroelectronics, 850 rue Jean Monnet, Crolles, France 2 CEA LETI - MINATEC, 17 rue des Martyrs, Grenoble cedex 09, France 3 ST-Ericsson, 12 rue J.Horowitz, Grenoble, France 4 ST-Microelectronics, 12 rue J.Horowitz, Grenoble cedex, France 16