Graduate Institute of Electronics Engineering, NTU MIPS CPU Lab 3 memory,register file & control unit

Transcription

1 MIPS CPU Lab 3 memory,register file & control unit TA: 王奕權 2004/5/7 ACCESS IC LAB

2 A simplified processor

3 Memory 64 words length of each word:16 bit

4 Memory:write WriteEnable =1 DataIn can be written into the memory synchronously with clk(posedge) The written location is specified by input address DataOut could be arbitrary number during write operation

5 Memory:read WriteEnable =0 The memory behaves as a combinational logic block. read the data in the memory asynchronously The location to be read is specified by input address.

6 Memory:I/O pin

7 synchronous memory Modify the above memory to make the read operation synchronously with clk synchronous memory for both read and write operation Also, compare the simulation waveforms of (1) and (2).

8 Register file length of each word : 16 bit 32 registers in the register file. one 16 bit input bus: busw. Two 16 bit output buses: busa and busb.

9 Register file:write WriteEnable =1 The data on busw will be written into a register synchronously with clk(posedge). RW selects the register(one of 32 registers) to be written. BusA and busb could be arbitrary number during write operation.

10 Register file:read WriteEnable =0 The register file behaves as a combinational logic block. read the data in the register file asynchronously RA selects one of 32 registers. The content of that register will be output on busa. At the same time, RB selects one of 32 registers. The content of that register will be output on busb.

11 Register file:i/o pin

12 synchronous register file Modify the above register file to make the read operation synchronously with clk as you have done in problem 1. Also, compare the simulation waveforms of (1) and (2).

13 Single cycle architecture

14 Multi-cycle architecture

15 Control unit single-cycle:the control unit can be realized with combinational logic. multi-cycle: need a state machine to be our control unit. write a FSM control unit based on the text: Computer Organization & design, The hardware/software interface, Chapter 5.

16 Multi-cycle architecture control unit

17 State transition diagram

18 Notes(1/2) 5 different operations in the diagram: LW, SW, R-type, BEQ, J(jump). You can choose the binary numbers to represent the 5 opcodes by yourself. use parameter in Verilog to change binary numbers to LW, SW, Rtype, BEQ, J in your verilog code.

19 Notes(2/2) Follow the above graph to use binary number(0000~1001) to represent 10 states. use parameter to avoid using a binary number to represent a state in your verilog code. write verilog code for the control unit and do simulations on each path on the state transition diagram (all 5 operations).

20 State abbreviation table

21 I/O pin

22 Submission list(due on 5/21) Hardcopy submission only: print out and submit to TA before deadline Two memory modules (read synchronous/asynchronous) verilog code and simulation waveforms to verify the two modules. Comment on differences of the two waveforms. Two register file modules (read synchronous/asynchronous) verilog code and simulation waveforms to verify the two modules. Comment on differences of the 2 waveforms. Control unit verilog code and simulation waveforms.

23 Reference Computer Organization & design, the hardware/software interface,chapter 5 course slides of prof. 郭斯彥