Engineer To Engineer Note

Transcription

1 Engineer To Engineer Note EE-164 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs Contributed by Benno Kussttscher April 15, 2003 Introduction EPROM or Flsh devices re often used to boot ADSP-2191/95/96 DSPs, but fter booting, the EPROM/Flsh is not used nymore. The gol of this document is to demonstrte tht EPROM/Flsh is of use t run-time s well. It my store coefficient tbles, overlys nd, lst but not lest, the DSP my execute instructions directly from it. If you tke dvntge of the boot device this wy, you my reduce the SRAM requirements of your ppliction. Perhps you cn choose derivtive with less on-chip memory, perhps you cn sve n dditionl externl SRAM device. This document discusses vrious scenrios of dvnced Boot EPROM usge. Besides ADSP specific spects it will explin how VisulDSP++ TM helps you to mnge such pplictions. EPROM Booting Tools Chin Detils of stndrd EPROM booting re discussed in ppliction note EE-131 [1]. Just to complete the picture, this first section provides brief overview bout the relted tool chin. 1 Some fetures discussed require ltest ptches instlled. Downlod from: ftp://ftp.nlog.com/pub/tools/ If you build VisulDSP++ project during the development cycle the linker will output soclled Executble File (.dxe) tht meets the ELF / DWARF-2 stndrd. This file is pssed to the debugging tools nd contins ppliction dt s well s debugging informtion. The DSP itself cnnot ccess such Executble File (.dxe). It simply expects properly formtted dt in the EPROM/Flsh. Before you cn progrm the EPROM/Flsh physiclly you need to convert the Executble File (.dxe) into ny formt known by the EPROM progrmming tool. A common file formt for such purposes is the Enhnced Intel Hex File formt. Therefore, VisulDSP++ provides nother utility tht post processes the Executble File (.dxe). It genertes the boot strem nd emits it to so-clled Loder File (.ldr) tht meets these Intel Hex conventions. This post-processor is clled Loder Utility (elfloder.exe). Figure 1 illustrtes how to set up the Project Options in order to mke VisulDSP++ invoke the Loder Utility. If you set the Type field in the Project Options Dilog to Loder file, VisulDSP++ invokes the Loder Utility during the project build to post-process the project s Executble File (.dxe). To burn the Loder File (.ldr) into the EPROM/Flsh device externlly you my use seprte progrmming tool. Flsh devices cn lso be progrmmed in circuit, lterntively. Use the VisulDSP++ plug-in Tools Flsh Progrmmer to downlod nd flsh the Loder File (.ldr) through the JTAG emultor (or even the USB connection if you re working with the EZ-KIT Lite ). Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 Figure 1: VisulDSP Project Options Figure 2: Lod Property Pge If the DSP detects EPROM boot configurtion mode fter reset, it strts executing the Loder Kernel. This is progrm residing t the on-chip ROM ddress 0xFF It is responsible for the boot process. Initilly, the Loder Kernel reds two control bytes from /BMS spce to determine the BMSCTL nd EMICTL register settings, such s Wit sttes, EMI Clock divider nd EMI Bus width (8 or 16 bit). Once the control registers of the Externl Memory Interfce (EMI) re set up ccordingly, the Loder Kernel prses the boot strem in the EPROM nd completes the boot process without further user intervention. When the DSP is booted, the Loder Kernel executes JUMP instruction to on-chip ddress 0x nd the user ppliction gets control over the DSP. Loder Utility nd Loder Kernel hide ll the boot strem detils from you. Appliction note EE- 131 [1] provides further explintions. Using the Lod property pge shown in Figure 2 you cn choose whether the boot device is 8-bit or 16-bit wide. Also, you hve ccess to the Wit sttes nd to the EMI Clock divider used for EPROM ccesses. According to the speed-grde of the used EPROM/Flsh device you my speed up the boot process by ltering the defult vlues. The Opmode field specifies the preferred hrdwre setting (SPI0 + SPI1 versus SPORT2) during booting only. The Strt ddress box is useful if the DSP hs to shre the boot EPROM with other processors or if multiple boot imges need to be stored in single EPROM. The settings shown in Figure 2 mke the loder utility generte Intel Hex Loder File (.ldr) for 8-bit EPROM booting. They result in the Loder Utility commnd line: elfloder -proc ADSP f HEX -b PROM -width 8 -opmode 0 -clkdivide 5 -wits 7 -o test test.dxe Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 2 of 16

3 Alterntively, one my set the Width field to 16 bit if the DSP is booted from 16-bit EPROM or to 8+8 bit if the DSP is booted from two 8-bit EPROMS in 16-bit mode. In the lst cse, the Loder Utility will output two Loder Files (.ldu,.ldl). Before burning/flshing the Loder File (.ldr) you my evlute it in softwre. The VisulDSP simultor cn red the imge file from the tools commnd menu Settings Simultor Boot EPROM.Rx. The simultor interprets the Loder File (.ldr) in the sme wy s the Loder Kernel does. Once file is loded, the simultor boots the memory content every time reset is issued until the menu setting Settings Simultor Boot No Booting is checked gin. ADSP-219x Memory Booting is nothing else thn initilizing RAM fter power-up or system reset. In most of cses only on-chip SRAM of the ADSP-219x DSPs is initilized by the boot process. ADSP-2191 ADSP-2195 ADSP k x 24 bit 16k x 24 bit 16k x 24 bit 003FFF FFF BFFF 00C000 00FFFF 16k x 24 bit 16k x 16 bit 16k x 16 bit 16k x 16 bit Figure 3: On-chip Memory Mp 8k x 16 bit Figure 3 illustrtes the physicl lyout of the onchip memory. The ADSP-2191 hs four independent memory blocks. Two re 24-bit wide nd cn store instructions, but my lso store 16-bit dt. The other two blocks cn only store 16-bit dt. In totl, 32k words of 24-bit memory nd 32k of 16-bit memory re integrted on-chip. These 64k ddress loctions build the memory pge 0. While ccessing on-chip memory, lwys set the relted pge registers DMPG0, DMPG1 nd IJPG to zero. In ddition the ADSP-219x DSPs my ccess dditionl externl SRAM through the EMI port. This prllel interfce supports both, 8-bit nd 16-bit dt width. The ADSP-219x DSPs my ddress 16M words, orgnized s 256 Memory Pges of 64k words size. Pge 0 is reserved for on-chip memory. Pge 255 holds the on-chip boot ROM. All ccesses to ny of the pges 1 to 254 initite n off-chip bus trnsfer. 24 ddress line re required to ccess the complete 16M ddress spce. To void the need of off-chip ddress decoders, ADSP-219x DSPs provide four memory strobes /MS0 to /MS3. Every strobe controls one Memory Bnk, 4M words ech. Consistently, the EMI fetures only 22 ddress lines. Every memory bnk hs its own control register MSxCTL. Access prmeters such s wit-sttes cn be controlled individully. Although the MEMPGx registers my redefine the strt pge of the individul memory bnks, this ppliction note lwys ssume the defult settings. Bnk 0 (/MS0) Bnk 1 (/MS1) Bnk 2 (/MS2) Bnk 3 (/MS3) 0x x3FFFFF 0x x7FFFFF 0x xBFFFFF 0xC xEFFFFF Note tht the ddress rnge of Bnk 0 is overlpped by the on-chip memory pge. Similrly, the boot ROM pge overlps Bnk 3. If 4MWord device is connected to /MS0, the lower 64k ddresses cnnot be ccess using this scheme. Typiclly, devices re much smller, nd ll loctions cn be reched by ddress lises. For exmple, device ddress 0x cn be ccessed through lis ddress 0x200000, if the connected device fetures less thn 22 ddress lines. Beside the /MSx strobes, the EMI fetures n dditionl Boot Memory Select (/BMS) pin. There re three bits in the E_STAT register, tht my overwrite the norml /MSx functionlity, for instruction fetch, DM bus ccess or PM ccess Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 3 of 16

4 opertions. If set, the the EMI ctivtes the /BMS strobe insted of the /MSx ones whenever the ddress rnge 0x to 0xEFFFFF is ccessed, by one of the three opertions. The Boot Kernel typiclly reds the boot strem from the so-clled Boot Memory Spce by ctivting /BMS. If it is booting off-chip SRAM, the Boot Kernel mnges the E_STAT bits properly. Finlly, the ADSP-219x DSPs feture n I/O memory spce. This one is typiclly not booted nd is not described in this document, therefore. Logicl versus Physicl Addresses There is need to distinguish between logicl nd physicl prmeters. Logicl settings describe memory from the core s perspective: logicl dt width is either 16 or 24 bit wide; logicl ddresses re the ones used by progrm coding. Physicl ddresses nd memory width my differ from the logicl prmeters, especilly when describing off-chip memories. The physicl width of on-chip memory cn be either 16 bit or 24 bit, ccording to the individul memory blocks shown in Figure bit opertions to/from 24-bit on-chip memory ccess the upper 16-bits of the ddressed memory loctions only. 24-bit writes to on-chip 16-bit memory ignore the lower 8 bits stored in the PX register. 24-bit reds from on-chip memory zero the PX register. The E_BWS bit in the EMICTL register controls, whether the interfce is 8-bit or 16-bit wide. Logicl width Physicl width Address Multiply 16 bit 8 bit 2 24 bit 8 bit 4 16 bit 16 bit 1 24 bit 16 bit 2 Tble 1: Physicl Address Multiply Fctor When physicl dt width does not mtch the logicl one, multiple physicl ddress loctions re required to built one logicl ddress loction. Consistently, physicl ddresses re multiples of logicl ddresses. The multiply fctor depends on logicl to physicl dt width reltionship (nd EMI settings) s shown in Tble 1. When multiplying logicl ddresses with the proper fctor, the resulting ddress my be of theoreticl nture. Often the result exceeds the ddress rnge supported by given memory devices. If, for exmple, 64kByte SRAM is connected to /MS0, nd the progrm performs 16-bit ccess to ddress 0x011000, the physicl ddress is not 0x It is 0x In the generl cse, the logicl to physicl ddress clcultion performs the multipliction nd msks non-existing ddress bits out, fterwrds. Whether off-chip dt ccesses re trde s 16- bit or 24-bit opertions is controlled by the E_DFS bit in the E_STAT register. At run-time this bit is usully clered. If set, it helps to lod 24-bit instructions into on-chip memory. Memory Segment Types When you re mnging EPROM boot scenrios you need to be fmilir with few bsic commnds of the Linker Description File (.ldf). While processing the Executble File (.dxe) the Loder Utility evlutes the individul memory segments. Memory segments re defined within the memory lyout of the Linker Description File (.ldf). Besides the logicl ddress rnge, every segment specifies its physicl width by the WIDTH() commnd. Externl memory segments set their physicl width ccording to EMI port settings. It is possible tht the invidul off-chip memory segments hve different width settings. Then, Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 4 of 16

5 softwre must tke cre, tht the E_BWS bit is mnged propely t run-time. Also, every memory segment hs type. The dedicted TYPE() commnd ccepts four different options: TYPE(DM RAM) TYPE(PM RAM) TYPE(DM ROM) TYPE(PM ROM) The Loder Utility ignores ll segments declred by the TYPE(ROM) option nd reds the TYPE(RAM) segments only. It genertes 16-bit boot strems for TYPE(DM RAM) segments nd 24-bit boot strems for TYPE(PM RAM) segments. Plese note tht this nming convention is of historicl nture. TYPE(PM) segments re 24-bit wide nd my contin dt nd progrm code. If segment holds 16-bit dt only, it cn be defined by the TYPE(DM) commnd, regrdless whether the contining dt is ccessed through the DM or the PM bus. MEMORY { seg_code { TYPE(PM RAM) WIDTH(24) START(0x000000) END(0x007FFF) seg_dt1 { TYPE(DM RAM) WIDTH(16) START(0x008000) END(0x00BFFF) seg_dt2 { TYPE(DM RAM) WIDTH(16) START(0x00C000) END(0x00FFFF) Listing 1: LDF Memory Lyout Exmple Listing 1 illustrtes very bsic exmple of n ADSP-2191 memory lyout ccording to Figure 3. It sets up on-chip memory for booting, becuse ll segments re of TYPE(RAM). Note tht the Linker Description File (.ldf) does not describe the boot memory itself. Use the Lod property pge in Figure 2 to define whether the DSP is booted from 8-bit or from 16-bit EPROM. Booting Off-chip SRAM So fr we discussed booting to internl memory. If you hve dditionl SRAM connected to the system bus you my wnt to initilize its content t boot-time, too. This section discusses n exmple scenrio with n 8-bit boot EPROM connected to /BMS nd n dditionl 8-bit SRAM tht is connected to the memory strobe /MS1. Although the ADSP-2191 Loder Kernel cn boot on-chip nd off-chip memory from 8-bit nd from 16-bit EPROMs, the E_BWS bit in the EMICTL register is set only once. As result, externl SRAM must use the sme bus width s the boot EPROM, if you wnt to boot it. This exmple cn still use the project options shown in Figure 1 nd Figure 2. However the Linker Description File (.ldf) needs to be enriched by externl memory segments. MEMORY { seg_code { TYPE(PM RAM) WIDTH(24) START(0x000000) END(0x007FFF) seg_dt1 { TYPE(DM RAM) WIDTH(16) START(0x008000) END(0x00BFFF) seg_dt2 { TYPE(DM RAM) WIDTH(16) START(0x00C000) END(0x00FFFF) seg_dt_ext { TYPE(DM RAM) WIDTH(8) START(0x400000) END(0x40FFFF) seg_code_ext { TYPE(PM RAM) WIDTH(8) START(0x408000) END(0x417FFF) Listing 2: LDF Memory Lyout Exmple Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 5 of 16

6 If new segments re introduced in the LDF memory mp, lso proper section ssignment is required like shown in Listing 3. PROCESSOR p0 { SECTIONS {... ext_dt_dxe { INPUT_SECTIONS( $OBJECTS(extdt) ) > seg_dt_ext ext_code_dxe { INPUT_SECTIONS( $OBJECTS(extcode) ) > seg_code_ext Listing 3: LDF Section Assignment Exmple Listing 2 introduces one 24-bit TYPE(PM RAM) segment intended to store instructions nd one 16-bit TYPE(DM RAM) segment for dt. Both re bootble. The WIDTH(8) commnds in Listing 2 define the physicl width to 8 bit s required. A little understnding of EMI ddress trnsltion is required to determine strt nd end ddress of the externl memory segments. Provided tht the E_DFS bit in the E_STAT register is clered, the EMI uses the following pcking schemes: if core or DMA engine ccess 16-bit dt in the segment seg_dt_ext, then two 8-bit ccesses re required. Logicl ddresses re multiplied by two. However, if the core fetches 24-bit instructions from segment seg_code_ext, three 8-bit reds re required, resulting in n ddress multiply fctor of four. Since not just the pcking but lso the ddressing scheme differs, the memory mp of the off-chip 8-bit SRAM needs to be defined crefully: segment seg_dt_ext strts t logicl ddress 0x Therefore it ctivtes the memory strobe /MS1. The corresponding byte ddress would be 0x , but the ADSP-2191 DSPs feture only 22 ddress lines A0..A21. Therefore dt red from logicl ddress 0x ccesses the byte ddresses 0x nd 0x of the SRAM. Similrly, red from logicl ddress 0x40.FFFF ccesses the SRAM t ddress 0x01.FFFE nd 0x01.FFFF (0x81FFFE nd 0x81FFFF ANDed with 0x03.FFFF). It is obvious tht the code segment seg_code_ext should follow contiguously to seg_dt_ext without wsting SRAM loctions due to ddress gps. Segment seg_code_ext reserves spce for instructions nd every instruction word tkes four byte loctions. Thus, seg_code_ext should fit into SRAM ddresses 0x to 0x05.FFFF. To chieve this gol, the logicl ddress spce of the code segment spns from 0x to 0x41.7FFF. Tble 2 summrizes the ddress trnsltion of the exmple used in Listing 2. logicl ddress theoreticl 8-bit ddress seg_dt_ext (16 bit) physicl 8-bit SRAM ddress FFFF 081 FFFE 01 FFFE seg_code_ext (24 bit) FFF 105 FFFC 05 FFFC Tble 2: EPROM Boot Exmple Address Trnsltion Plese note tht the Clock divide nd Wit Sttes settings specified in the Lod property pge do not pply to SRAM ccesses. The Loder Kernel does not lter the MSxCTL registers. No-Boot Option Although rrely used, there my be good resons to refuse the booting cpbilities of the ADSP fmily. One exmple is pplictions tht use on-chip memory for dt storge only. Also, this mode helps to implement customized boot loder scenrios. Being progrmmble by the hrdwre pins (strp pins), the DSP cn bypss the Loder Kernel nd strt progrm execution t ddress 0x Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 6 of 16

7 Two different options support instruction fetching from 8-bit s well s from 16-bit memory connected to the strobe /MS0. The memory connected to /MS0 is usully n EPROM or Flsh, but it cn lso be voltile memory controlled by nother processor in the system. In order to generte proper EPROM file, the so-clled Splitter Utility needs to be invoked. This Splitter Utility is prt of the sme elfloder.exe tool like the Loder Utility mentioned bove. Also the Splitter Utility prses VisulDSP++ Executble File (.dxe), but this time it ignores ll segments declred by TYPE(RAM) nd reds TYPE(ROM) segments only. Listing 4 shows very bsic exmple of n LDF memory lyout tht meets the requirements. The segment seg_code contins ll progrmming code including the interrupt vector tble. Section ssignment instructions re not shown explicitly. MEMORY { seg_dt1 { TYPE(PM RAM) WIDTH(24) START(0x000000) END(0x007FFF) seg_dt2 { TYPE(DM RAM) WIDTH(16) START(0x008000) END(0x00FFFF) seg_code { TYPE(PM ROM) WIDTH(16) START(0x010000) END(0x01FFFF) seg_constnts { TYPE(DM ROM) WIDTH(16) START(0x040000) END(0x05FFFF) Listing 4: No-boot LDF File Exmple If the boot mode is set up ccordingly, fter reset the DSP strts progrm execution t the reset vector 0x The exmple ssumes 16-bit wide EPROM/Flsh connected to /MS0. No pcking nd no ddress multipliction is needed to ccess 16-bit words off-chip. Wheres fetching 24-bit instructions still requires two offchip reds nd ddresses re multiplied by two. The first instruction is locted t physicl EPROM ddresses 0x nd 0x The segment seg_code occupies EPROM spce up to ddress 0x03.FFFF. EPROM loction lower thn 0x cn be ccessed through lis ddresses. The exmple in Listing 4 uses the these loctions to store constnt 16-bit dt tbles mpped to the dt segment seg_constnts. Nevertheless the explined procedure cn lso be used to llocte the sme EPROM spce for second code segment. Assuming the size of the used EPROM is 256k by 16 bits, only the ddress lines A0..A17 re connected. EPROM ddresses re lised periodiclly in the DSP ddress spce. The reset vector cn be red from ddress 0x but lso from ddress 0x or 0x0A Similrly, the EPROM spce 0x to 0x01.FFFF cn be ccessed through the physicl ddress lis 0x to 0x05.FFFF. No ddress trnsltion is required for 16-bit ccesses. Thus, lso the LDF file my use the ddress rnge between 0x nd 0x05.FFFF to define segment seg_constnts. Agin, Tble 3 summrizes the ddress trnsltion. logicl ddress theoreticl 16-bit ddress seg_constnts (16 bit) physicl 16-bit EPROM ddress FFFF 05 FFFF 01 FFFF seg_code (24 bit) FFFF 03 FFFE 03 FFFE Tble 3: No-Boot Exmple Address Trnsltion If the Splitter Utility processes n Executble File (.dxe) bsed on the exmple LDF file, it would emit EPROM ddress from 0x to Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 7 of 16

8 0x05.FFFF. This is uncceptble becuse the 256k EPROM used in this exmple provides ddresses from 0x to 0x03.FFFF only. Tht is why the Splitter Utility fetures the dditionl mskddr ddressbit commnd line switch. This switch enbles the msking of the upper physicl ddress bits. If, in the exmple bove, ll physicl ddress bits greter or equl A18 re msked out, every EPROM ddress is ANDed with 0x03.FFFF before it is emitted to the Intel Hex file. All ddresses belonging to segment seg_code remin unchnged, but seg_constnts ddresses re mpped into ddress spce 0x to 0x01.FFFF s required. The complete commnd line my look s follows: elfloder -proc ADSP romsplitter -mskddr 18 -f HEX -width 16 -o test test.dxe Using the integrted environment of VisulDSP++ the sme commnd line is generted if the Lod property pge is set up s shown in Figure 4. Figure 4: No-boot Property Pge Currently, the VisulDSP++ singlestepping nd brekpoint fetures re supported for off-chip code execution debug. When the DSP detects no-boot option fter reset, the interrupt vector tble strts from off-chip ddress 0x If you wnt to mp it to onchip ddress 0x set the RMODE bit in the SYSCR register. Mke sure, tht corresponding on-chip memory loctions hve been initilized ccordingly. You my lso cler the RMODE bit gin to mp the interrupt vector tble bck to 0x Combining Boot + No-Boot Fortuntely, the Splitter functionlity discussed in the previous section is not restricted to the noboot options only. Almost ll pplictions require booting fter reset. Booting is trnsprent to the user nd once ll code nd dt resides in on-chip memory progrm execution cn perform t full speed. In tody s pplictions DSPs hve to perform severl tsks rther thn executing single reltime lgorithm repetitively. Memory requirements increse, perhps beyond the SRAM resources vilble on-chip. Adding n dditionl SRAM device could help. Although this increses systems costs, complex pplictions my or my not give you the choice here. But, you hve nother option. There is lredy dditionl memory connected to your system: the boot EPROM/Flsh device. ADSP-2191 processors hve full ccess to the boot device t run-time. Not only cn flsh be used to store dt nd boot code, it cn lso be used to store progrm instructions. These instructions cn be directly executed by the DSP without moving them into internl memory first. VisulDSP++ provides you ll the support you need. Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 8 of 16

9 The sme elfloder.exe tool covers both Loder nd Splitter functionlity. It cn combine both techniques esily nd emits Loder nd Splitter dt to the sme Intel Hex EPROM imge file. With the redll commnd line switch or the Lod property pge settings shown in Figure 5, you cn force the elfloder.exe tool to consume TYPE(RAM) s well s TYPE(ROM) segments. Figure 5: Boot+No-boot Property Pge The commnd line could look like this: elfloder -proc ADSP b PROM -redll -width 8 -mskddr 19 -f HEX opmode 0 clkdivide 0 wits 5 -o test test.dxe As n exmple you my blnce system costs by utilizing the on-chip memories for DSP lgorithms nd dt storge only nd executing slower progrm prts directly from the EPROM. Evlute your ppliction nd distinguish between rel-time code nd less speed-criticl prts of progrm such s initiliztion nd control code. Typiclly, DSP lgorithms re speed-sensitive nd execute in highly optimized progrm loops. It is the setup nd control code tht - due to its liner nture - consumes mny memory loctions for progrm storge. Assign different section nmes to the individul code frgments in order you cn mnge them in the LDF file properly. The following exmple executes the initiliztion code directly from EPROM nd continues with on-chip progrm execution fterwrd. Also it ccesses some EPROM constnts..section / dt constnts;.vr myconst[2] = 0xded, 0xbef;.section / code IVreset; _reset: iopg = Externl_Memory_Interfce_Pge; r = 0x086D; io(bmsctl) = r; io(ms0ctl) = r; r = 0x0070; io(emictl) = r; iopg = Externl_Access_Bridge_Pge; r = 0x0007; io(e_stat) = r; lcll _initsystem; jump _lgorithm;.section / code setup_code; _initsystem: dmpg1 = 0; dmpg2 = 0; l0 = 0; l1 = 0; l2 = 0; l3 = 0; l4 = 0; l5 = 0; l6 = 0; l7 = 0;... rts;.section / code dsp_code; _lgorithm: dmpg1 = PAGE(myconst); x0 = dm(myconst); x1 = dm(myconst+1); do lgo until forever; cll _librry;... lgo:....section / code lib_code; _librry:... rts; Listing 5: Code exmple with off-chip setup routine The sections Ivreset, lib_code nd dsp_code re booted in the norml wy, but section setup_code will execute from EPROM. Within the reset vector routine the EMI port is configured ccordingly before the off-chip function _initsystem is invoked by long cll instruction. Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 9 of 16

10 Mke sure tht you re using long brnch instructions when jumping from on-chip memory to externl instructions or vice vers. Alterntively you cn use indirect brnches by tking dvntge of the IJPG register. RTS nd RTI instructions restore the pge by themselves. We need to describe the memory lyout within the LDF file, but first let us discuss how to mnge the EPROM ddresses. The exmple is bsed on the ADSP-2196 rchitecture, with 8k of 24-bit memory nd 8k of 16-bit memory vilble on-chip s shown in Figure 3. This exmple ssumes tht 32k of EPROM bytes re sufficient to store the complete boot strem. Note tht this ssumption does not cover the worst cse (48k + some extr boot control words)! Assuming 4MBit EPROM (512k x 8 bit) the byte ddresses 0x to 0x07.FFFF re vilble for further usge. Just s n exmple let us reserve ddresses 0x to 0x01.FFFF for constnt dt storge nd 0x to 0x07.FFFF for code execution. Due to the size of the EPROM the elfloder tool will be invoked with the mskddr 19 commnd. One possible result of the required ddress clcultion is shown in Tble 4: logicl ddress theoreticl 8-bit ddress seg_ext_constnts (16 bit) physicl 8-bit EPROM ddress FFFF 09 FFFE 01 FFFE seg_ext_code (24 bit) A FFFF 0F FFFC 07 FFFC Tble 4: Boot+No-boot Exmple Address Trnsltion Accordingly, the memory lyout in the LDF files is specified s follows: MEMORY { seg_ivt { TYPE(PM RAM) WIDTH(24) START(0x000000) END(0x000241) seg_int_code { TYPE(PM RAM) WIDTH(24) START(0x000242) END(0x001FFF) seg_ext_code { TYPE(PM ROM) WIDTH(8) START(0x028000) END(0x03FFFF) seg_ext_constnts { TYPE(DM ROM) WIDTH(8) START(0x044000) END(0x04FFFF) Listing 6: Boot + No-boot LDF File Exmple Finlly, you cn mnge the individul sections by editing the LDF SECTIONS ssignment. Use it s cross tble. PROCESSOR p0 { SECTIONS { vectors_dxe { INPUT_SECTIONS( $OBJECTS(IVreset) ) > seg_ivt dsp_code_dxe { INPUT_SECTIONS( $OBJECTS(dsp_code) ) > seg_int_code lib_code_dxe { INPUT_SECTIONS( $OBJECTS(lib_code) ) > seg_int_code setup_code_dxe { INPUT_SECTIONS( $OBJECTS(setup_code) ) > seg_ext_code constnts_dxe { INPUT_SECTIONS( $OBJECTS(constnts) ) > seg_ext_constnts Listing 7: LDF Section Assignment Exmple Keep in mind tht the elfloder.exe tool genertes boot strem for TYPE(RAM) segments only. TYPE(ROM) segments re stored without formtting. Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 10 of 16

11 Speed Estimtion It is obvious tht code tht executes from EPROM is slower thn the one executed from on-chip memory. Without providing complete speed nlysis, this chpter will just imprt first ide of how much slower code execution from EPROM is by discussing one exmple. Assuming n ADSP-2191 device running t 160MHz (CCLK) nd 80MHZ (HCLK) nd Flsh device with red ccess time of 70ns the EMI cn be clocked with full speed (E_CDS = 000b), but requires five dditionl wit-sttes (E_RWC = 101b). Then, ny instruction fetch tkes 18 HCLK cycles if the Flsh is 16-bit wide nd 25 HCLK cycles if the Flsh is 8-bit wide. Depending on the bus width, off-chip progrm execution is 36 to 50 times slower thn on-chip execution if stndrd 70ns Flsh device is used. EPROM Overlys We lerned tht code execution from off-chip EPROM is very esy to hndle, but the execution speed is not tht efficient. One my use n overly pproch, by loding speed-sensible lgorithms from EPROM into internl memory on demnd during run-time. ADSP-219x overlys re discussed in ppliction notes EE-152 [2] nd AN-572 [3]. This document ssumes the bsic VisulDSP++ overly principle is lredy known. Usully, overly live in off-chip SRAM. With the restriction tht overly dt is red-only (code overlys, coefficient sets etc.) overlys my lso live in ny kind of ROM. If this ROM is the sme s the boot EPROM, system complexity nd costs will be reduced drsticlly, becuse no dditionl SRAM device is required. In order to implement such n EPROM overly scenrio properly, ll informtion of EE-152 [2] is still vlid, except tht overlys cnnot be written bck nd live segments re chnged from TYPE(RAM) to TYPE(ROM). Section Code Exmple on pge 12 provides complete exmple. About Memory Strobes The question is whether ll these scenrious discussed in the previous sections cn be implemented glue-less, or whether dditionl logic is required. At run-time the E_STAT register controls whether the severl types of off-chip ccesses ctivte the /BMS or the /MSx strobes. As long s there is only the boot EPROM connected to the system, it should be connected to /BMS. After booting set the three bits, E_PI_BE, E_PD_BE nd E_DD_BE to one nd ll off-chip ccesses (except IO trnsfers) will ctivte the EPROM. These control bits belong to ll /MSx strobes. If dditionl SRAM is connected to the system things re getting tricky. Nevertheless there re three possibilities to hndle this: Combine /BMS nd /MS0 with n AND gte (logicl OR due to negtive logic) prior to connecting them to the chip enble pin of the EPROM. Connect the SRAM to /MS1, for exmple. Alter the E_STAT register nytime the progrm is ccessing the SRAM or the EPROM. Once booted, use the EPROM for dditionl code execution but not for dt storge nymore. Also use the SRAM for dt storge only. Then, you cn set E_PI_BE but keep E_PD_BE nd E_DD_BE clered. Plese note tht we recommend keeping E_PD_BE equl to E_DD_BE. In mny cses it is just question of the optimiztion level whether dt ccess uses the PM or the DM bus. Note the difference between the following two instructions: r=x0+y0, y0=dm(i4,m4); nd r=x0+y0, x0=dm(i0,m0), y0=pm(i4,m4); Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 11 of 16

12 Another issue of interest is tht boot EPROM needs to be connected to /BMS but if the ADSP detects the no-boot option it expects n EPROM connected to /MS0. If hrdwre needs to support both scenrios ANDing /BMS nd /MS0 sounds like gret ide. The ADSP-2191 EZ- KIT Lite fetures such gte. At the other hnd, if the AND gte is missing nd the EPROM is connected to /BMS directly, it is very simple to simulte the no-boot option by booting smll progrm into on-chip memory tht just sets up the EMI port properly nd jumps to ddress 0x fterwrds. Generlly, when booting from EPROM lwys pull the ACK down by 10kΩ resistor. A floting ACK signl could prevent off-chip ccesses from being completed ccording to the wit-sttes, becuse the E_WMS field in the BMSCTL register is set to binry 11 during the boot process. Code Exmple The following code exmple is written for the ADSP-2191 EZ-KIT Lite. It ssumes n 8-bit flsh device connected to /BMS. It tkes dvntge of the boot device in two wys: the initiliztion code executes directly from flsh nd lso code overlys re loded from it. In order to concentrte on the functionlity discussed in this ppliction note, the exmple (specilly the overly mnger) is kept s simple s possible. The exmple consists of four source files min.sm ovlmn.sm overlys.h exmple.ldf The min ssembly file min.sm contins the complete ppliction code, including reset vector nd overlys. The initiliztion code is not booted. It executes from EPROM directly. Only few instructions re required to setup the EMI port ccordingly before ccessing the EPROM. Plese note tht this exmple sets the E_DFS bit in the E_STAT register. Also the overly code is not loded t boot-time, but loded on demnd t run-time. It executes from on-chip memory (run spce). #include <def2191.h> /****************************************** * Reset Vector * this piece of code is booted normlly * to on-chip ddress 0x0000.section / code IVreset; _reset: /* configure EMI * use 5 wit sttes * ignore ACK * set EMI clock equl HCLK iopg = Externl_Memory_Interfce_Pge; r = 0x086D; io(bmsctl) = r; io(ms0ctl) = r; /* set EMI width to 8-bit nd * use ctive-low strobes r = 0x0070; io(emictl) = r; /* ctive /BMS for ll off-chip ccesses * lso use 24-bit ccess scheme, becuse * the core-bsed overly mnger reds * instructions using 24-bit PM moves. iopg = Externl_Access_Bridge_Pge; r = 0x000F; io(e_stat) = r; nop; nop; nop; nop; nop; nop; nop; nop; /* long cll, note tht _sys_init * resided in off-chip memory nd the jump * crosses pge boundry lcll _sys_init; do _lgo until forever; cll _lgorithm; nop; _lgo: nop; idle; /****************************************** * Initilition Routine * this piece of code is not criticl in * terms of speed. Therefore it is not * booted. It resides in off-chip ROM. Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 12 of 16

13 .section / code romcode; _sys_init: l0 = 0; l1 = 0; l2 = 0; l3 = 0; l4 = 0; l5 = 0; l6 = 0; l7 = 0; dmpg1 = 0; iopg = 0; rts; /*************************************** * Dt Section * The exmple requires some vribles * to store results..section / dt dt1;.vr result_dd = 0;.vr result_sub = 0;.vr result_mul = 0;.vr result_div = 0; /****************************************** * Norml DSP code * this piece of code is booted normlly * fter reset.section / code progrm; _lgorithm: en mm; x0 = 10; y1 = 2; cll _func_dd; dm(result_dd) = r; cll _func_sub; dm(result_sub) = r; cll _func_mul; dm(result_mul) = r; cll _func_div; dm(result_div) = r; rts; // set brekpoint here /****************************************** * Overly code * these functions live in off-chip ROM * nd re loded on demnd into internl * memory. In this exmple every overly * consists of single function. Overly * entry functions hve to be globl..section / code code_overly1;.globl _func_dd; _func_dd: r = x0 + y1; rts;.section / code code_overly2;.globl _func_sub; _func_sub: r = x0 - y1; rts;.section / code code_overly3;.globl _func_mul; _func_mul: rts (db); mr = x0 * y1 (ss); r = mr0;.section / code code_overly4;.globl _func_div; _func_div: // divide x0 by y1 // integer division requires left shift sr = lshift x0 by 1 (lo); // unsigned division core // y0 = f:y0 / y1 f = pss 0, y0 = sr0; stt = 0; r = y1; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; divq r; rts (db); divq r; r = y0; Listing 8: min.sm The Linker Description File plys n importnt role. Note tht PLIT code, overly mnger nd overly run spce re ll mpped into the generl on-chip code segment. Similr overly live spce shres its segment with off-chip ROM code. #include "overlys.h" ARCHITECTURE(ADSP-2191) $OBJECTS MEMORY { = $COMMAND_LINE_OBJECTS; mem_int_rsti { TYPE(PM RAM) WIDTH(24) START(0x000000) END(0x00001f) mem_code { TYPE(PM RAM) WIDTH(24) START(0x000242) END(0x007fff) mem_dt2 { TYPE(DM RAM) WIDTH(16) START(0x008000) END(0x00bfff) Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 13 of 16

14 mem_dt1 { TYPE(DM RAM) WIDTH(16) START(0x00c000) END(0x00ffff) mem_romcode { TYPE(PM ROM) WIDTH(8) START(0x028000) END(0x03ffff) // end of memory mp PROCESSOR p0 { LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST ) OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) PLIT { // ssuming r nd y0 re scrtch // registers r = PLIT_SYMBOL_OVERLAYID; y0 = PLIT_SYMBOL_ADDRESS; // ssuming plit nd run ddress re // both locted in internl memory no // ljump intruction is required nd // simple jump is sufficient jump _ovl_mn; // plit SECTIONS { IVreset_dxe { INPUT_SECTIONS( $OBJECTS(IVreset) ) > mem_int_rsti progrm_dxe { INPUT_SECTIONS( $OBJECTS(progrm) ) > mem_code.plit { > mem_code // OVL_SECTION() is PP mcro run_dxe { OVL_SECTION(1) > mem_romcode OVL_SECTION(2) > mem_romcode OVL_SECTION(3) > mem_romcode OVERLAY_SECTION(4) > mem_romcode > mem_code setup_dxe { INPUT_SECTIONS( $OBJECTS(romcode) ) > mem_romcode dt1_dxe { INPUT_SECTIONS( $OBJECTS(dt1) ) > mem_dt1 dt2_dxe { INPUT_SECTIONS( $OBJECTS(dt2) ) > mem_dt2 // SECTIONS // PROCESSOR p0 Listing 9: exmple.ldf This LDF file uses the preprocessor mcro OVL_SECTION() tht hs been defined in the file overlys.h shown in Listing 11. The PLIT code clls the overly mnger shown in Listing 10. This is very bsic overly mnger for demonstrtion purposes. It uses core instructions to lod overlys into on-chip memory rther thn DMA. Plese refer to EE-152 [2] for rel-world overly mngers. // import C-style structure.import "overlys.h"; // include preprocessor mcros #include "overlys.h";.section / dt dt1;.extern OVL_EXTERNALS(1);.extern OVL_EXTERNALS(2);.extern OVL_EXTERNALS(3);.extern OVL_EXTERNALS(4);.struct ovl_struct _ovl_tb[] = { OVL_STRUCT_INIT(1), OVL_STRUCT_INIT(2), OVL_STRUCT_INIT(3), OVL_STRUCT_INIT(4) ;.globl _ovl_id;.vr _ovl_id;.globl _ovl_ddr;.vr _ovl_ddr;.vr _ovl_loded = -1;.vr _sve_dmpg2;.vr _run_ddr; /****************************************** /* this simple exmple ssumes * dmpg1 = 0, iopg = 0 * l4 = 0, l2 = 0; * run spce is in pge 0 * _ovl_tb in pge 0 * input prmeters * r = overly_id * y0 = run ddress * lso it lters severl registers.section / code progrm;.globl _ovl_mn; _ovl_mn: // sve run ddress dm(_run_ddr) = y0; // is ovl lredy loded? y0 = dm(_ovl_loded); r - y0; if eq rts; dm(_ovl_loded) = r; // red overly structure i4 = _ovl_tb - sizeof(ovl_struct); y0 = dmpg2; dm(_sve_dmpg2) = y0; dmpg2 = 0; m4 = sizeof(ovl_struct); Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 14 of 16

15 cntr = r; do getstructddr until ce; getstructddr: modify(i4+=m4); r = dm(i4+offsetof(ovl_struct,run_size)); cntr = r; y0 = dm(i4+offsetof(ovl_struct,run_ddr)); i2 = y0; r = dm(i4+offsetof(ovl_struct,live_ddr)); y0 = dm(i4+offsetof(ovl_struct,live_pge)); dmpg2 = y0; i4 = r; m4 = 1; m2 = 1; // lod overly do lodovl until ce; r = pm(i4+=m4); lodovl: pm(i2+=m2)=r; // jump to run ddress i4 = dm(_run_ddr); flush cche; jump (i4) (db); y0 = dm(_sve_dmpg2); dmpg2 = y0; Listing 10: ovlmn.sm The overly mnger tkes dvntge of C-style structures, first time supported by the VisulDSP ssembler. The specil overly structure ovl_struct is defined in Listing 11. The overly mnger uses the.import ssembly directive to get ccess to this structure. Furthermore overlys.h defines preprocessor mcros tht help you to define nd initilize the ovl_struct structure. In order to group structure definition nd mcros in one file, the structure definition needs to be encpsulted by the #ifdef _LANGUAGE_C sttement. #ifndef overly_heder #define overly_heder /*** ASM mcros ************************ #define OVL_EXTERNALS(N) \ _ov_word_size_live_##n,\ _ov_word_size_run_##n,\ _ov_strtddress_##n, \ _ov_runtimestrtddress_##n #define OVL_STRUCT_INIT(N) \ { \ PAGE(_ov_strtddress_##N), \ _ov_strtddress_##n, \ _ov_word_size_live_##n, \ PAGE(_ov_runtimestrtddress_##N), \ _ov_runtimestrtddress_##n, \ _ov_word_size_run_##n \ /*** LDF mcros *********************** #define OVL_SECTION(N) \ OVERLAY_INPUT { \ ALGORITHM (ALL_FIT) \ OVERLAY_OUTPUT ( \ $COMMAND_LINE_OUTPUT_DIRECTORY\ovl \ ##N##.ovl ) \ INPUT_SECTIONS ( \ $OBJECTS(code_overly##N)) \ /*** C-style structures ************** #ifdef _LANGUAGE_C typedef struct { int live_pge; int live_ddr; int live_size; int run_pge; int run_ddr; int run_size; ovl_struct; #endif #endif Listing 11: overlys.h Finlly mke sure tht the project is built using the settings shown in Figure 1 nd Figure 2. If you re working with VisulDSP you my need some ptches to get this exmple to work. Plese downlod the ltest ssembler / linker / loder ptches from ftp://ftp.nlog.com/pub/tools/ptches. To evlute this exmple you my use n ADSP EZ-KIT Lite. Downlod the Loder File (.ldr) using the VisulDSP++ Flsh Progrmming plug-in. Afterwrd dectivte the VisulDSP++ debugging session. Mke sure the boot mode is set to EPROM boot, nd press the Reset push button. Then, invoke the debugging session gin nd use the File Lod Symbols commnd to downlod the debugging informtion stored in the project s Executble File (.dxe). Without performing single-steps, set brekpoint t the RTS instruction of the _lgorithm subfunction. Press F5. As soon s the DSP hlts due to the brekpoint you my verify the content of the result vribles strting from ddress 0x00.C000. Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 15 of 16

16 Conclusion In the successful story of Anlog Devices DSPs, booting from prllel EPROM or Flsh devices hs lwys plyed n import role. Although the soft overly pproch of the ADSP- 218x DSPs lredy took dvntge of the boot EPROM during run-time, the ADSP-2191 DSP is the first processor from ADI tht enbles unrestricted ccess to the boot EPROM during run-time. VisulDSP tkes this rchitecture into considertion nd provides powerful scenrios to reduce system complexity nd costs. References [1] Booting the ADSP-2191/95/96 DSPs (EE-131), April 2003, Anlog Devices Inc. [2] Using Softwre Overlys with the ADSP-219x nd VisulDSP (EE-152), Februry 2002, Anlog Devices Inc. [3] Overly Linking on the ADSP-219x (AN-572), Jnury 2001, Anlog Devices Inc. Recommended Redings [4] VisulDSP Linker nd Utilities Mnul, July 2002, Anlog Devices Inc. [5] ADSP-2191 DSP Hrdwre Reference, July 2001, Anlog Devices Inc. [6] ADSP-219x DSP Instruction Set Reference, October 2000, Anlog Devices Inc. [7] ADSP-2191 DSP Dt Sheet, Rev. 0, April 2002, Anlog Devices Inc. [8] ADSP-2106x EPROM Overlys Support with VisulDSP (EE-166), June 2002, Anlog Devices Inc. [9] Using Code Overlys from ROM on the ADSP EZ-Kit Lite (EE-180), December 2002, Anlog Devices Inc. Document History Version April 15, 2003 by B.Kussttscher Description Initil Relese, focusing on ADSP-2191/95/96 DSPs Advnced EPROM Boot nd No-boot Scenrios with ADSP-219x DSPs (EE-164) Pge 16 of 16