ENE 334 Microprocessors

Transcription

1 ENE 334 Microprocessors Lecture 2: Instructions Week #02 : Dejwoot KHAWPARISUTH Adapted from Computer Organization and Design, 3 th & 4 th Edition, Patterson & Hennessy, 2005/2008, Elsevier (MK) and Lecture from Mary Jane Irwin ( ) Page 1

2 Introduction: ENE 334: Instructions Page 2 Week #02 This course is all about how computers work But what do we mean by a computer? Different types: desktop, servers, embedded devices Different uses: automobiles, graphics, finance, genomics Different manufacturers: Intel, Apple, IBM, Microsoft, Sun Different underlying technologies and different costs! Analogy: Consider a course on automotive vehicles Many similarities from vehicle to vehicle (e.g., wheels) Huge differences from vehicle to vehicle (e.g., gas vs. electric) Best way to learn: Focus on a specific instance and learn how it works While learning general principles and historical perspectives

3 Introduction: ENE 334: Instructions Page 3 Week #02 Both Hardware and Software affect performance: Algorithm determines number of source-level statements Language/Compiler/Architecture determine machine instructions (Chapter 2 and 3) Processor/Memory determine how fast instructions are executed (Chapter 5, 6, and 7)

4 ENE 334: Instructions Page 4 Week #02 What is a computer? Components: input (mouse, keyboard) output (display, printer) memory (disk drives, DRAM, SRAM, CD) network Our primary focus: the processor (datapath and control) implemented using millions of transistors Impossible to understand by looking at each transistor We need...

5 ENE 334: Instructions Page 5 Week #02 Abstraction Delving into the depths reveals more information An abstraction omits unneeded detail, helps us cope with complexity What are some of the details that appear in these familiar abstractions?

6 Abstraction Page 6

7 Abstraction Page 7

8 Abstraction Page 8

9 Abstraction Page 9

10 How do computers work? Need to understand abstractions such as: Applications software Systems software Assembly Language Machine Language Architectural Issues: i.e., Caches, Virtual Memory, Pipelining Sequential logic, finite state machines Combinational logic, arithmetic circuits Boolean logic, 1s and 0s Transistors used to build logic gates (CMOS) Semiconductors/Silicon used to build transistors Properties of atoms, electrons, and quantum dynamics So much to learn! ENE 334: Instructions Page 10 Week #02

11 ENE 334: Instructions Page 11 Week #02 Instruction Set Architecture A very important abstraction interface between hardware and low-level software standardizes instructions, machine language bit patterns, etc. advantage: different implementations of the same architecture disadvantage: sometimes prevents using new innovations True or False: Binary compatibility is extraordinarily important? Modern instruction set architectures: IA-32, PowerPC, MIPS, SPARC, ARM, and others

12 Instructions: Language of the Machine We ll be working with the MIPS instruction set architecture similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM ENE 334: Instructions Page Week #02

13 Instruction Set: Page 13

14 Instruction Set: Page 14

15 Outlines: ENE 334: Instructions Page 15 Week #02 Language of the computer MIPS Operands (Registers, Memory) Instruction Set Instruction encoding (machine language) Addressing

16 MIPS Architecture: ENE 334: Instructions Page 16 Week #02 One of the first RISC (Reduced Instruction Set Computer) MIPS Is simple, elegant Instruction Set small Fast hardware 32-bit registers A load-store architecture

17 MIPS Architecture: Page 17

18 MIPS Architecture: Page 18

19 Hardware and Software: ENE 334: Instructions Page 19 Week #02 Coordinate of many levels(layers) of abstraction

20 MIPS: Operands ENE 334: Instructions Page 20 Week #02 Why just 32 registers? - Smaller is faster

21 MIPS: Register conventions ENE 334: Instructions Page 21 Week #02 $1,$26, $27: reserved for the assembler/os

22 MIPS: Arithmetic MIPS Assembler Instructions Category Instruction Example Meaning Comments Arithmetic add add $s1,$s2,$s3 $s1 = $s2 + $s3 3 operands; exception possible subtract sub $s1,$s2,$s3 $s1 = $s2 - $s3 3 operands; exception possible All instructions have 3 operands Operand order is fixed (destination first) The natural number of operands for an operation like addition is three requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple ENE 334: Instructions Page 22 Week #02

23 MIPS: Arithmetic ENE 334: Instructions Page 23 Week #02 Example: a C program with the variables a = b + c; d = a - e; compile to MIPS assembly language add $s0,$s1,$s2 # a=b+c sub $s3,$s0,$s4 # d=a-e comment

24 MIPS: Arithmetic ENE 334: Instructions Page 24 Week #02 Example: a C program with the variables a = b+c-d+e; compile to MIPS assembly language add $t0,$s1,$s2 # temp=b+c sub $t0,$t0,$s3 # temp=temp-d add $s0,$t0,$s4 # temp=temp+e

25 Register Operands: Page 25

26 Register Operands: Page 26

27 MIPS: Arithmetic ENE 334: Instructions Page 27 Week #02 Design Principle: simplicity favors regularity. Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d Operands must be registers, only 32 registers provided Each register contains 32 bits Design Principle: smaller is faster. Why?

28 Registers vs. Memory ENE 334: Instructions Page 28 Week #02 Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables Control Input Memory Datapath Output Processor I/O

29 Memory Operands Page 29

30 Memory Organization ENE 334: Instructions Page 30 Week #02 Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory.

31 Memory Organization ENE 334: Instructions Page 31 Week #02 Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes. Registers hold 32 bits of data 2 32 bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned i.e., what are the least 2 significant bits of a word address?

32 Memory: Byte Ordering ENE 334: Instructions Page 32 Week #02 Advantages of Big Endian, Little Endian? Alignment?

33 Memory: Byte Ordering Page 33

34 Memory: Byte Ordering Page 34

35 ENE 334: Instructions Page 35 Week #02 MIPS: Data transfer MIPS Assembler Instructions Category Instruction Example Meaning Comments Arithmetic Data transfer add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 - $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $ constant; exception possible load word lw $1,100($2) $1 = Memory[$2+100] Data from memory to register store word sw $1,100($2) Memory[$2+100] = $1 Data from register to memory

36 MIPS: Data transfer ENE 334: Instructions Page 36 Week #02 Addresses CPU Data Memory sw $1,32($2) offset Addresses CPU Memory lw $1,32($2) Data Base Register

37 MIPS: Data transfer ENE 334: Instructions Page 37 Week #02 Example: a C program A[12] = b+a[8]; compile to MIPS assembly language lw $t0,32($s2) # temp=a[8] add $t0,$s1,$t0 # temp=temp+b sw $t0,48($s2) # A[12]=b+A[8] offset Base Register

38 MIPS: Data transfer ENE 334: Instructions Page 38 Week #02 Example: a C program A[12] = b+a[8]+4; compile to MIPS assembly language lw $t0,32($s2) # temp=a[8] add $t0,$s1,$t0 # temp=temp+b addi $t0,$t0,4 # temp=temp+4 sw $t0,48($s2) # A[12]=b+A[8]

39 Constants Page 39 Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; Solutions? Why not? put 'typical constants' in memory and load them. create hard-wired registers (like $zero) for constants like one. MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 Design Principle: Make the common case fast. Which format?

40 Immediate Operands Page 40

41 The Constant Zero Page 41

42 Unsigned Binary Integers Page 42

43 Unsigned Binary Representation Page 43

44 2s-Complement Signed Integers Page 44

45 2s-Complement Signed Integers Page 45

46 Signed Negation Page 46

47 Signed Negation Page 47

48 Signed Extension Page 48

49 How about larger constants? Page 49 We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction Then must get the lower order bits right, i.e., ori $t0, $t0,

50 Representing Instructions Page 50

51 MIP R-format Instructions Page 51

52 Machine Language ENE 334: Instructions Page 52 Week #02 Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 # R[rd] = R[rs] + R[rt] registers have numbers, $t0=8, $s1=17, $s2=18 Instruction Format: Can you guess what the field names stand for?

53 R-format Example Page 53

54 Hexadecimal Page 54

55 MIP I-format Instructions Page 55

56 Stored Program Computers Page 56

57 Machine Language ENE 334: Instructions Page 57 Week #02 Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw $t1, 32($s2) # R[rt] = M[R[rs]+SignExtImm] SignExtImm = {16{immediate[15]},immediate} Where's the compromise?

58 ENE 334: Instructions Page 58 Week #02 MIPS: instruction encoding MIPS machine langauge Format Comments Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits 32 bits R-format R op rs rt rd shamt funct Arithmetic instruction format I-format I op rs rt address Data transfer, branch format op: opcode rs,rt: the register source rd: the register destination shamt: shift amount (for shift instructionns) funct: Function

59 MIPS: instruction encoding Page 59

60 MIPS: instruction encoding Page 60

61 ENE 334: Instructions Page 61 Week #02 MIPS: instruction encoding MIPS machine langauge Instruction Format Example Comments add R add $s1,$s2,$s3 sub R sub $s1,$s2,$s3 addi I addi $s1,$s2,100 lw I lw $s1,100($s2) sw I sw $s1,100($s2) Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits 32 bits R-format R op rs rt rd shamt funct Arithmetic instruction format I-format I op rs rt constant or address Data transfer, branch format Note: any comment?

62 ENE 334: Instructions Page 62 Week #02 MIPS: instruction encoding Example Decimal format Binary format add $s1,$s2,$s sub $s1,$s2,$s addi $s1,$s2, lw $s1,100($s2) sw $s1,100($s2) Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits R-format op rs rt rd shamt funct op rs rt rd shamt funct I-format op rs rt constant or address op rs rt constant or address

63 Stored Program Concept ENE 334: Instructions Page 63 Week #02 Instructions are bits Programs are stored in memory to be read or written just like data Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the next instruction and continue

64 Logical Operations Page 64

65 Shift Operations Page 65

66 AND Operations Page 66

67 OR Operations Page 67

68 NOT Operations Page 68

69 MIPS Logical Operations Page 69

70 ENE 334: Instructions Page 70 Week #02 MIPS: Logical MIPS assembly language Category Instruction Example Meaning Comments and and $1,$2,$3 $1 = $2 & $3 3 register operands; Logical AND or or $1,$2,$3 $1 = $2 $3 3 register operands; Logical OR Logical and immediate and $1,$2,100 $1 = $2 & 100 Logical AND register, constant or immediate or $1,$2,100 $1 = $2 100 Logical OR register, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant Bitwise Operations

71 Control ENE 334: Instructions Page 71 Week #02 Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label:...

72 Control ENE 334: Instructions Page 72 Week #02 MIPS unconditional branch instructions: j label Example: if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5 Lab2:... Can you build a simple for loop?

73 Control Flow ENE 334: Instructions Page 73 Week #02 We have: beq, bne, what about Branch-if-less-than? New instruction: slt $t0, $s1, $s2 if $s1 < $s2 then $t0 = 1 else $t0 = 0 Can use this instruction to build "blt $s1, $s2, Label" can now build general control structures Note that the assembler needs a register to do this, there are policy of use conventions for registers

74 Conditional Operations Page 74

75 Compiling If Statement Page 75

76 ENE 334: Instructions Page 76 Week #02 MIPS: Decision MIPS assembly language Category Instruction Example Meaning Comments branch on equal beq $1,$2,100 if ($1 == $2) go to PC Equal test; PC relative branch branch on not equal bne $1,$2,100 if ($1!= $2) go to PC Not equal test; PC relative Conditional branch Unconditional jump set on less than slt $1,$2,$3 if ($2 < $3) $1 = 1; else $1 = 0 Compare less than; 2`s complement set less than immediate slti $1,$2,100 if ($2 < 100) $1 = 1; else $1 = 0 Compare < constant; 2`s complement set less than unsigned sltu $1,$2,$3 if ($2 < $3) $1 = 1; else $1 = 0 Compare less than; natural number set less than immediate unsigned sltiu $1,$2,100 if ($2 < 100) $1 = 1; else $1 = 0 Compare constant; natural number jump j goto Jump to target address jump register j $31 goto $31 For switch, procedure return jump and link jal $31 = PC + 4;go to For procedure call

77 MIPS: Decision ENE 334: Instructions Page 77 Week #02 Example: a C program if (i==j) f = g + h; else f = g - h; compile to MIPS beq $s3,$s4,add # i=j? sub $s0,$s1,$s2 # f = g - h j Exit # goto Exit Add: add $s0,$s1,$s2 # f = g + h Exit:

78 MIPS: Decision ENE 334: Instructions Page 78 Week #02 Example: a C program if (i<j) goto Less; i - $s0 j - $s1 compile to MIPS Start: slt $t0,$s0,$s1 # $t0=1 if (i<j) bne $t0,$0,less # if $t0!= 0. # go to Less.. Less:

79 MIPS: Decision ENE 334: Instructions Page 79 Week #02 Example: a C program if (i>j) goto More; i - $s0 j - $s1 compile to MIPS Start: slt $t0,$s1,$s0 # $t0=1 if (j<i) bne $t0,$0,more # if $t0!= 0. # go to More.. More:

80 MIPS: Decision ENE 334: Instructions Page 80 Week #02 Example: a C program if (i>=j) goto MoreEq; i - $s0 j - $s1 compile to MIPS Start: slt $t0,$s0,$s1 # $t0=1 if (i<j) beq $t0,$0,moreeq # if $t0 = 0. # go to MoreEq.. MoreEq:

81 MIPS: Decision ENE 334: Instructions Page 81 Week #02 Example: a C program if (i<=j) goto LessEq; i - $s0 j - $s1 compile to MIPS Start: slt $t0,$s1,$s0 # $t0=1 if (j<i) beq $t0,$0,lesseq # if $t0 = 0. # go to LessEq.. LessEq:

82 MIPS: Decision ENE 334: Instructions Page 82 Week #02 Example: Loop a C program while (save[i] == k) i += 1; compile to MIPS Loop: sll $t1,$s3,2 # $t1 = 4*i Exit: i - $s3 k - $s5 base addr.of the array save is in $s6 add $t1,$t1,$s6 # $t1 = addr lw $t0,0($t1) # $t0 = save[i] bne $t0,$s5,exit # save[i]=k? addi $s3,$s3,1 # i = i+1 j Loop # go to Loop

83 MIPS: Decision ENE 334: Instructions Page 83 Week #02 Example: Loop a C program if (i>=1) goto Loop; i - $s0 compile to MIPS Loop:... slti $t0,$s0,1 # $t0=1 if (i<1) beq $t0,0,loop # go to Loop # if (i>=1)

84 MIPS: Decision Page 84

85 MIPS: Decision Page 85

86 MIPS: Decision Page 86

87 MIPS: Decision Page 87

88 MIPS: Decision Page 88

89 MIPS: Decision Page 89

90 MIPS: Decision Page 90

91 Branch Instruction Design Page 91

92 Signed vs. Unsigned Page 92

93 Page 93 Assembly Language vs. Machine Language Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide 'pseudoinstructions' e.g., move $t0, $t1 exists only in Assembly would be implemented using add $t0,$t1,$zero When considering performance you should count real instructions

94 MIPS: Procedure Calling Page 94

95 MIPS: Procedure Calling Page 95

96 Register Usage Page 96

97 Procedure Call Instruction Page 97

98 Procedure Call Instruction Page 98

99 MIPS: Procedure ENE 334: Instructions Page 99 Week #02 Example: a C program int leaf_example (int g, int h, int i, int j) { int f; } f = (g+h) (i+j); return f; g,h,i,j - $a0-3 f - $s0

100 ENE 334: Instructions Page 100 Week #02 MIPS: Procedure compile to MIPS # save the registers used by the procedure addi $sp,$sp,-12 # adjust stack sw $t1,8($sp) # save $t1 sw $t0,4($sp) # save $t0 sw $s0,0($sp) # save $s0 High addr Memory High addr Memory High addr Memory $SP -> $SP -> Contents of $t1 Contents of $t1 Contents of $t0 Contents of $t0 $SP -> Contents of $s0 Contents of $s0 Low addr Low addr Low addr Before During After

101 ENE 334: Instructions Page 101 Week #02 MIPS: Procedure compile to MIPS (continue) # the body of the procedure # f = (g+h) (i+j); # add $t0,$a0,$a1 add $t1,$a2,$a3 sub $s0,$t0,$t1 # f=(g+h)-(i+j) # then return value of f add $v0,$s0,$zero # $v0=$s0+0

102 ENE 334: Instructions Page 102 Week #02 MIPS: Procedure compile to MIPS (continue) # then restore POP lw $s0,0($sp) # restore $s0 lw $t0,4($sp) # restore $t0 lw $t1,8($sp) # restore $t1 addi $sp,$sp,12 # adjust stack # a jump register using the return addr jr $ra # jamp back to # calling routine --> leaf procedure

103 Leaf Procedure Example Page 103

104 Leaf Procedure Example Page 104

105 Non-Leaf (Nested) Procedures Page 105

106 Non-Leaf Procedure Example Page 106

107 Non-Leaf Procedure Example Page 107

108 Non-Leaf Procedure Example Page 108

109 Non-Leaf Procedure Example Page 109

110 Local Data on the Stack Page 110

111 Non-Leaf Procedure Example Page 111

112 Character Data Page 112

113 Byte/Halfword Operations Page 113

114 String Copy Example Page 114

115 String Copy Example Page 115

116 MIPS: Addressing ENE 334: Instructions Page 116 Week #02 1. Register addressing 2. Base or displacement addressing 3. Immediate addressing 4. PC-relative addressing 5. Pseudodirect addressing

117 MIPS: Addressing Register addressing Ex: add $s1,$s2,$s3 # R[rd]=R[rs]+R[rt] Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits R-format op rs rt rd shamt funct Register Register Register ENE 334: Instructions Page 117 Week #02

118 ENE 334: Instructions Page 118 Week #02 MIPS: Addressing Base or displacement addressing Ex: lw $s1,100($s2) # R[rt]=M[R[rs]+SignExtImm] Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits I-format op rs rt Immediate the operand is at the memory location whose address is the sum of a Reg. + a constant

119 ENE 334: Instructions Page 119 Week #02 MIPS: Addressing Immediate addressing Ex: addi $s1,$s2,100 #R[rt]=R[rs]+SignExtImm Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits I-format op rs rt Immediate the operand is a constant within the instruction itself

120 ENE 334: Instructions Page 120 Week #02 MIPS: Addressing PC-relative addressing Ex: beq $s1,$s2,100 #if(r[rs]==r[rt]),pc=pc+4+branchaddr Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits I-format op rs rt immediate

121 ENE 334: Instructions Page 121 Week #02 MIPS: Addressing Pseudodirect addressing Ex: j # PC=JumpAddr Field size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits J-format op address the jump address is the 26 bits of the instruction concanated with the upper bits of the PC

122 Branch Addressing Page 122

123 Jump Addressing Page 123

124 Target Addressing Example Page 124

125 Branch Far Away Page 125

126 Translation and Startup Page 126

127 Assembler Pseudoinstructions Page 127

128 Producing an Object Module Page 128

129 Linking Object Modules Page 129

130 Loading a Program Page 130

131 Dynamic Linking Page 131

132 Lazy Linkage Page 132

133 Starting Java Applications Page 133

134 C Sort Example Page 134

135 The Procedure Swap Page 135

136 The Sort Procedure in C Page 136

137 The Procedure Body Page 137

138 The Full Procedure Page 138

139 Arrays vs. Pointers Page 139

140 Example: Clearing and Array Page 140

141 Comparison of Array vs. Ptr Page 141

142 ENE 334: Instructions Page 142 Week #02 Binary & Gray Code: Optical Shaft Angle Encoder

143 ENE 334: Instructions Page 143 Week #02 ASCII: 1/2 American Standard Code for Information Interchange

144 ENE 334: Instructions Page 144 Week #02 ASCII: 2/2 Control Characters

145 ENE 334: Instructions Page 145 Week #02 UNICODE: The First 256 codes (16 bit code)

146 Overview of MIPS ENE 334: Instructions Page 146 Week #02 simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats rely on compiler to achieve performance what are the compiler's goals? help compiler where we can

147 Addresses in Branches and Jumps ENE 334: Instructions Page 147 Week #02 Instructions: bne $t4,$t5,label Next instruction is at Label if $t4 $t5 beq $t4,$t5,label Next instruction is at Label if $t4 = $t5 j Label Next instruction is at Label Formats: Addresses are not 32 bits How do we handle this with load and store instructions?

148 Addresses in Branches ENE 334: Instructions Page 148 Week #02 Instructions: bne $t4,$t5,label beq $t4,$t5,label Formats: Next instruction is at Label if $t4 $t5 Next instruction is at Label if $t4=$t5 Could specify a register (like lw and sw) and add it to address use Instruction Address Register (PC = program counter) most branches are local (principle of locality) Jump instructions just use high order bits of PC address boundaries of 256 MB

149 To summarize: MIPS operands Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 30 memory Memory[4],..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s ] Word from memory to register store word sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s ] Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper immediate lui $s1, 100 $s1 = 100 * 2 16 Loads constant in upper 16 bits branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC branch on not equal bne $s1, $s2, 25 if ($s1!= $s2) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne set less than immediate slti $s1, $s2, 100 if ( $s2 < 100) $s1 = 1; else $s1 = 0 Compare less than constant ENE 334: Instructions jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call Page 149 Week #02

150 ENE 334: Instructions Page 150 Week #02 To summarize: 1. Immediate addressing op rs rt Immediate 2. Register addressing op rs rt rd... funct Registers Register 3. Base addressing op rs rt Address Memory Register + Byte Halfword Word 4. PC-relative addressing op rs rt Address Memory PC + Word 5. Pseudodirect addressing op Address Memory PC Word

151 ENE 334: Instructions Page 151 Week #02 Alternative Architectures Design alternative: provide more powerful operations goal is to reduce number of instructions executed danger is a slower cycle time and/or a higher CPI The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions Let s look (briefly) at IA-32

152 IA - 32 ENE 334: Instructions Page 152 Week # : The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The increases address space to 24 bits, +instructions 1985: The extends to 32 bits, new addressing modes : The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: 57 new MMX instructions are added, Pentium II 1999: The Pentium III added another 70 instructions (SSE) 2001: Another 144 instructions (SSE2) 2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64) 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions This history illustrates the impact of the golden handcuffs of compatibility adding new features as someone might add clothing to a packed bag an architecture that is difficult to explain and impossible to love

153 IA-32 Overview ENE 334: Instructions Page 153 Week #02 Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., base or scaled index with 8 or 32 bit displacement Saving grace: the most frequently used instructions are not too difficult to build compilers avoid the portions of the architecture that are slow what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective

154 IA-32 Registers and Data Addressing Registers in the 32-bit subset that originated with Name 31 0 Use EAX GPR 0 ECX GPR 1 EDX GPR 2 EBX GPR 3 ESP GPR 4 EBP GPR 5 ESI GPR 6 EDI GPR 7 CS SS DS ES FS GS Code segment pointer Stack segment pointer (top of stack) Data segment pointer 0 Data segment pointer 1 Data segment pointer 2 Data segment pointer 3 EIP Instruction pointer (PC) ENE 334: Instructions EFLAGS Page 154 Condition codes Week #02

155 IA-32 Register Restrictions ENE 334: Instructions Page 155 Week #02 Registers are not general purpose note the restrictions below

156 IA-32 Typical Instructions ENE 334: Instructions Page 156 Week #02 Four major types of integer instructions: Data movement including move, push, pop Arithmetic and logical (destination register or memory) Control flow (use of condition codes / flags ) String instructions, including string move and string compare

157 IA-32 instruction Formats ENE 334: Instructions Page 157 Week #02 Typical formats: (notice the different lengths) a. JE EIP + displacement JE Condition Displacement b. CALL 8 32 CALL Offset c. MOV EBX, [EDI + 45] MOV d w r/m Postbyte Displacement d. PUSH ESI 5 3 PUSH Reg e. ADD EAX, # ADD Reg w Immediate f. TEST EDX, # TEST w Postbyte Immediate

158 Summary ENE 334: Instructions Page 158 Week #02 Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate Design Principles: simplicity favors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a very important abstraction indeed!

159 Summary Page 159

160 ENE 334: Instructions Page 160 Week #02 Conclusions: The arithmetic instruction: assignment statement Data transfer instruction: data structure The conditional branches: if statement/loop The unconditional jumps: procedure calls, return and case/switch statements See figure 2.48 page 146

161 ENE 334: Instructions Page 161 Week #02 Questions?: Why doesn't MIPS have a subtract immediate instruction?

162 ENE 334: Instructions Page 162 Week #02