Figure 7.7. A digital system like the one in Figure 7.2.
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- Peregrine Rafe Miles
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1 Figure 7.7. A digital ytem like the oe i Figure 7.2.
2 Figure 7.8. Uig multiplexer to implemet a bu.
3 Figure 7.3. Code for the proceor (Part a).
4 Figure 7.3. Code for the proceor (Part b).
5 module proc(data, Reet, w, Clock, F, Rx, Ry, Doe, BuWire); iput [7:] Data; iput Reet, w, Clock; iput [:] F, Rx, Ry; output reg [7:] BuWire; output reg Doe; reg [7:] Sum; reg [:3] Ri, Rout; reg Exter, Ai, Gi, Gout, AddSub; wire [:] Cout, I; wire [:3] Xreg, Y; wire [7:] R, R, R2, R3, A, G; wire [:6] Fuc, FucReg, Sel; wire Clear = Reet Doe (~w & ~Cout[] & ~Cout[]); upcout couter (Clear, Clock, Cout); aig Fuc = {F, Rx, Ry}; wire FRi = w & ~Cout[] & ~Cout[]; reg fuctioreg (Fuc, FRi, Clock, FucReg); defparam fuctioreg. = 6; aig I = FucReg[:2]; dec2to4 decx (FucReg[3:4], b, Xreg); dec2to4 decy (FucReg[5:6], b, Y);! cotiued i Part b. Figure 7.4. Alterative code for the proceor. (Part a).
6 I, Xreg, Y) begi Exter = 'b; Doe = 'b; Ai = 'b; Gi = 'b; Gout = 'b; AddSub = 'b; Ri = 4'b; Rout = 4'b; cae (Cout) 2'b: ; //o igal aerted i time tep T 2'b: //defie igal i time tep T cae (I) 2'b: begi //Load Exter = 'b; Ri = Xreg; Doe = 'b; 2'b: begi //Move Rout = Y; Ri = Xreg; Doe = 'b; default: begi //Add, Sub Rout = Xreg; Ai = 'b; cae 2'b: //defie igal i time tep T2 cae (I) 2'b: begi //Add Rout = Y; Gi = 'b; 2'b: begi //Sub Rout = Y; AddSub = 'b; Gi = 'b; default: ; //Add, Sub cae 2'b: cae (I) 2'b, 2'b: begi Gout = 'b; Ri = Xreg; Doe = 'b; default: ; //Add, Sub cae cae cotiued i Part c. Figure 7.4. Alterative code for the proceor (Part b).
7 ! reg reg_ (BuWire, Ri[], Clock, R); reg reg_ (BuWire, Ri[], Clock, R); reg reg_2 (BuWire, Ri[2], Clock, R2); reg reg_3 (BuWire, Ri[3], Clock, R3); reg reg_a (BuWire, Ai, Clock, A); //alu A, BuWire) begi if (!AddSub) Sum = A + BuWire; ele Sum = A - BuWire; reg reg_g (Sum, Gi, Clock, G); aig Sel = {Rout, Gout, Exter}; R, R, R2, R3, G, Data) begi if (Sel == 6'b) BuWire = R; ele if (Sel == 6'b) BuWire = R; ele if (Sel == 6'b) BuWire = R2; ele if (Sel == 6'b) BuWire = R3; ele if (Sel == 6'b) BuWire = G; ele BuWire = Data; module Figure 7.4. Alterative code for the proceor (Part c).
8 Reet S Load A B S2 S3 Shift right A Doe B B + A =? a Figure 7.7. ASM chart for the peudo-code i Figure 7.6.
9 module bitcout (Clock, Reet, LA,, Data, B, Doe); iput Clock, Reet, LA, ; iput [7:] Data; output reg [3:] B; output reg Doe; wire [7:] A; wire z; reg [:] Y, y; reg EA, EB, LB; // cotrol circuit parameter S = 2'b, S2 = 2'b, S3 = 2'b; y, z) begi: State_table cae (y) S: if (!) Y = S; ele Y = S2; S2: if (z == ) Y = S2; ele Y = S3; S3: if () Y = S3; ele Y = S; default: Y = 2'bxx; cae Clock, egedge Reet) begi: State_flipflop if (Reet = = ) y <= S; ele y <= Y;! cotiued i Partr b. Figure 7.2. Verilog code for the bit-coutig circuit (Part a).
10 A[]) begi: FSM_output // default EA = ; LB = ; EB = ; Doe = ; cae (y) S: LB = ; S2: begi EA = ; if (A[]) EB = ; ele EB = ; S3: Doe = ; cae // datapath circuit // couter B Reet, poedge Clock) if (!Reet) B <= ; ele if (LB) B <= ; ele if (EB) B <= B + ; hiftre ShiftA (Data, LA, EA,, Clock, A); aig z = ~ A; module Figure 7.2. Verilog code for the bit-coutig circuit (Part b).
11 LA DataA LB DataB EA L E Shift-left regiter EB L E Shift-right regiter Clock A 2 B + Sum 2 2 z b Pel DataP 2 EP E Regiter 2 P Figure Datapath circuit for the multiplier.
12 Reet S Pel =, EP S2 S3 Pel =, EA, EB Doe EP z b Figure ASM chart for the multiplier cotrol circuit.
13 module multiply (Clock, Reet, LA, LB,, DataA, DataB, P, Doe); parameter = 8; iput Clock, Reet, LA, LB, ; iput [-:] DataA, DataB; output [+-:] P; output reg Doe; wire z; reg [+-:] A, DataP; wire [+-:] Sum; reg [:] y, Y; reg [-:] B; reg EA, EB, EP, Pel; iteger k; // cotrol circuit parameter S = 2'b, S2 = 2'b, S3 = 2'b; y, z) begi: State_table cae (y) S: if ( == ) Y = S; ele Y = S2; S2: if (z == ) Y = S2; ele Y = S3; S3: if ( == ) Y = S3; ele Y = S; default: Y = 2'bxx; cae Clock, egedge Reet) begi: State_flipflop if (Reet = = ) y <= S; ele y <= Y;! cotiued i Part b. Figure Verilog code for the multiplier circuit (Part a).
14 y, B[]) begi: FSM_output // default EA = ; EB = ; EP = ; Doe = ; Pel = ; cae (y) S: EP = ; S2: begi EA = ; EB = ; Pel = ; if (B[]) EP = ; ele EP = ; S3: Doe = ; cae //datapath circuit hiftre ShiftB (DataB, LB, EB,, Clock, B); defparam ShiftB. = 8; hiftle ShiftA ({{{'b}}, DataA}, LA, EA, b, Clock, A); defparam ShiftA. = 6; aig z = (B = = ); aig Sum = A + P; // defie the 2 2-to- multiplexer Sum) for (k = ; k < +; k = k+) DataP[k] = Pel? Sum[k] : b; rege RegP (DataP, Clock, Reet, EP, P); defparam RegP. = 6; module Figure Verilog code for the multiplier circuit (Part b).
15 Reet Load A Load B S R, C S2 Shift left R A S4 Doe S3 C C R B? Shift ito Q Shift ito Q R R B C =? Figure ASM chart for the divider.
16 Reet S Rel =, LR, LC S2 ER, EA S3 EQ, Rel =, EC c out S4 Doe LR z Figure 7.3. ASM chart for the divider cotrol circuit.
17 Reet S LR Rel =, LC, ER EA, ER S2 ER, ER, EA, Rel = c out S3 Doe LR EC z Figure ASM chart for the ehaced divider cotrol circuit.
18 LA DataA EB DataB Clock EA L E Left-hift regiter w E Regiter B c out + c i Rel ER LR ER L E Left-hift regiter w rr Q Q D q r 2 r R Q Figure Datapath circuit for the ehaced divider.
19 module divider (Clock, Reet,, LA, EB, DataA, DataB, R, Q, Doe); parameter = 8, log = 3; iput Clock, Reet,, LA, EB; iput [-:] DataA, DataB; output [-:] R, Q; output reg Doe; wire Cout, z; wire [-:] DataR; wire [:] Sum; reg [:] y, Y; reg [-:] A, B; reg [log-:] Cout; reg EA, Rel, LR, ER, ER, LC, EC, R; iteger k; // cotrol circuit! parameter S = 2'b, S2 = 2'b, S3 = 2'b; y, z) begi: State_table cae (y) S: if ( == ) Y = S; ele Y = S2; S2: if (z == ) Y = S2; ele Y = S3; S3: if ( == ) Y = S3; ele Y = S; default: Y = 2'bxx; cae Clock, egedge Reet) begi: State_flipflop if (Reet == ) y <= S; ele y <= Y; cotiued i Part b. Figure Verilog code for the divider circuit (Part a).
20 Cout, z) begi: FSM_output // default LR = ; ER = ; ER = ; LC = ; EC = ; EA = ; Rel = ; Doe = ; cae (y) S: begi LC = ; ER = ; if ( == ) begi LR = ; ER = ; ele begi LR = ; EA = ; ER = ; S2: begi Rel = ; ER = ; ER = ; EA = ; if (Cout) LR = ; ele LR = ; if (z == ) EC = ; ele EC = ; S3: Doe = ; cae Figure Verilog code for the divider circuit (Part b).
21 //datapath circuit rege RegB (DataB, Clock, Reet, EB, B); defparam RegB. = ; hiftle ShiftR (DataR, LR, ER, R, Clock, R); defparam ShiftR. = ; muxdff FF_R ( b, A[-], ER, Clock, R); hiftle ShiftA (DataA, LA, EA, Cout, Clock, A); defparam ShiftA. = ; aig Q = A; dowcout Couter (Clock, EC, LC, Cout); defparam Couter. = log; aig z = (Cout = = ); aig Sum = { b, R[-2:], R} + { b, ~B} + ; aig Cout = Sum[]; // defie the 2-to- multiplexer aig DataR = Rel? Sum : ; module Figure Verilog code for the divider circuit (Part c).
22 Sum = ; for i = k dow to do Sum = Sum +R i ; for; M = Sum k ; (a) Peudo-code Reet S Load regiter Sum, C k S2 Sum Sum + R i C C C =? S3 S4 M Sum k Doe (b) ASM chart Figure A algorithm for fidig the mea of k umber.
23 RAdd ER w y w 2-to-4 y y 2 y 3 E Data E Regiter E Regiter E Regiter E Regiter Clock Sel ES E Regiter EC LC E L Dow-couter z + k EB Sum LA k B EB A LA Div Divider R Q Doe M zz Figure Datapath circuit for the mea operatio.
24 Reet S LC, Sel =, ES S2 EC Sel =, ES z S3 LA, EB S4 Div S5 Div, Doe zz Figure ASM chart for the mea operatio cotrol circuit.
25 Reet Load regiter S C i S2 A R, i C j C i C i C i + S3 C j C j + S4 B R j S5 C j C j + B < A? S6 R j A S8 A R i S7 R i B C j = K? S9 Doe C i = k 2? Figure 7.4. ASM chart for the ort operatio.
26 Reet S LI, It = S2 It =, Cel =, Ai, LJ EI S3 EJ S4 Bi, Cel =, It = S5 EJ BltA S6 Cel =, It =, Wr, Aout S8 Cel =, It =, Ai S7 Cel =, It =, Wr, Bout z j S9 Doe z i Figure ASM chart for the cotrol circuit.
27 module ort (Clock, Reet,, WrIit, Rd, DataI, RAdd, DataOut, Doe); parameter = 4; iput Clock, Reet,, WrIit, Rd; iput [-:] DataI; iput [:] RAdd; output [-:] DataOut; output reg Doe; wire [:] Ci, Cj, CMux, IMux; wire [-:] R, R, R2, R3, A, B, RData, ABMux; wire BltA, zi, zj; reg It, Cel, Wr, Ai, Bi, Aout, Bout; reg LI, LJ, EI, EJ, Ri, Ri, Ri2, Ri3; reg [3:] y, Y; reg [-:] ABData; // cotrol circuit parameter S = 4'b, S2 = 4'b, S3 = 4'b, S4 = 4'b; parameter S5 = 4'b, S6 = 4'b, S7 = 4'b, S8 = 4'b, S9 = 4'b;! BltA, zj, zi) begi: State_table cae (y) S: if ( == ) Y = S; ele Y = S2; S2: Y = S3; S3: Y = S4; S4: Y = S5; S5: if (BltA) Y = S6; ele Y = S8; S6: Y = S7; S7: Y = S8; S8: if (!zj) Y = S4; ele if (!zi) Y = S2; ele Y = S9; S9: if () Y = S9; ele Y = S; default: Y = 4'bx; cae cotiued i Part b. Figure Verilog code for the ortig circuit (Part a).
28 Clock, egedge Reet) begi: State_flipflop if (Reet = = ) y <= S; ele y <= Y; zj, zi) begi: FSM_output // default It = ; Doe = ; LI = ; LJ = ; EI = ; EJ = ; Cel = ; Wr = ; Ai = ; Bi = ; Aout = ; Bout = ; cae (y) S: begi LI = ; It = ; S2: begi Ai = ; LJ = ; S3: EJ = ; S4: begi Bi = ; Cel = ; S5: ; // o output aerted i thi tate S6: begi Cel = ; Wr = ; Aout = ; S7: begi Wr = ; Bout = ; S8: begi Ai = ; if (!zj) EJ = ; ele begi EJ = ; if (!zi) EI = ; ele EI = ; S9: Doe = ; cae cotiued i Part c. Figure Verilog code for the ortig circuit (Part b).
29 //datapath circuit rege Reg (RData, Clock, Reet, Ri, R); defparam Reg. = ; rege Reg (RData, Clock, Reet, Ri, R); defparam Reg. = ; rege Reg2 (RData, Clock, Reet, Ri2, R2); defparam Reg2. = ; rege Reg3 (RData, Clock, Reet, Ri3, R3); defparam Reg3. = ; rege RegA (ABData, Clock, Reet, Ai, A); defparam RegA. = ; rege RegB (ABData, Clock, Reet, Bi, B); defparam RegB. = ; aig BltA = (B < A)? : ; aig ABMux = (Bout == )? A : B; aig RData = (WrIit == )? ABMux : DataI; upcout OuterLoop (2 b, Reet, Clock, EI, LI, Ci); upcout IerLoop (Ci, Reet, Clock, EJ, LJ, Cj); aig CMux = (Cel == )? Ci : Cj; aig IMux = (It == )? CMux : RAdd;! cotiued i Part d. Figure Verilog code for the ortig circuit (Part c).
30 Wr, IMux) begi cae (IMux) : ABData = R; : ABData = R; 2: ABData = R2; 3: ABData = R3; cae if (WrIit Wr) cae (IMux) : {Ri3, Ri2, Ri, Ri} = 4'b; : {Ri3, Ri2, Ri, Ri} = 4'b; 2: {Ri3, Ri2, Ri, Ri} = 4'b; 3: {Ri3, Ri2, Ri, Ri} = 4'b; cae ele {Ri3, Ri2, Ri, Ri} = 4'b; aig zi = (Ci == 2); aig zj = (Cj == 3); aig DataOut = (Rd == )? 'bz : ABData; module Figure Verilog code for the ortig circuit (Part d).
31 (a) Loadig the regiter ad tartig the ort operatio (b) Completig the ort operatio ad readig the regiter Figure Simulatio reult for the ort operatio.
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