Exercise 1. Due to Sunday, 27/12/2009

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1 1 بسم اهلل الرحمن الرحيم Islamic University of Gaza Computer Engineering Department Eng. Husam Alzaq, Eng. Mahmoad Alhabbash and Eng. Huda Sammour Due to Sunday, 27/12/2009 Exercise 1 This is a three-part question about critical path calculation. Consider a simple single cycle implementation of MIPS ISA. The operation times for the major functional components for this machine are as follows: Below is a copy of the MIPS single-cycle datapath design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. All instructions have the same instruction fetch and decode steps. The basic register transfer of the instructions are: Fetch/Decode: Instruction <- IMEM[PC]; R-type: R[rd] <- R[rs] op R[rt]; PC <- PC + 4; load: R[rt] <- DMEM[ R[rs] + signext(offset)]; PC <- PC +4; store: DMEM[ R[rs] + signext(offset)] <- R[Rt]; PC <- PC +4;

2 2 (Part A) In the table below, indicate the components that determine the critical path for the respective instruction, in the order that the critical path occurs. If a component is used, but not part of the critical path of the instruction (ie happens in parallel with another component), it should not be in the table. The register file is used for reading and for writing; it will appear twice for some instructions. All instruction begins by reading the PC register with a latency of 2ns. (Part B) Place the latencies of the components that you have decided for the critical path of each instruction in the table below. Compute the sum of each of the component latencies for each instruction. (Part C)

3 Use the total latency column to derive the following critical path information: Given the data path latencies above, which instruction determines the overall machine critical path (latency)?

3 3 Use the total latency column to derive the following critical path information: Given the data path latencies above, which instruction determines the overall machine critical path (latency)? What will be the resultant clock cycle time of the machine based on the critical path instruction? What frequency will the machine run? Exercise 2 Exercise 3 Consider the performance of two single-cycle MIPS R2000 machines, given the following assumptions:

4 (i) that the operation time of the major functional units of the MIPS R2000 CPU is: Memory units: 2 ns; ALU: 2 ns; Register access (read or write): 1 ns (ii) that the multiplexors, control unit, PC accesses, sign extension unit and wires have no delay (iii) that the instruction mix is 30% loads, 15% stores, 35% R-format instructions, 15% branches (all taken) and 5% jumps. 4 Compare execution times of the two implementations: where every instruction executes in 1 clock cycle of fixed length. where every instruction executes in 1 clock cycle using a variable-length clock of minimum duration per instruction. Exercise 4 We wish to add the instruction lui (load upper immediate) to the Multicycle datapath described in this chapter. This instruction is described in Chapter 2 on page 95. Add any necessary datapaths and control signals to the Multicycle datapath of Figure 5.28 on page 323 and show the necessary modifications to the finite state machine of Figure 5.37 on page 338. You may find it helpful to examine the execution steps shown on pages 325 through 329 and consider the steps that will need to be performed to execute the new instruction. You can photocopy existing figures to make it easier to show your modifications. Try to find a solution that minimizes the number of clock cycles required for the new instruction. Please explicitly state how many cycles it takes to execute the new instruction on your modified datapath and finite state machine. Exercise 5 We wish to add the instruction sll to the single-cycle datapath described in Chapter 5. Add any necessary data paths and control signals to the single cycle datapath. Is this an R- format, I- format, or J-format instruction? You can show your additions on scanned copy of this figure. Exercise 6 Explain why it is not possible to modify the single-cycle implementation to the implement the load with increment instruction without modifying the register file, where the local with increment instruction l-inc (load with increment) performs the following task in a single step: lw $rt, L($rs) addi $rs, $rs, 4

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For More Practice FMP

For More Practice FMP FMP 5.13-1 Single Cycle Datapaths with Floating Point 5.4 [5] < 5.4> Suppose we have a floating-point unit that requires 400 ps for a floating-point add and 600 ps for a floating-point multiply, not including