Recap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt

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1 Recap: The MIPS Subset EEL-47 - Computer Architecture Single-Cycle Logic ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits 2 bits 5 bits 5 bits bits LOAD and STORE lw rt, rs, imm sw rt, rs, imm BRANCH: beq rs, rt, imm JUMP: j target target address bits bits EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo Recap: A Single Cycle path We have everything ecept control signals (underline) Today s lecture will show you how to generate the control signals RegWr imm -bit Etender Src ctr In <:> <2:25> <:2> MemWr <:5> <:5> Imm The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input path Output Today s Tic: Designing the for the Single Cycle path EEL-47 Renato Figueiredo EtOp EEL-47 Renato Figueiredo

2 Outline of Today s Lecture Recap and Introduction for Register-Register & Or Immediate instructions signals for Load, Store,, & RTL: The ADD 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits add rd, rs, rt Building a local controller: The main controller Summary mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual eration PC <- PC + 4 Calculate the net instruction s address EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo at the Beginning of / Fetch the instruction from memory: <- mem[pc] This is the same for all instructions PC imm <5:> EEL-47 Renato Figueiredo PC<:28> Target <25:> SignEt 4 = previous = previous = previous r<:2> r<:> <:> The Single Cycle path during and = = RegWr = -bit imm EEL-47 Renato Figueiredo R[rd] <- R[rs] + / - R[rt] EtOp = Etender 2 = ctr = or rs rt rd shamt t Src = In <:> <2:25> <:2> = MemWr = <:5> <:5> Imm

3 The Single Cycle path during and R[rd] <- R[rs] + / - R[rt] npc_sel= +4 = RegWr = -bit imm EEL-47 Renato Figueiredo rs rt rd shamt t EtOp = Etender 2 ctr = or Src = In <:> <2:25> <:2> = MemWr = <:5> <:5> Imm at the End of and PC <- PC + 4 This is the same for all instructions ecept: and PC imm <5:> EEL-47 Renato Figueiredo PC<:28> Target <25:> SignEt 4 = = = r<:2> r<:> <:> The Single Cycle path during Or Immediate = = RegWr = ctr = Or -bit imm R[rt] <- R[rs] or Et[Imm] = Etender 2 Src = In <:> <2:25> <:2> MemWr = <:5> <:5> Imm = The Single Cycle path during Or Immediate = RegWr = imm -bit Etender 2 R[rt] <- R[rs] or Et[Imm] npc_sel= +4 ctr = Or Src = In <:> <2:25> <:2> MemWr = <:5> <:5> Imm = EEL-47 Renato Figueiredo EtOp = EEL-47 Renato Figueiredo EtOp =

4 The Single Cycle path during Load 2 The Single Cycle path during Load 2 R[rt] <- {R[rs] + SignEt[imm]} = = RegWr = -bit imm EEL-47 Renato Figueiredo EtOp = = Etender Src = ctr = In <:> <2:25> <:2> MemWr = <:5> Imm = <:5> R[rt] <- {R[rs] + SignEt[imm]} = RegWr = imm EEL-47 Renato Figueiredo -bit Etender EtOp = npc_sel= +4 ctr = Src = In <:> <2:25> <:2> MemWr = <:5> Imm = <:5> The Single Cycle path during Store 2 The Single Cycle path during Store 2 {R[rs] + SignEt[imm]} <- R[rt] = = RegWr = -bit imm EEL-47 Renato Figueiredo EtOp = = Etender ctr = In Src = <:> <2:25> <:2> = MemWr = <:5> <:5> Imm {R[rs] + SignEt[imm]} <- R[rt] = RegWr = imm EEL-47 Renato Figueiredo -bit EtOp = Etender npc_sel= +4 ctr = In Src = <:> <2:25> <:2> = MemWr = <:5> <:5> Imm

5 The Single Cycle path during if (R[rs] - R[rt] == ) then <- ; else <- = = RegWr = -bit imm EEL-47 Renato Figueiredo EtOp = = Etender 2 Src = ctr = In <:> <2:25> <:2> MemWr = <:5> <:5> Imm = at the End of if ( == ) then PC = PC SignEt[imm]*4 ; else PC = PC + 4 PC imm <5:> EEL-47 Renato Figueiredo PC<:28> Target <25:> SignEt 2 4 = = = Assume = to see the interesting case. r<:2> r<:> <:> The Single Cycle path during target address at the End of target address Nothing to do! Make sure control signals are set correctly! = = RegWr = ctr = -bit imm EEL-47 Renato Figueiredo EtOp = = Etender Src = In <:> <2:25> <:2> MemWr = <:5> <:5> Imm = PC <- PC<:29> concat target<25:> concat PC imm <5:> EEL-47 Renato Figueiredo PC<:28> Target 4 <25:> SignEt = = = r<:2> r<:> <:>

6 Step 4: Given path: RTL -> A Summary of Signals Inst Op <:> <2:25> Fun <2:25> <:2> <:5> <:5> Imm inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 src = RegB, ctr = add, = rd, RegWr, npc_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 src = RegB, ctr = sub, = rd, RegWr, npc_sel = +4 ORi R[rt] < R[rs] + zero_et(imm); PC < PC + 4 src = Im, Et = Z, ctr = or, = rt, RegWr, npc_sel = +4 npc_sel RegWr EtOp Src ctr MemWr Equal LOAD R[rt] < MEM[ R[rs] + sign_et(imm)]; PC < PC + 4 src = Im, Et = Sn, ctr = add,, = rt, RegWr, npc_sel = +4 DATA PATH STORE MEM[ R[rs] + sign_et(imm)] < R[rs]; PC < PC + 4 src = Im, Et = Sn, ctr = add, MemWr, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_et(imm)] else PC < PC + 4 npc_sel = Br, ctr = sub EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo A Summary of the Signals *The Concept of Local Decoding See We Don t Care :-) MIPS ref. chart add sub ori lw sw beq jump Src RegWrite MemWrite EtOp ctr<2:> Or 2 R-type rs rt rd shamt t add, sub I-type ori, lw, sw, beq J-type target address jump EEL-47 Renato Figueiredo Src RegWrite MemWrite EtOp <N:> EEL-47 Renato Figueiredo R-type Main Or R-type, control selects by N (Local) ctr

7 The Encoding of *The Decoding of the Field Main N (Local) ctr Main N (Local) ctr In this eercise, has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (), and (4) To implement the full MIPS ISA, has to be bits to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (), (4), and (5) And (Eample: andi) (Symbolic) R-type Or <2:> EEL-47 Renato Figueiredo (Symbolic) R-type Or <2:> 2 R-type rs rt rd shamt t t<5:> Operation ctr add subtract and or set-on-less-than EEL-47 Renato Figueiredo ctr<2:> Operation And Or Set-on-less-than The Truth Table for ctr t<:> Op. The Logic Equation for ctr<2> R-type ori lw sw beq (Symbolic) R-type Or <2:> add subtract and or set-on-less-than bit<2> bit<> bit<> bit<> bit<2> bit<> bit<> ctr<2> bit<2> bit<> bit<> bit<> bit<2> bit<> bit<> Operation ctr bit<2> bit<> bit<> Or And Or Set on < X Y Z A B C D ctr<2> =!<2> & <> + This makes <> a don t care <2> &!<2> & <> &!<> =!X&Z + X&!A&!B&C&!D + X&A&!B&C&!D =!X&Z + X&!B&C&!D EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo

8 The Logic Equation for ctr<> The Logic Equation for ctr<> bit<2> bit<> bit<> bit<> bit<2> bit<> bit<> ctr<> ctr<> =!<2> &!<> + <2> &!<2> &!<> bit<2> bit<> bit<> bit<> bit<2> bit<> bit<> ctr<> ctr<> =!<2> & <> + <2> &!<> & <2> &!<> & <> + <2> & <> &!<2> & <> &!<> EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo The Block Step 5: Logic for each control signal (Local) ctr npc_sel <= if (OP == BEQ) then EQUAL else src <= if (OP == ype ) then regb else immed ctr<2> =!<2> & <> + <2> &!<2> & <> &!<> ctr<> =!<2> &!<> + <2> &!<2> &!<> ctr<> =!<2> & <> + <2> &!<> & <2> &!<> & <> + <2> & <> &!<2> & <> &!<> ctr <= if (OP == ype ) then t elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add EtOp <= MemWr <= <= RegWr: <= : <= EEL-47 Renato Figueiredo EEL-47 Renato Figueiredo

9 Step 5: Logic for each control signal npc_sel <= if (OP == BEQ) then EQUAL else src <= if (OP == ype ) then regb else immed ctr <= if (OP == ype ) then t elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add EtOp <= if (OP == ORi) then zero else sign MemWr <= (OP == Store) <= (OP == Load) RegWr: <= if ((OP == Store) (OP == BEQ)) then else : <= if ((OP == Load) (OP == ORi)) then else EEL-47 Renato Figueiredo The Truth Table for the Main Src RegWrite MemWrite EtOp EEL-47 Renato Figueiredo Main Src : (Symbolic) R-type Or <2> <> <> (Local) ctr The Truth Table for RegWrite RegWrite PLA Implementation of the Main.. <> <> <> <> <> <> RegWrite = R-type + ori + lw =! &!<4> &!<> &!<2> &!<> &!<> (R-type) +! &!<4> & <> & <2> &!<> & <> (ori) + &!<4> &!<> &!<2> & <> & <> (lw).. <> <> <> <> <> EEL-47 Renato Figueiredo <> RegWrite EEL-47 Renato Figueiredo RegWrite Src MemWrite EtOp <2> <> <>

10 Instr<:> Putting it All Together: A Single Cycle Processor RegWr Main imm Instr<5:> EEL-47 Renato Figueiredo -bit Src : Etender EtOp Instr<5:> Src ctr In <:> <2:25> <:2> MemWr ctr <:5> <:5> Imm PC,,, Op, Func ctr Worst Case Timing (Load) EEL-47 Renato Figueiredo -to-q New Value Old Value Access Time New Value Delay through Logic New Value RegWr Old Value New Value Old Value Old Value EtOp Old Value New Value Src Old Value New Value Old Value New Value Old Value Delay through Etender & Old Value Register Write Occurs Register File Access Time New Value New Value Delay ress Old Value New Value Access Time Old Value New Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Access Time + Register File Access Time + Delay (address calculation) + Access Time + Register File Setup Time + Clock Skew Cycle time is much longer than needed for all other instructions EEL-47 Renato Figueiredo Summary Single cycle datapath => clocks per instruction=, clock cycle time => long 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Processor Input is the hard part MIPS makes control easier s same size immediates have same size & location Source registers always in same place Operations always on registers/immediates EEL-47 Renato Figueiredo path Output