TITAC 2: A 32-bit Scalable-Delay-Insensitive Microprocessor

Transcription

1 TITA 2: A 32-bit Scalable-Delay-Insensitive Microprocessor Takashi Nanya 1);2) Akihiro Takamura 2), Masashi Kuwako 1), Masashi Imai 1) Taro Fujii 2), Motokazu Ozawa 2), Izumi Fukasaku 2), Yoichiro Ueno 2) Fuyuki Okamoto 3), Hiroki Fujimoto 3), Osamu Fujita 3) Masakazu Yamashina 3), Masao Fukuma 3) 1) Research enter for Advanced Science and Technology, University of Tokyo 2) Department of omputer Science, Tokyo Institute of Technology 3) Microelectronics Research Laboratories, NE orporation TITA 2 FOIL 1 PRESENTATION OVERVIEW Why Asynchronous? Scalable-Delay-Insensitive Model TITA 2 Architecture Design Methodology hip Implementation onclusions TITA 2 FOIL 2

2 Why Asynchronous? MOS Technology in 27 (suggested at ISS97) Minimum Tr. size : :1m Number of logic Trs. : 5M=cm 2 Gate delay: 1ps hip area: 1cm 2 Fundamental Limitation: No signal can run 3mm, or probably even 1mm, in1ps. Wire delays moving into dominance on chip, getting harder and harder to control Synchronous systems cannot enjoy the ultra-high speed of picosecond devices!! TITA 2 FOIL 3 Why Asynchronous? Without any global clock 1. Potentially fast operation: Achieve average-case performance, i.e. optimize frequent operations and allow rare operations to spend more time Future technology scales up system performance 2. Timing-fault-tolerance: Robust and resilient with possible delay variation caused in fabrication process and operating environment 3. Low power consumption: Signal transitions occur only when and where needed 4. Ease of modular composition: No clock alignment needed at interfaces an overcome design complexity TITA 2 FOIL 4

3 Delay Models Assumptions on gate and wire delays. Play an essential role for dependable system design. Must be carefully examined and validated for design process, device technology and operating environment. Synchronous: Fixed or bounded delays that are known a priori Asynchronous: Variable delays that are unknown Fundamental-Mode: Bounded gate and wire delays Speed-Independent: Unbounded gate delays with no wire delays Delay-Insensitive: Unbounded gate delays and wire delays Quasi-Delay-Insensitive: Delay-Insensitive + Isochronic Forks (All branches of a fork have the same wire delay) TITA 2 FOIL 5 Observations Synchronous or Bounded-Delay model: Too optimistic of uncontrollable wire delays an make design expensive to guarantee reliable operations Delay-Insensitive or Quasi-Delay-Insensitive model: Too cautious against unlikely variations of delay an cause excessive hardware overhead and performance penalty What is likely in future VLSI technology? omponent delays are liable to uncontrollable variation through design phase, fabrication process, operating environment, aging, etc However, It is unlikely that some delays decrease (increase) while others increase (decrease)! Scalable-Delay-Insensitive (SDI) Model TITA 2 FOIL 6

4 Scalable-Delay-Insensitive (SDI) Model Unbounded delays with bounded relative variation ratio [Definition] onsider any two components 1 and 2 d 1 ;d 2 :Delays for 1, 2 D = d 1 =d 2 : Relative delay D of 1 to 2 D e : Estimated relative delay(at design phase) D a : Actual relative delay (through system s lifetime) R = D a =D e : Relative variation ratio Then, SDI model assumes that 1=K < R < K, where K is a constant (maximum variation ratio) TITA 2 FOIL 7 How SDI model works Specification: Transition t1 precedes transition t2 DI implementation : t2 must be caused by t1 t 1 t 2 QDI implementation: t2 may be caused by other fanout branch that shares its stem with t1 t 1 t 2 SDI implementation: that also causes t1,if t2 may be caused by common stem t K 1 d1 < d2 t d 1 t 1 t 2 d 2 TITA 2 FOIL 8

5 Example ompletion signal generation with QDI and SDI models EN Di Register (1bit) Racki Yi Di 3unit delay (data, en -> write) 2unit delay (write -> ack) Yi register select (1-outof-4) 4 write data 64 (2-rail 32bits) 32bit register en d 32 ack 32inputs -element (a) QDI model circuit 4inputs OR R QDI-ack 16 unit delay en d ack 6unit delay R 5unit delay d d d31 d31 4inputs OR 32inputs -element 5unit delay (b) SDI model circuit (Max. var. ratio = 2) SDI-ack 7 unit delay 6unit delay TITA 2 FOIL 9 SDI Design Methodology Step 1: Divide the entire system into functional blocks Step 2: Design each block as well as interconnections with QDI model Step 3: Determine K considering process technology and area size of each block Step 4: Apply SDI implementation to each QDI block whenever Kd1 < d2 TITA 2 design: K = 2 validated by limiting each functional block to be within a maximum of 1:93mm 2 1:93mm based on :5 MOS technology used TITA 2 FOIL 1

6 TITA 2 Architecture Asynchronous (clock-free) version of MIPS R2 Why MIPS R2? Nice target to demonstrate asynchronous design Easy to compare with synchronous counterpart Reasonably simple to design ompiler available Instruction set ; almost same Some instructions modified; multiply/divide resulting in least significant 32 bits 2 delay slots for branch instructions privileged instructions Object code: not compatible due to different instruction encoding TITA 2 FOIL 11 TITA 2 Instruction Set Logical Arithmetic Multiply Divide ompare Shift Load Store Branch Privileged Instructions AND, ANDI, OR, ORI XOR, XORI, LU, LUI ADD, ADDI, SUB, SUBI MUL, MULU DIV, DIVU, MOD, MODU SLT, SLTI, SLTU, SLTIU SLL, SRA, SRL SLLV, SRAV, SRLV LB, LBU, LH, LHU, LW SB, SH, SW J, JR, JAL, JALR BEQ, BNE, BGTZ, BLEZ BGEZ, BGEZAL, BLTZ, BLTZAL MOVSR, MOVRS, RFE, SYSALL TITA 2 FOIL 12

7 TITA 2 Architecture latch P IF stage ID stage EX stage ME stage WB Register File RD WR nextpc IR latch decode FWD SR DST latch ALU I-cache Memory ontroller write buffer address data R1 DST latch R1 DST latch 5-stage pipeline structure 8-KByte Instruction ache on chip (Data cache not implemented) 4 32-bit registers (R32 R39 for kernel-mode use only) Exception Handling (for user-mode only) External Interrupt Memory Protection TITA 2 FOIL 13 TITA 2 Design Features 2-level Delay Assumption SDI model for local functional blocks DI/QDI model for global interconnection Elastic asynchronous pipeline with FIFO buffer 2-rail 2-phase register transfer Idle-phase acceleration in 2-rail 2-phase data-path Adjustable delay elements for bundled-data path (cache, external bus) TITA 2 FOIL 14

8 Data-Path Encoding 2-rail 2-phase (return-to-zero) for register transfer Working phase: (; )! (; 1) : logic value has arrived (; )! (1; ) : logic value 1 has arrived Idle phase: (; 1)! (; ) : logic value has cleared away (1; )! (; ) : logic value 1 has cleared away Bundled-Data for on-chip cache and external interface TITA 2 FOIL 15 Asynchronous Pipeline Stage Model Request/Acknowledge Handshake Decentralized ontrol source latch 2-rail 2-phase combinational circuit 2-rail 2-phase destination latch read request combinational circuit acknowledge write acknowledge control circuit TITA 2 FOIL 16

9 Pipeline Latch Asynchronous FIFO: 4 primitive latches in cascade 7% faster than 3-latch FIFO rd_req X X Y X X Y wr_ack rd_req primitive latch (X, X) : write data input (Y, Y) : read data output TITA 2 FOIL 17 ombinational ircuit Design 2-rail logic implementation Direct mapping from BDD representation Easy to generate completion signals Hazard-free due to monotonic signal transitions DVSL implementation for frequently used modules (e.g. adders in multiplier) Gate-level implementation for other cases TITA 2 FOIL 18

10 2-rail Implementation from BDD A A A 1 A 1 A B A B B B B 1 1 B B F F F F F F ompletion TITA 2 FOIL 19 Idle Phase Acceleration (a) x1 x1 xn xn combinational circuit(f) combinational circuit(g) y1 y1 ym ym f(w) g(w) f(i) g(i) time (b) x1 x1 xn xn combinational circuit(f) combinational circuit(g) y1 y1 ym ym f(w) g(w) f(i) ia g(i) time ia f(w) : Working phase for "f" f(i) : Idle phase for "f" g(w) : Working phase for "g" g(i) : Idle phase for "g" TITA 2 FOIL 2

11 onversion between 2-railed data and Bundled-data Async RAM read-operation Async RAM write operation ADR Async RAM DATA DATA ADR Async RAM strobe ADR 2-1ONV delay RAM 1-2ONV DATA ADR DATA 2-1ONV delay delay WE RAM 2-rail 1-rail 2-rail strobe strobe Y1 Z1 X1 /X1 X2 /X2 Y1 Y2 Y2 /Z1 Z2 /Z2 TITA 2 FOIL 21 hip Implementation Fabricated in NE s.5 m, with 3 metal layers 3.3 V MOS Process Die size: 12:15mm 2 12:15mm 496,367 Logic Transistors + 8.6K Byte Memory macro Number of I/O pins: 164 (excluding power pins) TITA 2 FOIL 22

12 Die Photo REGISTER FILE INSTRUTION AHE INSTRUTION DEODER ME DATA MEM PROTETION ALU INSTRUTION FETH DIVIDER AHE TAG MULTIPLIER INST. MEM PROTETION TITA 2 FOIL 23 Performance Dhrystone V2.1 benchmark 52.3 VAX MIPS consuming 2.1 W at 3.3 V in room temperature Delay Insensitivity Power Supply Voltage: from 1.5 V to 6. V(variable) hip Surface Temperature: from 196 to +1 TITA 2 FOIL 24

13 Speed and Power onsumption vs. Supply Voltage 6 (at room temperature) Dhrystone [VAX MIPS] Speed [MIPS] Power [W] Power onsumption [W] Supply Voltage [V] TITA 2 FOIL 25 Tools Used ommercial: synchronous Verilog for RT-level and logic level simulation ell-3 Ensemble for layout and design rule check Saber for analog simulation of original macros Home-made: asynchronous Asynchronous synthesis from STG Speed-independent logic verification Delay evaluation Test generation TITA 2 FOIL 26

14 onclusions Asynchronous design methodology is now available Performance is already comparable with synchronous counterpart SDI model ensures both performance and dependability Easiness of modular design helps much More suitable architecture can fully exploit concurrency Testing is a major challenge TITA 2 FOIL 27