Implementing an Instruction Set
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1 Implementing an Instruction Set David E. Culler CS61CL Oct 28, 2009 Lecture 9 10/28/09 UCB CS61CL F09 Lec 9 1
2 Review: Synchronous Circuit Design Combinational Logic Blocks (CL) cyclic no internal state (no feedback) output only a function of inputs Registers (reg) collections of flip-flops clock distributed to all flip-flops LL CYCLES GO THROUGH REG! 10/14/09 CS61CL F09 2
3 MIPS: Register Transfers 10/14/09 CS61CL F09 3
4 MIPS: Register Transfers 10/28/09 UCB CS61CL F09 Lec 9 4
5 MIPS: Register Transfers 10/28/09 UCB CS61CL F09 Lec 9 5
6 Standard High-level Organization Controller accepts external and control input, generates control and external output and sequences the movement of data in the datapath. Datapath is responsible for data manipulation. Usually includes a limited amount of storage. Memory optional block used for long term storage of data structures. Standard model for CPUs, micro-controllers, many other digital sub-systems. Usually not nested. Often cascaded: 6
7 Datapath vs Control Datapath Controller signals Control Points Datapath: Storage, FU, interconnect sufficient to perform the desired functions Inputs are Control Points Outputs are signals Controller: State machine to orchestrate operation on the data path Based on desired function and signals 7
8 Register Transfer Level Descriptions standard high-level representation for describing systems. It follows from the fact that all synchronous digital system can be described as a set of state elements connected by combination logic (CL) blocks: RTL comprises a set of register transfers with optional operators as part of the transfer. Example: reg regb regc reg + regb if (start==1) reg regc Personal style: use ; to separate transfers that occur on separate cycles. Use, to separate transfers that occur on the same cycle. Example (2 cycles): reg regb, regb 0; regc reg; 8
9 The Methodology 1. Identify state and operations visible in the IS register transfer level operations of the IS 2. Select a set of storage elements, function units, and interconnections that realize all the architected state & operations plus internal state and operations 3. Map each instruction to register transfers on the data path 4. Identify the control points that cause the specified data transfers 5. Implement a controller that asserts those control points as a function of instruction, controller state, and signals from the data path 10/28/09 UCB CS61CL F09 Lec 9 9
10 r0 r1 r31 lo hi MIPS R3000 tiny subset 0 Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, rithmetic logical dd, ddu, Sub, SubU, nd, Or, Xor, Nor, SLT, SLTU, ddi, ddiu, SLTI, SLTIU, ndi, OrI, XorI, LUI SLL, SRL, SR, SLLV, SRLV, SRV Memory ccess LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JL, JR, JLR BEQ, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZL,BGEZL 10/28/09 cs61cl f09 lec 6 10
11 TinyMIPS Reg-Reg instructions (op == 0) addu R[rd] := R[rs] + R[rt]; pc:=pc+4 subu R[rd] := R[rs] - R[rt]; pc:=pc+4 Reg-Immed (op!= 0) lw R[rt] := Mem[ R[ rs ] + signex(im16) ] sw Mem[ R[ rs ] + signex(im16) ] := R[rt] Jumps j := addr 00 jr := R[rs] Branches BEQ := (R[rs] == R[rt])? + signex(im16) : +4 BLTZ := (R[rs] < 0)? + signex(im16) : +4 10/28/09 UCB CS61CL F09 Lec 9 11
12 dministration Project 3 is out due Sun 11/15 Homework 7 is out due Wed 11/4 Midterm 2 is Monday 11/9 10/28/09 UCB CS61CL F09 Lec 9 12
13 Starting Point RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt ld_pc pc2 ld_ir wrt m2d ld_reg sx_sel comp s2 s2d 10/28/09 UCB CS61CL F09 Lec 9 13
14 Ifetch: IR := Mem[] RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt ld_pc pc2 ld_ir wrt m2d ld_reg sx_sel comp s2 s2d RM_addr <- <- ; (pc2) IR_in <- D <- RM_data; (m2d, ~wrt) IR := IR_in; (ld_ir) 10/28/09 UCB CS61CL F09 Lec 9 14
15 Exec: rithmetic RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt ld_pc pc2 ld_ir wrt m2d rs rt rd ld_reg sx_sel comp s2 s2d R[rd] := R[rs] + R[rt];(~sx_sel,~comp,s2D,ld_reg,~wrt) R[rd] := R[rs] R[rt];(~sx_sel, comp,s2d,ld_reg,~wrt) 10/28/09 UCB CS61CL F09 Lec 9 15
16 Exec: LW RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt ld_pc pc2 ld_ir wrt m2d rs rt rd rt_sel ld_reg sx_sel comp s2 s2d R[rt]:= Mem[R[rs]+SXim16]; sx_sel,~comp,s2,~pc2,~wrt,m2d,ld_reg rt_sel 10/28/09 UCB CS61CL F09 Lec 9 16
17 Exec: SW RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt ld_pc pc2 ld_ir wrt m2d rs rt rd rt_sel ld_reg sx_sel comp s2 s2d Mem[R[rs]+SXim16]:= R[rt]; 10/28/09 UCB CS61CL F09 Lec 9 17
18 Exec: SW RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd ld_pc pc2 ld_ir wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d Mem[R[rs]+SXim16]:= R[rt]; b2d, sx_sel, ~comp, s2, ~s2d, ~m2d, wrt, ~ld_reg, ~pc2 10/28/09 UCB CS61CL F09 Lec 9 18
19 Exec: := +4 RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd ld_pc pc2 ld_ir wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d ld_pc 10/28/09 UCB CS61CL F09 Lec 9 19
20 Exec: := +4 RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd ld_pc pc2 ld_ir wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d ld_pc 10/28/09 UCB CS61CL F09 Lec 9 20
21 Exec: Jump RM D +4 IR ~ B Ci sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d j := addr 00 jr := R[rs] 10/28/09 UCB CS61CL F09 Lec 9 21
22 Exec: Branch RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d BEQ := (R[rs] == R[rt])? + signex(im16) : +4 BLTZ := (R[rs] < 0)? + signex(im16) : +4 10/28/09 UCB CS61CL F09 Lec 9 22
23 Exec: Branch RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d := (R[rs] == R[rt])? + signex(im16) : +4 n_sel = EQ? pcdd : Inc BLTZ := (R[rs] < 0)? + signex(im16) : +4 10/28/09 UCB CS61CL F09 Lec 9 23
24 DataPath + Control RM D +4 IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d 10/28/09 UCB CS61CL F09 Lec 9 24
25 Levels of Design Representation CS 61C Pgm Language sm / Machine Lang Instruction Set rch Machine Organization HDL FlipFlops Gates Circuits EE 40 Devices Transistor Physics Transfer Function 25
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