Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing for IoT Applications

Transcription

1 5th Berkeley Symposium on Energy Efficient Electronics & Steep Transistors Workshop 10:45-11:05, Oct. 19, Auditorium on the 3rd floor of Sutardja Dai Hall at the UC Berkeley campus, San Francisco, CA, USA Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing for IoT Applications Takahiro Hanyu 1,2,3 [Contributors] D. Suzuki 5, M. Natsui 1,2,3, N. Onizawa 5, S. Ikeda 1,3,4, T. Endoh 1,3,6, and H. Ohno 1,3,4 1 Center for Spintronics Integrated Systems, Tohoku University, JAPAN 2 Laboratory for Brainware Systems, RIEC, Tohoku University, JAPAN 3 Center for Innovative Integrated Electronic Systems (CIES), Tohoku University, JAPAN 4 Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University, JAPAN 5 Frontier Research Institute for Interdisciplinary Sciences, Tohoku University, JAPAN 6 Dept. of Electrical Engineering, Tohoku University, JAPAN Acknowledgement: A part of this work was supported by ImPACT of CSTI, CIES s Industrial Affiliation On the STT MRAM program, and ACCEL under JST.

2 Outline Background & Motivation ~Nonvolatile Logic-in-Memory Architecture~ Design of Nonvolatile FPGA VLSI CAD Environment Conclusions & Future Prospects 1

3 Background: IoT/IoE Era Processor Sensor Interface Radio Memory Power-Constrained SoC Sensors, actuators, Button cells, etc... Processor Radio Security Sensor Interface Memory Display IoT: Internet of Things IoE: Internet of Everything Power management Video Middle/high-End IoT SoC Automotive, cloud, smartphone, etc... Require a variety of VLSI Processors under Power-Dissipation Limit 2

4 Problem: Energy Gap [Ref.] Y. Liu, et al., ISSCC, pp , Feb Standby power consumption is a critical issue for IoT applications. 3

5 Recent Trends in DNN Hardware K. Bong, et al., ISSCC Dig. Tech. Pap. pp , Performance (TOPS) 10 1 Targe t area SoC TOPS mW FPGA ~1.2 TOPS ~40 W GPU ~5.75 TOPS ~250 W Power (W) FPGAS is a key device to realize energy-efficient hardware. 4

6 Power-Supply Stability Problem 1) Power supply is frequently shut down in IoT applications. 2) Processing overhead is serious in conventional volatile processor, because data must be backup/recall to/from external NVM. Percentage of Completion Done 100% Volatile Start Power supply 0% B R B R B R B R ON OFF ON OFF ON OFF ON OFF ON B:Backup R:Recall Time 5

7 Power-Supply Stability Problem 1) Power supply is frequently shut down in IoT applications. 2) Processing overhead is serious in conventional volatile processor, because data must be backup/recall to/from external NVM. 3) Immediate backup/recall are possible in a nonvolatile processor. Percentage of Completion Done 100% Nonvolatile Volatile Start 0% Power supply B R B R B R B R ON OFF ON OFF ON OFF ON OFF ON B:Backup R:Recall Time 6

8 Nonvolatile Memories Flash FRAM Spin device Access speed Middle High High Non-destructive read Write endurance Good Weak Good Bad Weak Good Scalability Good Weak Good Operation voltage Bad Weak Good READ WRITE READ WRITE 2-Terminal 3-Terminal Low resistance 0 High resistance 1 7

9 What is a Nonvolatile VLSI? Conventional architecture Wire Logic Memory Transfer bottleneck Logic-in-memory architecture Non-volatile spin element MTJ layer Logic Memory CMOS layer Leakage current -Logic and memory modules are separated -Many interconnections between modules -Wire delay dominates chip performance -Global wires requires large drivers -On-chip memory is volatile -Power supply must be continuously applied Silicon Logic Magnetic Tunnel Junction (MTJ) device -Non-volatility -Unlimited endurance -Fast writability -Scalability -CMOS compatibility -3-D stack capability -Storage is nonvolatile -MTJ devices are put on the CMOS layer -Storage/logic are merged Delay: Long, Static power: High Delay: Short, Static power: Low 8

10 Nonvolatile VLSI Processor Architecture Flash DRAM GP-Logic: General-purpose logic SP-Logic: Special-purpose logic 1 st gen. NV Processor Spin RAM NV SRAM NV FF GP-Logic Si NV FF SP-Logic 2 nd gen. NV Processor Spin RAM NV SRAM NVLIM GP-Logic Si NVLIM SP-Logic Nonvolatile Field-Programmable Gate Array (FPGA) Nonvolatile Microcontroller LSI General-purpose logic Nonvolatile Ternary Content- Addressable Memory (TCAM) Special-purpose logic 9

11 Outline Background & Motivation ~Nonvolatile Logic-in-Memory Architecture~ Design of Nonvolatile FPGA VLSI CAD Environment Conclusions & Future Prospects 10

12 FPGA (Field-Programmable Gate Array) A B Ex: Half adder S C Circuit configuration True table A B S C Wiring TILE1 is connected to TILE2. Store into MTJs I/O PADs A FPGA I/O PADs Tile1 TILE2 I/O PADs I/O PADs S C Circuit functions are programmable by users. Circuit configuration including wiring is stored into MTJs. Therefore, there is no re-storing even when power supply is OFF and ON again. Suited to power-supply control The use of MTJs together with power gating makes standby power reduced B 11

13 Structure of TILE Circuit info. (Truth tbl.) I/Os from Neighbor CLB n X Wire truck Tile Logic Element (LE) Circuit info. (Truth tbl.) CLB LE CB RS Combination circuit Lookup table (LUT) I/Os from neighbor CLB SB RS FF CB RS I/Os from neighbor Tiles Seq. circuit MUX I/Os from Neighbor Titles Z Circuit info. (Wire info.) Configurable logic block (CLB) Logic function of Tile Connection Block (CB) Connect to neighbor CLB Switch Block (SB) Connect to neighbor Titles Routing switch (RS) Circuit info. (Wire info.) Latch Design arbitrary comb./ seq. circuits. FF is changed to nonvolatile one. NMOS pass gate with NV-latch determines wire-truck information. 12

14 Logic-in-Memory(LIM) Architecture LIM-based nonvolatile lookup table (NV-LUT) circuit Input Output Selector (read) Nonvolatile SRAM cell array (Large area cost) Selector (write) Circuit information Sense amp. & controller (8 Transistors) 2 MTJ devices Nonvolatile SRAM cell Shared Imput Shared Output Sense amp. Selector (read) MRAM cell array (Small area cost) Selector (write) &controller Circuit information 1 access transistor 1 MTJ device MRAM cell Nonvolatile SRAM-based (conventional) LIM-based (proposed) 13

15 Comparison of Multi-Input LUT circuit # of transistors NV-SRAM (Y. Shuto et al., Intermag 2011) NV-SRAM (W. Zhao et al., PSS-A, 2008.) SRAM (P. Chow et al., IEEE Trans. VLSI, 1999) NV-LIM (proposed) 31% off VLSI2009 SSDM % off 62% off 56 th MMM JAP2012 SSDM2011 JJAP2012 # of inputs 14

16 Logic-in-Memory(LIM) Architecture LIM-based nonvolatile lookup table (NV-LUT) circuit Input Output Selector (read) Nonvolatile SRAM cell array (Large area cost) Selector (write) Circuit information Sense amp. & controller (8 Transistors) 2 MTJ devices Nonvolatile SRAM cell Shared Imput Shared Output Sense amp. Selector (read) MRAM cell array (Small area cost) Selector (write) &controller Circuit information 1 access transistor 1 MTJ device MRAM cell Nonvolatile SRAM-based (conventional) LIM-based (proposed) 15

17 NV LUT Circuit SE: Shift enable WE: Write enable RE: Read enable Access transistor Sense amp. (SA) Out Controller SE WE M[0] M[1] M[2 K -1] Shift input Circuit info. Address X Logic input Y 6 6 MUX MUX Write driver (WD) 6 SEL[0] SEL[1] SEL[63] Selector (Read and write) RE Hardware cost for the selector is reduced. 16

18 Comparison of Tr. Counts Transistor counts of 6-input LUT circuit Selector Memory Controller % SRAM NV-SRAM Proposed LIM-based circuitry Transistor counts reduction in memory part Selector is shared in both read and write operations 64% of transistor counts reduction compared to SRAM-based LUT circuit 17

19 Comparison of Power Dissipation Power consumption of 6-input LUT circuit 8-bit shift 1200 Active Standby Write Power [nw] % Cycle (200 us) 90nm CMOS technology Write current:100ua@2ns Time NV-SRAM (1) Store data into MTJ devices every time after 1-bit shift operation NV-SRAM (2) Store data into MTJ devices only before power off 99% of power reduction compared to SRAM-based LUT circuit 18

20 Outline Nonvolatile Logic-in-Memory Architecture Overview Design of an NV FPGA Other Possibility Conclusions & Future Prospects 19

21 VLSI CAD for MTJ/MOS-Hybrid Circuit Design Logic Synthesis Circuit Simulation Layout Logic-Synthesis Ex. Circuit Editor 1h-spice 上でモデルファイルを使用する際は予めコメントアウトをしておく (.libでも同様).h-spiceでシミュレーションを行うときにコメントアウトを外す Layout result Logicsynthesis command executed Standard logic cells Nonvolatile flip-flop cells 20

22 Fabricated Nonvolatile Components STT-SRAM (2013 VLSI Symp.) TCAM (2013 VLSI Symp.) McGill Univ. (2013) NV-MPU (2013 ASSCC) ID WB EX Out Random Logic (2013 ISSCC) IF MEM NV-MCU (2014 ISSCC) RF CPU Inst. Data mem. mem. メモリ MRAM PS ctrl. BUS Port SP H/W ACC NV-FPGA (2015 VLSIC) Clock ctrl. Timer Timer S-link S-link ADC GP H/W ACC 21

23 Outline Background & Motivation ~Nonvolatile Logic-in-Memory Architecture~ Design of Nonvolatile FPGA VLSI CAD Environment Conclusions & Future Prospects 22

24 Conclusions & Future Prospects Propose a MOS/MTJ-hybrid circuit (nonvolatile logic-in-memory circuit using MTJ devices) style for IoE applications Key technologies; novel NV LUT Design & VLSI CAD environment to realize practical LSI. It could open ultra-low-power IoT application paradigm. Security Infrastructure Energy Buildings Agriculture Medical 23

25 Towards Brain-Inspired LSI Performance in real-world processing 1990 for real world Example: Brain-inspired computer Brain-like computing + conventional tech. Basic element using brain-like computing (IEEE Signal Proc. Let., 2015) Computing wall Conventional computer for computer world True North (IBM, USA), Aug Year Brainware Software/hardwaremixed structure IBM, USA(Aug. 7, 2014) True North hardware Big gain for brain-like comp. Not reached to goal of real brain-like computing <Aim of PJ> Explore mechanism & architecture for brainware. (Brainware LSI PJ:start in 2014) Tohoku U. has a world-class MTJ fabrication process technology. Open up a real brain-like computing paradigm! 24