Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-302 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources nd or e-mil or for technicl support. Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory Contributed by Ke Zhn nd Dniel Zho Rev 1 November 10, 2006 Introduction NAND flsh memory technology hs emerged s suitble, high-density lterntive to hrd disk drives in power-sensitive portble devices. Tody, most cellulr telephones, Personl Digitl Assistnts (PDAs), digitl cmers, Portble Medi Plyers (PMPs), nd other mobile computing/communictions/consumer products use NAND flsh memory to store incresingly lrge medi files, dt, nd operting systems. Blckfin processors re well-suited for portble systems due to their low power dissiption, high performnce, nd convergent rchitecture. As such, there is growing demnd to interfce Blckfin processors to NAND flsh memories. This EE-Note describes how to interfce both MLC- nd SLC-type NAND flsh memories to ADSP-BF53x Blckfin processors. Included re the low-level driver functions, which were vlidted on hrdwre pltform consisting of NAND flsh dughter bord connected to n ADSP-BF533 EZ-KIT LITE (rev. 1.6) evlution system nd the VisulDSP (Updted April 2006) development tools. To provide flexibility to system designers, two pproches re provided. The memory devices used to demonstrte this interfce re Smsung s K9F2G08U0M SLC NAND flsh nd Toshib s TC58NVG3D4CTG MLC NAND flsh. NAND Flsh vs. NOR Flsh NOR flsh devices re widely used in the electronics industry. They offer n esy memory interfce nd re suitble for code execution, mking them idel for devices tht do not need dt storge. NOR memory offers good red performnce, but hs slow write/erse times. However, s modern devices become more nd more sophisticted, they need to store more dt nd progrms loclly while supporting fster erse/write times. NAND flsh offers ll of this, plus better prices, in cpcities rnging from 8 to 512 MB. NAND is n I/O device nd requires reltively complicted driver for ny opertion. Memory cells tht re ccessed frequently become more prone to bit errors. Thus, NAND flsh devices typiclly include extr memory so tht the NAND flsh file system cn replce bd blocks with good blocks without decresing the size of the vilble memory. A NAND flsh file system, such s JFFS2, will typiclly ttempt to evenly wer the whole memory to increse the life of the device. NAND Flsh: SLC vs. MLC There re two different types of NAND flsh devices in the mrket tody: Single-Level-Cell (SLC) devices nd Multi-Level-Cell (MLC) devices. MLC chip technology is cpble of storing two or more bits of dt per memory cell, while SLC chip technology llows just one bit of dt per memory cell. Copyright 2006, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 MLC chips provide much lrger storge cpcity thn SLC; however, they lso suffer from lower bndwidth for red nd write opertions. Also, the Error Correcting Code (ECC) requirement for MLC is higher thn for SLC, s MLC technology is more prone to bit errors. The cost per bit of MLC flsh is much lower thn tht of SLC devices. Figure 1 shows the comprison. Item SLC MLC Storge cpcity Smll Lrge Throughput High Low ECC 1bit/528B 4bit/528B Write/Erse Endurnce 100K times 10K times Cost High Low Figure 1. SLC vs. MLC Performnce Comprison MLC NAND flsh memory provides competitive level of performnce nd mkes high-density NAND crds more ffordble, enbling new brekthroughs in portble pplictions. SLC NAND flsh is pproprite for specific, high-performnce pplictions. SLC NAND flsh is better suited for pplictions tht require speed. It performs mny write/erse cycles tht require high endurnce nd high relibility, such s in solid-stte hrd disk drives nd devices used for seismic dt recording, networking, HDTV, br code scnners, shockproof PCs, flight recorders, hndheld code storge devices, s well s PDAs nd digitl still cmers. Typicl pplictions tht re well-suited for MLC NAND flsh memory include digitl video nd digitl still cmer memory crds, USB flsh drives, MP3 plyers, utomobile dignostic monitors, GPS devices, nimtronics devices, video gme crds, nd mny toy pplictions. Applictions tht my be suited for either MLC NAND or SLC NAND technology include memory crds for printers (fonts), cell phones, telecom pplictions, voice mil, nd TV set-top boxes. Figure 2 illustrtes the clssifictions. Figure 2. Typicl Applictions for SLC nd MLC Devices Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 2 of 11

3 NOR flsh memories nd other trditionl SRAM-like devices nd memories use discrete ddress dt buses nd bsic control signls. NAND flsh memory is optimized for lrge block trnsfers, incorporting single set of I/O pins tht re used for both ddress nd dt. For Blckfin processors, it is possible to mp the NAND flsh memory ports to synchronous memory spce nd ccess them s stndrd memory-mpped device. The hrdwre interfce for both SLC nd MLC NAND flsh is identicl. Bsic NAND Flsh Interfce NAND flsh devices utilize I/O pins for both ddress nd dt, s well s for commnd inputs. The commnd signls nd commnd words re the sme for both SLC nd MLC NAND flsh devices. This mkes the interfce to both SLC nd MLC flsh chips universl for ll Blckfin processors. Flsh memory is ccessed by column, pge, nd block. The red nd progrm opertions execute t the pge level, nd erse opertions re performed t the block level. The bsic commnds supported by NAND flsh memories re block erse, pge progrm, red sttus, nd pge red. The Chip Enble (CE#) pin should be sserted low to ccess the device. When sserted, the NAND flsh cn be controlled to ccept bytes provided by the host when the Write Enble (WE#) signl is sserted low or provide dt to the host when the Red Enble (RE#) signl is sserted low. When CE# is high, the chip ignores RE# nd WE#, nd the I/O is tri-stted. The Commnd Ltch Enble (CLE) signl is used to send commnds to the device when CE# is sserted. The Address Ltch Enble (ALE) signl is used to ltch the ddress into the ddress register of the flsh device. Figure 3 depicts the internl register ccessed s result of vlid combintions of CLE nd ALE. ALE CLE Register Selected 0 0 Dt Register 0 1 Commnd Register 1 0 Address Register 1 1 Reserved Figure 3. Vlid ALE/CLE Combintions Smsung K9F2G08U0M Interfce The Smsung K9F2G08U0M is offered in 256M x 8-bit (2G-bit) configurtion with spre 64M-bit cpcity. This memory device is n optiml solution for lrge nonvoltile storge pplictions such s solid-stte file storge nd other portble pplictions requiring non-voltile memory. The device is offered in 2.7 V, 3.3 V, nd 3.6 V supply voltge rnges. Typiclly, progrm opertion cn be performed in 200 µs on the 2112-byte pge, nd n erse opertion cn be performed in 2 ms on 128-Kbyte block. Ech byte in the dt pge cn be red in 30 ns. The I/O pins serve s the ports for ddress nd dt input/output, s well s for commnd input. One pge in the K9F2G08U0M consists of 2112 bytes, nd one block comprises 64 pges. Figure 4 shows the orgniztion of the K9F2G08U0M flsh memory device in terms of pges nd blocks. Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 3 of 11

4 Figure 4. K9F2G08U0M Flsh Memory Orgniztion Toshib TC58NVG3D4CTG10 Interfce The Toshib TC58NVG3D4CTG10 device is single 3.3 V 8-Gbit NAND Electriclly-Ersble nd Progrmmble Red-Only Memory (NAND E2PROM), orgnized s 2112 ( ) bytes per pge, 128 pges per block, nd 4160 ( ) blocks. The device hs two 2112-byte sttic registers tht llow progrm nd red dt to be trnsferred between the register nd the memory cell rry in 2112-byte increments. The erse opertion is implemented on single block unit. necessry delys to mtch the timing requirements for NAND ccess. Figure 5 shows detils regrding the connections between n ADSP-BF533 Blckfin processor nd Smsung K95G08U0M flsh memory device. NAND Flsh Interfce to the ADSP-BF53x Processor Becuse ADSP-BF53x Blckfin processors do not hve n on-chip NAND flsh controller, softwre driver is used to control nd ccess NAND flsh memory. Two pproches re used to interfce Blckfin processor to NAND flsh device: GPIO pins nd EBIU pins. Using GPIO Pins to Interfce to NAND Flsh The first pproch uses Generl-Purpose I/O pins (GPIOs) to drive ll the required control signls. This pproch requires creful timing for the Figure 5. Using GPIO for NAND Flsh Interfce Using EBIU Pins to Interfce to NAND Flsh A second pproch is to use the Externl Bus Interfce Unit (EBIU) nd single GPIO pin to communicte with the NAND flsh memory device. Stndrd NAND flsh requires tht its CE# remins vlid during the red busy period. So, for comptibility with both stndrd NAND flsh nd Chip Enble Don t Cre (CEDC) NAND flsh, GPIO pin is used to drive the CE# signl. All other signls re driven directly by the EBIU interfce. Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 4 of 11

5 Figure 6 shows detils regrding the connections between n ADSP-BF533 Blckfin processor nd Smsung K9F2G08U0M flsh memory device. which is the frequency t which ll synchronous memories interfced to the processor will operte. Since the EBIU is utomticlly controlled by the synchronous memory controller of the Blckfin processor, hooking the NAND flsh in this wy is simple nd yields optiml ccess performnce. Figure 6. Using EBIU Pins for NAND Flsh Interfce The EBIU cn be progrmmed to control up to four bnks of devices with very flexible timing prmeters. Ech bnk occupies 1-Mbyte segment, regrdless of the size of the device used, so these bnks will only be contiguous if ech is fully populted with 1 Mbyte of memory. The EBIU is clocked by the system clock (SCLK), NAND Flsh Driver Development This EE-Note provides bsic Smsung K9F2G08U0M nd Toshib TC58NVG3D4CTG NAND flsh driver for the two interfce pproches described bove. This section focuses on the second pproch implementtion nd provides timing wveforms for ech commnd. Listing 1 shows the code exmple for the block erse code implemented. bool _NF_Block_Erse(unsigned int Block_Address) unsigned chr NAND_Dt = 0; NAND_Address_Tble.Vlue = Block_Address << 12; Write_Commnd(0x60); Write_Address(NAND_Address_Tble.NAND_Address.NAND_Address_A12_A19, NAND_Address_Tble.NAND_Address.NAND_Address_A20_A27, NAND_Address_Tble.NAND_Address.NAND_Address_A28, NAND_Address_Tble.NAND_Address.NAND_Address_A0_A7, NAND_Address_Tble.NAND_Address.NAND_Address_A8_A11, 0x03); Write_Commnd(0xd0); while(!wit_nand_rady()); Write_Commnd(0x70); dely(50000); NAND_Dt = *pnand_data_reg; NAND_Finish(); if(nand_dt!= 0xe0)//0xc0) return flse; else return true; Listing 1. Block Erse Function Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 5 of 11

6 Listing 2 shows the code exmple using the pge write function. bool _NF_Pge_Write(unsigned int Block_Address,unsigned short Pge_Address,unsigned chr *psrc) int i; unsigned chr NAND_Dt; int NAND_Addr; NAND_Addr = (Block_Address << 12) Pge_Address; NAND_Address_Tble.Vlue = NAND_Addr; Write_Commnd(0x80); Write_Address(NAND_Address_Tble.NAND_Address.NAND_Address_A0_A7, NAND_Address_Tble.NAND_Address.NAND_Address_A8_A11, NAND_Address_Tble.NAND_Address.NAND_Address_A12_A19, NAND_Address_Tble.NAND_Address.NAND_Address_A20_A27, NAND_Address_Tble.NAND_Address.NAND_Address_A28, 0x05); dely(100); for(i = 0;i<DATA_NUM;i++) *pnand_data_reg = *(psrc+i); Write_Commnd(0x10); while(!wit_nand_rady()); Write_Commnd(0x70); dely(5000); NAND_Dt = *pnand_data_reg; NAND_Finish(); if(nand_dt!= 0xe0) return flse; else return true; Listing 2. Pge Write Function Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 6 of 11

7 Listing 3 shows the code exmple for the pge red code implemented. bool _NF_Pge_Red(unsigned int Block_Address,unsigned short Pge_Address,unsigned chr *pdes) int i; Write_Commnd(0x00); Write_Address(NAND_Address_Tble.NAND_Address.NAND_Address_A0_A7, NAND_Address_Tble.NAND_Address.NAND_Address_A8_A11, NAND_Address_Tble.NAND_Address.NAND_Address_A12_A19, NAND_Address_Tble.NAND_Address.NAND_Address_A20_A27, NAND_Address_Tble.NAND_Address.NAND_Address_A28, 0x04); Write_Commnd(0x30); while(!wit_nand_rady()); for(i = 0;i<DATA_NUM;i++) dely(600); *(pdes+i) = *pnand_data_reg; NAND_Finish(); return true; Listing 3. Pge Red Function The bsic NAND flsh drivers re bsed on low-level opertions, like Write_Commnd(), Write_Address(), Wit_NAND_RADY(), nd Set_CE(). These opertions hndle the GPIO nd ddress signls to mnipulte the flsh chip. Listing 4 is for the implementtion of the write commnd. void Write_Commnd(unsigned chr commnd) Set_CE(0); Write_NAND_FLASH_Com(commnd); Listing 4. Write_Commnd Function Listing 5 is the implementtion of the Set_CE signl function. void Set_CE(bool stte) if(!stte) *pfio_flag_d &= ~PF11; else *pfio_flag_d = PF11; Listing 5. Set_CE Function Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 7 of 11

8 Listing 6 is for the implementtion of the write flsh commnd/ddress register function. void Write_NAND_FLASH_Com(unsigned chr Write_Dt) *pnand_command_reg = Write_Dt; void Write_NAND_FLASH_Addr(unsigned chr Write_Dt) *pnand_address_reg = Write_Dt; Listing 6. Write_NAND_FLASH_Com nd Write_NAND_FLASH_Addr Functions DMA cn lso be used to perform red/write opertions from/to the flsh memory device. In this cse, the progrmmer should ensure tht no other core or DMA ccesses hppen to ny of the externl memory bnks. Any such ccesses cn cuse spurious RD# nd/or WR# pulses to the flsh memory device, which will compromise the integrity of the interfce nd yield unexpected results. CRO screenshots representing timing digrms for this interfce re shown in the following figures. Figure 7: Erse Commnd Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 8 of 11

9 Figure 8: Write Block Commnd Figure 9: Red Commnd Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 9 of 11

10 Figure 10: Red Chip ID Commnd ECC for NAND Flsh Both the SLC nd MLC NAND flshes require n Error Correction Code (ECC) to detect nd correct bit errors. The Reed-Solomon lgorithm is well-suited for this nd hs become the stndrd EEC method for both types of flsh memory. The RS encoder nd decoder for 72-bit RS (464, 456, 4) code hve been implemented nd integrted into the NAND flsh red/write drivers. NAND Flsh File Systems NAND flsh is optimized for file structures where ech word does not need to be red, but insted provides tht sectors of dt cn be moved to nd from the medi supporting hrddrive-like repository structure for dt storge to support file systems nd lloction tbles (FAT). Unlike NOR flsh, NAND flsh demnds mechnism, such s TrueFFS, to be implemented to mp bd blocks. File systems in the industry, such s JFFS, JFFS2, FAT, nd so on, re fesible for NAND flsh. Additionlly, the YAFFS (Yet Another Flsh File System) is the only file system tht hs been designed specificlly for use with NAND flsh under ny operting system. YAFFS uses journling error correction nd verifiction techniques to enhnce robustness, nd is designed to work within the constrints of nd exploit the fetures of NAND flsh in order to mximize performnce. A future revision of this EE-note will include the implementtion of specific file system for NAND flsh. Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 10 of 11

11 Conclusion Although ADSP-BF53x Blckfin processors do not hve n on-chip NAND controller, designers cn esily connect SLC nd MLC NAND flsh memory devices to EBIU or GPIO. Both interfces re semless, thus requiring no dditionl externl logic. Designers cn refer to the code supplied with this EE-Note to develop other NAND devices drivers. References [1] ADSP-BF533 Blckfin Embedded Processor Dt Sheet, Rev. C, My, Anlog Devices, Inc. [2] MLC NAND Performnce for Consumer Applictions, Toshib Americ Electronic Components, Inc. [3] K9F2G08U0M 256M x 8 Bit / 512M x 8-Bit NAND Flsh Memory Dt Sheet, Rev 1.2, October 31, Smsung Electronics, Inc. [4] TC58NVG3D4CTG 8 GBIT (1G 8 BIT / 512M 16 BIT) CMOS NAND E2PROM (Multi-Level-Cell) Dt Sheet, TOSHIBA Semiconductor Compny. [5] Appliction Note for NAND Flsh Memory, Rev. 2.0, December 1999, Memory Product & Technology Division from Smsung Electronics, Inc. [6] ADSP-BF533 Blckfin Processor Hrdwre Reference, Rev. 3.2, July Anlog Devices, Inc. [7] Interfcing NAND Flsh Memory with ADSP-2126x SHARC Processors (EE-279), Rev. 1, November Anlog Devices, Inc. Document History Revision Rev 1 November 10, 2006 by Ke Zhn & Dniel Zho Description Initil version Interfcing ADSP-BF53x Blckfin Processors to NAND FLASH Memory (EE-302) Pge 11 of 11