TSV : impact on microelectronics European 3D TSV Summit MINATEC Campus Grenoble, January 22nd, 2013

Transcription

1 TSV : impact on microelectronics European 3D TSV Summit MINATEC Campus Grenoble, January 22nd, 2013

2 Welcome in Grenoble Grenoble : 3D by Nature Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 2

3 Welcome in MINATEC Campus a living example of heterogeneous integration Nanoscience Campus Campus European Photon&Neutron Science Campus Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 3

4 Welcome in LETI Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 4

5 Welcome in LETI Leti: Mission & Focus A unique mission : Innovate with Industry Over 1,900 patents in portfolio 1,300 staff members 300 PhD Students & post-docs 250 industrial assignees 5

6 LETI : a complete toolset for 3D CMOS D 300 CMOS 200 mm MEMS & 3D 200 mm Fully operationnal 300mm line dedicated to 3D inaugurated in 2011, January Nanoscale Characterization

7 TSV applications Where do westand? What challenges & perspectives for digital applications Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 7

8 A whole set of applications Yole Development, 2011

9 Where do we stand In Production In Introduction In Development CIS (imagers) Interposers Power Sensors Passives Stacked memories LEDs Logic Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 9

10 3D Industrialization status Memory stack Memory Stack Samsung HMC cube Under industrialization Large players : Hynix; members of HMC consortium (Samsung Micron IBM Altera..); Ziptronix Logic on Logic Logic with TSV Interposer Logic with TSV Development near to production, mainly depending on market Many known technology players ST Renesas TI (IBM/Amkor) GF (Amkor) Samsung & fabless Qualcomm STE IBM ST/STE Imagers In production for Conventional Back Side Illuminated Imagers (BSI) Some recent announces from Sony for active BSI Interposer Passive: in production for TSMC (CoWos with Xilinx, Altera), Advanced level of R&D for Shinko Active: Qualcomm(& other fabless) Photonics: IBM, Alcatel-Lucent Logic on Logic Coarse partitionning: Prototyping and Development Fine partitionning: Pushed by academics Some fabless interested (Qualcomm) Xilinx Qualcomm 10

11 Interposers An important sector : As a market As a first introduction of digital «non-2d» architectures As a first return on invests With markets of various size to serve Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 11

12 Silicon Interposer Technology Interposer size: 26x26mm² (warp management required) TSV: 10x100µm Cu damascene routing : Metal1-Via1-Metal2, 0.5µm line/0.5µm space Micro copper pillars: Pitch 50µm, /interposer TSV exposure RDL and passivation: 10µm Line / Space, one level Large copper pillar: pitch 500µm, height 70µm cumulative Micro Cu pillar Damascene TSV RDL and Passivation Large Cu Pillar Joined Lab J. Charbonnier et al., ESTC 2012

13 Interposers are not just wires Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 13

14 Towards smart interposers : More than Wires Thermal Interposer Computing Power Lighting Application processor Active Interposer Power management High Voltage External I/O (Mature node) Passives Interposer Smart interposer Photonic Interposer RF Platform for Baseband Lighting Application Processor (decoupling capacitance) Health: Implantable electronics Servers Data centers Computing

15 Active Interposer Concept Heterogeneous integration rationale: Small dies shorten new process introduction and improve overall yield Analog design and IOs doesn t shrink a lot with process technology Short interconnect improves signal and power integrity SoCpartitioning into several dies, with different technology nodes Processing layer: High performance multicore processors Multi-core SoC SDRAM Memory layer: High bandwidth, Wide data interface Active Interposer: Analog, interconnect, memory control and I/O peripherals Multi-core SoC Multi-core SoC On LETI roadmap for 2015

16 Digital applications A generic trend and expectation : Power Efficiency MID Segment PC, Video, Gaming Servers Pour modifier: Insertion / En Tête/Pied de page -Titre de la présentation Auteur 16

17 A global approach to energy efficiency in nanoelectronics Multi-core HW/SW architectures Local & dynamical trade-offs New transistors (FinFET vs Planar/SOI) Integrated photonics Intrinsicpower consumption µ-proc to mem access Speed I/O 3D integration& architectures

18 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip)

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20 Face-to-Back integration WideIO Matrix TSV SoC Front Side Bumps WideIO Memory SoC In collaboration with 1,0 Cumulated percentage pourcentage Cumulated percentage cumulé 200mm & 300mm processes & characterization for face to back flow chart for Wide I/O, S. Chéramy & Al, 8th International Conference and Exhibition on Device Packaging (2012) 0,8 0,6 0,4 0,2 0,0 2,4 2,6 2,8 3,0 3,2 3,4 3,6 R 50 TSV (Ω) P01 P02 P03 P04

21 Face-to-Face Integration for logic/analog partitioning (65nm technology stacked on 65nm) BGA TSV BEOL Top / bottom dies connection Cu TSV Cu TSV Bottom die / BGA connection Cu RDL

22 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip)

23 Logic-on-logic : 3D Asynchronous NoC Easily stackable logic tiles A set of tiles will give you the performance for your application Increase number of applications for a single die, reach required volume production Constraints? High bandwidth between dies, Easy staking, no clock distribution issues Power distribution, Testability, Fault Tolerance Proposal : 3D Asynchronous NoC Fast serial link Full asynchronous logic Demonstration in 2014 NoC Serial Links 2D NoC Router 3D NoC Router Processing Unit

24 3D IC evolution Si interposer 2,5D 3D Wide IO Memory Logic-on-logic (Advanced on Mature) Logic-on-analog Large grain 3D partitionning ( 50µm pitch) Active interposer Modular and Stackable logic (3D Network-On-Chip) 3D Cache memory on manycore processor Fine grain 3D partitionning ( 10µm pitch)

25 3D Cache Memory on manycore Non-uniform Memory Architecture (NUMA) : splitting uniform cache into multiple banks interconnected with a NOC 3D stacking adding flexibility, high capacity and a gain on power consumption High bandwidth and fault tolerance 1Oµm TSV pitch required >10000 TSVs per chip Eric Guthmuller et al., Adaptive Stackable 3D Cache Architecture for Manycores, ISVLSI2012

26 TSV shrink for cost reduction Surface Cost TSV surface + Keep away zone (KAZ) Active + M1-Mx layers Number of TSVs (today 1000 for Wide IO memory) Si KAZ TSV diameter 6 Surface occupied by x TSV [mm²] TSV Surface [mm²] Si TSV diameter [µm] 26

27 Low diameter TSV 15µm 15µm 3µm M1 Reducing Si thickness : 15µm High Density TSV s demosntrated in 65nm MOSFETS M5 Investigation on TSV impact on 65nm CMOS devices and circuits H. Chaabouni, M. Rousseau, P. Leduc et al., IEDM 2010

28 Cu direct bonding Full characterization of Cu/Cu direct bonding for 3D integration, Rachid Taibi, Léa Di Ciocciob et al., ECTC2010 >90% yield of daisy Chain with x3µm² Cu contacts Contact resistance : 2,5mΩ Contact chain SEM cross section Optical top view Acoustic image of bonding 0.5 µm thick line standard deviation σ ~ 1.2% Resistance (Ω)

29 A global approach to energy efficiency in nanoelectronics Multi-core HW/SW architectures Local & dynamical trade-offs New transistors (FinFET vs Planar/SOI) Integrated photonics Intrinsicpower consumption µ-proc to mem access Speed I/O 3D integration& architectures

30 Design challenges : collaborative definition of flow with EDA partners Yesterday: Survivor kit - manual implementation of TSV - Manual partitioning with 2D tools 3D Stack definition - Multiple techno nodes - Die partitioning - Architecture exploration - Simultaneous floorplan and TSV location exploration Optimized design and modeling Multiple partnerships to prepare 3D design flow 3D Stack/Package analysis & optimization: - Early floorplan & TSV Placement - 3D Thermal Profile -3D Test 3D Implementation - 3D Floorplan - 3D Power planning - 2D Place & CTS & Route - 3D analysis (power/timing) - 3D Verification

31 Impact on advanced devices Thermal studies Possibility of measureafterback end 3D assembly & packaging Deep understanding of impact on CMOS BEOL top die 20% TSV Radius in <110> Rcupi+RCupB 15% complete design rules for design kits Lcupi+LCupB 10% amincissement RTSV Vsub 5% IFoucauts Stress impact Determination of the min distance TSV -MOS Electrical impact Interconnects modelization & density impact Mobility variation (%) LTSV 0% Mode de conduction -5% M -10% -15% -20% M Cox Cdep Vsub BEOL bottom die Csi Gsi CM1-Sub Cu stress Longitudinal NMOS Cbeol-Sub Transverse NMOS Longitudinal PMOS Transverse PMOS Distance from TSV (µm) MOS

32 Thermal challenges Long distance heat dissipation Local heatdissipation (hot spot removal) Thermal heat spreader (carbone graphite, Cu, AlN Dynamic temperature smoothing Heat spreader Phase change materials Temperature cold Thermal model and design Rules Time

33 Conclusions TSV and 3D have (and will have) a global impact Applications in Digital require a global approach Leti develops 3D globally: A generic toolbox available (technology & design) Capability to transform 3D concepts into silicon demonstrators A roadmap of developments and demonstrators Generic R&D run in open innovation model Specific developments and prototyping through proprietary cooperation

34 Thank you for your attention and questions