Lecture Notes Electrical Engineering Volume 53

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1 Lecture Notes Electrical Engineering Volume 53

2 Alexander Barkalov and Larysa Titarenko Logic Synthesis for FSM-Based Control Units ABC

3 Prof. Alexander Barkalov Institute of Informatics and Electronics University of Zielona Gora Podgorna Street Zielona Gora Poland Dr. Larysa Titarenko Institute of Informatics and Electronics University of Zielona Gora Podgorna Street Zielona Gora Poland ISBN e-isbn DOI / Library of Congress Control Number: c 2009 Springer-Verlag Berlin Heidelberg This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typeset & Coverdesign: Scientific Publishing Services Pvt. Ltd., Chennai, India. Printed in acid-free paper springer.com

4 Acknowledgements Several people helped us with preparation of this manuscript. Our PhD students Mr Jacek Bieganowski and Mr S lawomir Chmielewski worked with us on initial planning of this work, distribution of tasks during the project, and final assembly of this book. We also thank Professor Marian Adamski for his support and special attention to this work. His guidelines in making this book useful for students and practitioners were very helpful in the organization of this book.

5 Contents 1 Hardwired Interpretation of Control Algorithms PrincipleofMicroprogramControl Control Algorithm Interpretation with Finite State Machines Control Algorithm Interpretation with Microprogram ControlUnits Organization of Compositional Microprogram Control Units References Matrix Realization of Control Units PrimitiveMatrixRealizationofFSM Optimization of Mealy FSM Matrix Realization OptimizationofMooreFSMLogicCircuit References Evolution of Programmable Logic SimpleField-ProgrammableLogicDevices Programmable Logic Devices Based on Macrocells ProgrammableDevicesBasedonLUTElements DesignofControlUnitswithFPLD References Optimization for Logic Circuit of Mealy FSM Synthesis of FSM with Replacement of Logical Conditions Synthesis of FSM with Encoding of Collections of Microoperations Synthesis of FSM with Encoding of Rows of Structure Table... 92

6 VIII Contents 4.4 SynthesisofFSMMultilevelLogicCircuits References Optimization for Logic Circuit of Moore FSM OptimizationforTwo-LevelFSMModel FSM Synthesis for CPLD with Embedded Memory Blocks Synthesis of Moore FSM with Logical Condition Replacement References FSM Synthesis with Transformation of GSA Optimization of Logical Condition Replacement Block Optimization for Block for Decoding of Microoperations SynthesisofMultilevelFSMModels References FSM Synthesis with Object Code Transformation PrincipleofObjectCodeTransformation Logic Synthesis for Mealy FSM with Object Code Transformation Logic Synthesis for Moore FSM with Object Code Transformation Multilevel Models of FSM with Object Code Transformation References FSM Synthesis with Elementary Chains Basic Models of FSM with Elementary Chains Optimization of Block of Input Memory Functions OptimizationofBlockofMicrooperations Synthesis for Multilevel Models of FSM with Elementary Chains References Conclusion Index

7 Symbols X = {x 1,...,x L } Y = {y 1,...y N } Y q Y Γ b 0 b E B 1 B 2 E = { b t,b q } a m A K(a m ) A = {a 1,...,a M } T = {T 1,...,T R } A m A Φ = {ϕ 1,...,ϕ R } H Π A = {B 1,...,B I } K(B i ) α g = b g1,...,b gfg M i S(M i ) F = {F 1,...,F H } X(a m ) p g P X(p g ) z r Z K(Y t ) τ set of logical conditions set of microoperations collection of microoperations (microinstruction) graph scheme of algorithm start vertex of GSA end vertex of GSA set of GSA operator vertices set of GSA conditional vertices set of GSA arcs internal state of FSM code of internal state a m A set of FSM internal states set of FSM state variables conjunction of state variables corresponding to the state code K(a m ) set of FSM input memory variables (excitation functions) the number of structure table rows (lines) set of the classes of pseudoequivalent states code of class of pseudoequivalent states B i Π A operational linear chain matrix (AND- or OR-plane) area of matrix M i set of FSM terms set of logical conditions determining transitions from the state a m A additional variable used to replace logical conditions, where P = G, G =max( X(a 1 ),..., X(a M ) ) set of logical conditions written in the column p g additional variable used to encode the microinstructions binary code of collection Y t set of variables used to code classes B i Π a,where τ = R 0 and R 0 = log 2 I

8 X Symbols BM FSM block generating variables for logical condition replacement BP FSM block generating variables written in the rows of (transformed) structure table BY FSM block generating microoperations and implemented with embedded memory blocks BD FSM block generating microoperations and implemented with decoders BF FSM block generating variables corresponding to rows of (transformed) structure table MX g multiplexer from block BM generating function p g P K(y n ) code of microoperation y n Y k from the class k of compatible microoperations R k the number of bits in the code K(y n ) z r Z k additional variables used for encoding of microoperations y n Y k DC k decoder from block BD generating microoperations from the class k of compatible microoperations K(F h ) binary code of row h of FSM structure table R F the number of bits in code K(F g ) H(f) the number of terms for SOP of some function f q the number of terms for PAL-based macrocell n(f,q) the number of macrocells having q terms, necessary to implement the logic circuit for function f NL i the number of FSM models having i levels V (Γ ) graph-scheme of algorithm Γ after verticalization I set of identifiers for FSM with object codes transformation K(I k ) binary code of identifier I k I having R V = log 2 K bits V = {v 1,...,v RV } set of variables used for encoding of identifiers I k I CE = {α 1,...,α GE } set of elementary operational linear chains R E the number of microinstruction address bits, where R E = log 2 M E M E the number of operator vertices in transformed GSA O g output of EOLC α g C E A(O g ) address of EOLC output O g I j input of EOLC α j C E A(I j ) address of EOLC input I j G E the number of EOLC in GSA Γ M g the number of components in EOLC α j C E Q E the maximal number of components in EOLC of GSA Γ

9 Symbols XI R EO R CO K(α g ) K(b t ) the number of variables for encoding of EOLC, where R EO = log 2 G E the number of variables for encoding of EOLC, where R EO = log 2 Q E code of EOLC α g C E code of component b t B 1 of EOLC α g C E

10 Abbreviations ASIC BAT BTC BM BP BTC BY CA CAD CAMI CC CCS CFA CLB CM CMCU CMO CPLD EAB EPROM EEPROM EOLC FPLD FSM FPGA GFT GSA HDL LAB LE LUT application-specific integrated circuit block of address transformer block of code transformer block for logical condition replacement block forming input memory functions of FSM block for code transformation block forming microoperations of FSM control automaton computer-aided design counter of microinstruction address sequential circuit statecodetransformer circuit of address formation (sequencer) configurable logic block control memory compositional microprogram control unit circuit (block) of microoperation generation complex programmable logic devices embedded array block erasable programmable read-only memory electrically erasable programmable read-only memory elementary operational linear chain field-programmable logic devices finite state machine field-programmable gate arrays generalized formula of transition graph- scheme of algorithm hardware description language logic array block logic element look-up table

11 XIV Abbreviations MCU MX OA OLC PAL PLD PLA PLS PROM RAM RAMI RG ROM SBF SOP SPLD ST TMS TSM VGSA VLSI microprogram control unit multiplexer operational automaton operational linear chain programmable array logic programmable logic device programmable logic array programmable logic sequencer programmable read-only memory random-access memory register of microinstruction address register read-only memory system of Boolean functions sums of products simple programmable logic devices structure table microoperation code transformer state code transformer vertical graph- scheme of algorithm very large scale integration circuit

12 Introduction Tremendous achievements in the area of semiconductor electronics turn microelectronics into nanoelectronics. Actually, we observe a real technical boom connected with achievements in nanoelectronics. It results in development of very complex integrated circuits, particularly the field programmable logic devices (FPLD). Up-to-day FPLD chips are so huge, that it is enough only one chip to implement a really complex digital system including a datapath and a control unit. Because of the extreme complexity of modern microchips, it is very important to develop effective design methods oriented on particular properties of logic elements. The development of digital systems with use of FPLD microchips is not possible without use of different hardware description languages (HDL), such as VHDL and Verilog. Different computer-aided design tools (CAD) are wide used to develop digital system hardware. As majority of researches point out, the design process is now very similar to the process of program development. It allows a researcher to pay more attention to some specific problems, where there are no standard formal methods of their solution. But application of all these achievements does not guarantee per se development of some competitive electronic product, especially in the acceptable time-to-market. This problem solution is possible only if a researcher possesses fundamental knowledge of a design process and knows exactly the mode of operation of industrial CAD tools in use. As it is known, any digital system can be represented as a composition of a datepath and a control unit. Logic schemes of data-path have regular structures; it allows use of standard library elements of CAD tools (such as counters, multibit adders, multipliers, multiplexers, decoders and so on) for their design. A control unit coordinates interplay of other system blocks producing a sequence of control signals that causes some operations in a data-path. As a rule, control units have irregular structures, which makes process of their design very sophisticated. In case of complex logic controllers, the problem of system design is reduced practically to the design of control units. Many important features of a digital system, such as performance, power consumption and so on, depend to a large extent on characteristics of its control

13 XVI Introduction unit. Therefore, to design competitive digital systems with FPLD chips, a designer should have fundamental knowledge in the area of logic synthesis and optimization of logic circuits of control units. As our experience shows, design methods used by standard industrial packages are, in case of complex control units design, far from optimal. It means that a designer may be forced to develop his own design methods, next to program them and at last to combine them with standard packages to get a result with desired characteristics. To help such a designer, this book is devoted to solution of the problems of logic synthesis and reduction of hardware amount in control units, when a control unit is represented using the model of finite state machine (FSM). The book contains some original design and optimization methods based on the structural decomposition of FSM model. Such an approach results in multilevel models of FSM, where regularity of the device increases in comparison with known single- and double-level models. Regular parts of these models can be implemented using such library elements as memory blocks, decoders and multiplexers. In the same time, an irregular part of the control units described by means of Boolean functions is reduced. It permits to decrease the total number of logic elements (PAL, GAL, PLA, or LUT macrocells) in comparison with logic circuits based on known models of FSM. This approach is especially fruitful when a control unit is implemented using up-to-day FPLD chips which include not only combinational macrocells, but also the embedded memory blocks. In our book, control algorithms are represented by graph-schemes of algorithms (GSA). This choice is based on obvious fact that this specification provides simple explanation of methods proposed by authors. The methods of synthesis and design presented in the book are not oriented to any particular FPLD chips, but to construction of tables describing the behaviour of FSM blocks. These tables are used to find the systems of Boolean functions, which can be used to implement logic circuits of particular FSM blocks. In order to implement corresponding circuits, this information should be transformed using data formats of particular industrial CAD systems. This step is beyond the scope of our book, in which the following information is presented: Chapter 1 introduces such basic topics as principle of microprogram control and specification of control units by graph-scheme of algorithms. Such conceptions as microoperations (FSM output signals), logical conditions (FSM input signals), FSM states, interstate transitions, and FSM structure table are introduced. Next, some methods of control algorithms interpretation are discussed, such as finite state machines and microprogram control units. The FSM models of Mealy and Moore are introduced; the methods of transition from GSA to Mealy and Moore FSM graphs are shown. All FSM discussed in the book are specified either by GSA or by structure table of FSM. Last part of the chapter is devoted to organization principles of compositional microprogram control units, which can be viewed as a composition of Mealy finite-state machine addressing microinstructions and microprogram control unit with natural microinstruction addressing. These control units are Moore

14 Introduction XVII FSMs using counter to represent their state codes; they can be used for interpretation of linear GSA. Chapter 2 discusses some problems, connected with logic synthesis and optimization of FSM implemented with custom matrix integrated circuits. The primitive matrix implementation of FSM circuit is analyzed first. It is reduced to direct interpretation of FSM structure table and is characterized by considerable redundancy. Next, the methods of logical condition replacement and encoding of collections of microoperations are considered. These methods allow decrease for circuit redundancy due increase of the number of FSM model levels. Next, it is shown that the model of Moore FSM offers an additional possibility for its circuit optimization due to existence of the classes of pseudoequivalent states. Each such class corresponds to one state of the equivalent Mealy FSM. Optimization methods are introduced based on different approaches for state encoding, as well as on transformation of state codes into class codes. The last part of the chapter is devoted to optimization of the block generating microoperations. Chapter 3 discussed contemporary field-programmable logic devices and their evolution, starting from the simplest programmable logic devices such as PROM, PLA, PAL and GAL, and finishing with very sophisticated chips such as CPLD and FPGA. This analysis shows particular features of different logic elements and permits to optimize the FSM logic circuits, in which some particular elements are used. The analysis is accompanied by some examples for systems of Boolean functions implementation using PROM, PLA and PAL chips. The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter. Chapter 4 is devoted to the hardware amount reduction in the logic circuit of Mealy FSM. The methods of logical condition replacement are analyzed, as well as different methods of encoding of collections of microoperations (maximal encoding and encoding of the classes of compatible microoperations). Next, the methods of structure table rows encoding are discussed. Each of these methods produces double-level circuit of Mealy FSM. The main part of the chapter is devoted to joint application of these methods, the main advantage of whose is possibility of standard library cells use for implementation of logic circuits for some blocks of an FSM model. For example, the logical condition replacement allows application of multiplexers, whereas the encoding of collections of microoperations permits to use embedded memory blocks. Standard decoders can be used in case of encoding of the classes of compatible microoperations. It increases FSM logic circuit regularity and leads to simplification of its design process. Chapter 5 is devoted to original synthesis and optimization methods oriented on Moore FSM logic circuit implemented with CPLD. These methods are based on results of joint investigations conducted by the authors and their PhD students Cololo S. (Ukraine) and Chmielewski S. (Poland). These methods deal with both homogenous and heterogeneous CPLD chips. In the first case, only PAL- or PLA- based macrocells are used for logic circuit

15 XVIII Introduction implementation. In the second case, the logic circuit is implemented using both PAL-based macrocells and embedded memory blocks. The hardware amount reduction is based on use of several sources (up to three) to represent the codes of classes of pseudoequivalent states. The methods assume joint minimization of Boolean expressions for input memory functions and microoperations of Moore FSM. The last part of the chapter is devoted to joint application of proposed methods and logical condition replacement. Chapter 6 is devoted to design methods based on transformation of an interpreted graph-scheme of algorithm. The methods of decrease for the number of logical conditions per FSM state are discussed. In extreme case, all FSM transitions depend on single logical condition; it allows use of embedded memory blocks for implementation of FSM input memory functions. In this case all FSM blocks are implemented using standard library cells (not just macrocells of a particular FPLD chip). The second part of the chapter is devoted to hardware optimization for block of microoperations, based on verticalization of an interpreted GSA. It permits to decrease the number of decoders (up to 1) and bit capacity of microinstruction word, but this optimization is connected with increase for the number of cycles required for a control algorithm interpretation. At last, the models based on joint application of these methods are discussed. Chapter 7 is devoted to original optimization methods oriented on decrease of the number of outputs for FSM block generating input memory functions. These methods are based on the object code transformation. The FSM objects are either states or collections of microoperations. Sometimes, some additional identifiers are needed for one-to-one representation of different objects. Such optimization methods are discussed for both Mealy and Moore finite state machines. At last, the multilevel models of FSM with object code transformation, logical condition replacement and encoding of collections of microoperations are discussed. This chapter is written together with employee of Nokia-Siemens Network Alexander Barkalov (Ukraine). Chapter 8 is devoted to original methods oriented on optimization of Moore FSM interpreting graph-schemes of algorithms with long sequences of operator vertices having only one input. These sequences are named elementary operational linear chains (EOLC). These FSM models include the counter keeping, either microinstruction addresses or code of EOLC component. In the beginning the Moore FSM models with code sharing are analysed, where the register keeps EOLC codes. The methods of EOLC encoding and transformation are discussed; these methods permit to decrease the number of macrocells in the block generating input memory functions. The second part of the chapter is devoted to reduction of the number of embedded memory blocks in the FSM block generating microoperations. These methods are based on transformation of microinstruction address represented as concatenation of EOLC code and code of its component into either linear microinstruction address or code of collection of microoperations. The last part of the chapter discusses synthesis methods for multilevel FSM models with EOLC.

16 Introduction XIX We hope that our book will be interesting and useful for students and postgraduates in the area of Computer Science, as well as for designers of modern digital devices. We think that proposed FSM models enlarge the class of models applied for implementation of control units with modern CPLD and FPGA chips.

CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS

CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler