# VALLIAMMAI ENGINEERING COLLEGE

Size: px
Start display at page:

Transcription

1 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation 2017 CHOICE BASED CREDIT SYSTEM Prepared by Dr. A. R. Revathi, Associate Professor/IT Ms. S. Shenbagavadivu, Assistant Professor (S.G)/IT

2 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK SUBJECT : DIGITAL PRINCIPLE AND SYSTEM DESIGN SEM / YEAR : III SEMESTER/ SECOND YEAR UNIT I - BOOLEAN ALGEBRA AND LOGIC GATES Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates - Theorems and Properties of Boolean Algebra - Boolean Functions - Canonical and Standard Forms - Simplification of Boolean Functions using Karnaugh Map - Logic Gates NAND and NOR Implementations. PART-A Q.no Question BTL Competence 1 Find the octal equivalent of hexadecimal numbers of AB.CD (OR) DC.BA BTL5 Evaluating 2 State and prove the Consensus theorem. BTL2 Understanding 3 State the principle of Duality. BTL2 Understanding 4 Implement AND gate using only NOR gates. (OR) Realize XOR gate BTL6 Creating using only NAND gates. 5 Convert (0.6875) 10 to binary (OR) Convert (126) 10 to Octal & Binary BTL3 Applying 6 Prove the following using DeMorgan s Theorem. BTL5 Evaluating [(X + Y)'+(X + Y) '] '=X + Y. 7 Write short notes on weighted binary codes. BTL2 Understanding 8 Illustrate NOR Operation with a truth table BTL2 Understanding 9 What is Excess-3 Code? BTL1 Remembering 10 Simplify Z = (AB +C) (B'D + C'E')+(AB+C)' BTL4 Analyzing 11 Realize G = AB'C +DE+F' BTL4 Analyzing 12 Convert ( ) 2 to base 16 &(231.07) 8 to base 10 BTL3 Applying 13 Convert the binary number to into gray code. (OR) Convert BTL3 Applying (A3B)H into decimal number. 14 Find the complement of the function F= X'YZ' + X'Y'Z. BTL1 Remembering 15 Define Self complementary Code? BTL1 Remembering 16 What are Universal Gates? Why are they named so? BTL1 Remembering 17 What bit must be complemented to change an ASCII letter from capital to BTL1 Remembering

3 lower case and vice versa? 18 Express the following Boolean expression in to minimum number of literals. XYZ+X'Y+XYZ'. BTL5 Evaluating 19 What are the limitations of K-map? BTL1 Remembering 20 Analyse the following Boolean functions using three variable maps. F(X,Y,Z) = (0,2,3,6,7). PART-B BTL4 Analyzing Q.no Question Mark BTL Competence 1 Simplify the following switching function using Quine Mc Cluskey method and realize expression using gates F(A,B,C,D) = (0,5,7,8,9,10,11,14,15) 2 Simplify the following switching function using karnaugh map method and realize expression using gates F(A,B,C,D) = (0,3,5,7,8,9,10,12,15) 3 Simplify the function F(w,x,y,z)= m(2,3,12,13,14,15) using Tabulation method. Implement the simplified function using gates. 4(a) Simplify the Boolean function in Sum of Products(SOP) and Product of Sum(POS) F(w,x,y,z)= m(0,1,2,5,8,9,10). 4(b) Design the Boolean function in Karnaugh map and simplify it F(w,x,y,z)= m(0,1,2,4,5,6,8,9,12,13,14). 13 BTL3 Applying 13 BTL2 Understanding 13 BTL4 Analyzing 08 BTL4 Analyzing 05 BTL6 Creating 5 Simplify the following Boolean expression in (a) Sum of Product (b) BTL4 Analyzing Product of Sum using Karnaugh map AC' + B'D + A'CD + ABCD. 6(a) Express the following function in sum of min-terms and product of 06 BTL2 Understanding max-terms : F(x,y,z)=x+yz. 6(b) Convert the following logic system in to NAND gates only. 07 BTL3 Applying 7(a) Add, subtract and multiply the following numbers in binary 04 BTL1 Remembering (110010) 2 and (11101) 2. 7(b) State and prove De Morgan s theorems for 2-variables 04 BTL1 Remembering 7(c) Find dual and complement of the following Boolean expression xyz 05 BTL1 Remembering +x yz+z(xy+w) 8 Minimize the following function using Karnaugh map F(A,B,C,D) = 13 BTL4 Analyzing m(0,1,2,3,4,5,6,11,12,13) 9 Minimize the expression using K-map and Quine Mccluskey method 13 BTL2 Understanding Y= A BC D + A BC D+ABC D +ABC D +AB C D+A B CD 10(a) Implement the following Boolean function with NAND-NAND logic 07 BTL6 Creating F(A,B,C)= M(0,1,3,5) 10(b) Define prime implicate and essential prime implicate. 04 BTL1 Remembering

4 10(c) Convert (78.5) 10 into binary 02 BTL3 Applying 11 Explain the rules for Binary Addition and Subtraction using 1's & 13 BTL5 Evaluating 2 s complement. Give examples. 12 Explain about common postulates used to formulate various algebraic 13 BTL1 Remembering structures. 13(a) Explain the procedure for obtaining NAND- NAND circuit for any 06 BTL5 Evaluating AND-OR network with a suitable example. 13(b) Implement Y= (A'B+AB') (C+D') using NOR gates. 07 BTL3 Applying 14(a) 14(b) Explain the procedure for obtaining NOR- NOR circuit for any AND-OR network with a suitable example. Simplify the given Boolean function in POS form using k-map and draw the logic diagram using NOR gates. F(A,B,C,D) =ΠM(0,1,4,7,8,10,12,15)+d(2,6,11,14) PART-C 06 BTL5 Evaluating 07 BTL4 Analyzing Q.no Question Mark BTL Competence 1 Minimize the expression using Quine Mc Cluskey method F= m(0,1,9,15,24,29,30) + d(8,11,31) (OR) Reduce the expression using tabulation method F(X 1,X 2,X 3,X 4,X 5 ) = m(0,2,4,5,6,7,8,10,14,17,18,21,29,31) + d(11,20,22) 2 Express the following function in a simplified manner using K map technique (i) G=πM(0,1,3,7,9,11). (ii) f(w,x,y,z)= m(0,7,8,9,10,12) + d(2,5,13). 3 Simplify the following function using five variable map: F(A,B,C,D,E)=A B CE +B C D E +A B D +B C D +A CD+A BD 4 Simplify the following expression Y= m 1 +m 3 +m 4 +m 7 +m 8 +m 9 +m 10 +m 11 +m 12 +m 14 using Quine Mc Cluskey method & K map technique UNIT II - COMBINATIONAL LOGIC 15 BTL5 Evaluating 15 BTL6 Creating 15 BTL5 Evaluating 15 BTL5 Evaluating Combinational Circuits Analysis and Design Procedures - Binary Adder-Subtractor - Decimal Adder - Binary Multiplier - Magnitude Comparator - Decoders Encoders Multiplexers - Introduction to HDL HDL Models of Combinational circuits. PART-A Q.no Question BTL Competence 1 Implement (solve) the function G= m (0, 3) using a 2x4 decoder. BTL6 Creating 2 Draw (design) the circuit diagram for 2 to 1 line multiplexer. BTL3 Applying 3 Implement(solve) the following Boolean function using 8:1 multiplexer F(A,B,C)= M(1,3,5,6). BTL5 Evaluating 4 What is priority encoder? BTL1 Remembering 5 Implement (solve) a full adder with 4x1 multiplexer. BTL6 Creating 6 Write the Data flow description of a 4 bit comparator. BTL2 Understanding 7 What is half adder?. Draw the truth table of half adder BTL1 Remembering 8 Write short notes on propagation delay BTL2 Understanding

5 9 Define combinational circuits BTL1 Remembering 10 Differentiate between Multiplexer and Demultiplexer. BTL4 Analyzing 11 State the differentiate between decoder and demultiplexer. BTL4 Analyzing 12 Obtain the truth table for BCD to Excess-3 code converter BTL1 Remembering 13 Draw the truth table and circuit diagram of 4 to 2 encoder. BTL3 Applying 14 Write any two advantages of HDL. BTL2 Understanding 15 Write the HDL data flow description of 4 bit adder BTL2 Understanding 16 Differentiate between encoder and decoder. BTL4 Analyzing 17 List out the application of multiplexer. BTL1 Remembering 18 Determine the HDL description for the following circuit BTL5 Evaluating 19 Draw the full adder circuit as a collection of two half adders. BTL3 Applying 20 List the truth table of full subtractor. BTL1 Remembering PART-B Q.no Question Mark BTL Competence 1 Describe the process involved in converting 8421 code to Excess 3 13 BTL2 Understanding code with neat sketch. (OR) Design a code converter that converts a 8421 to BCD Code 2(a) Examine the following Boolean function using 8 to 1 Multiplexer. 06 BTL4 Analyzing F(A,B,C,D)=A BD + ACD + B'CD + A'C'D. 2(b) Discover the above function using 16 to 1 Multiplexer. 07 BTL4 Analyzing 3 Describe the procedure of converting 8421 to Gray code converter 13 BTL2 Understanding also realize the converter using only NAND gates. 4 Design 2-bit magnitude comparator and write a verilog HDL code. 13 BTL6 Creating 5(a) Examine the following Boolean functions with a multiplexer. 06 BTL4 Analyzing F(w,x,y,z) = (2,3,5,6,11,14,15) 5(b) Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 to 4 07 BTL3 Applying line decoder. 6(a) Explain the Analysis procedure. Analyze the following logic diagram. 06 BTL5 Evaluating

6 6(b) With neat diagram explain the 4 bit adder with Carry look ahead. 07 BTL5 Evaluating 7 Design Full subtractor and derive expression for difference and 13 BTL6 Creating borrow. Realize using gates. 8 Design the full adder with inputs x,y,z and two outputs S and C. The 13 BTL6 Creating circuits perform x+y+z is the input carry, C is the output carry and S is the Sum & realize it s using only NOR gates 9 Design a logic circuit that accepts a 4-bit gray code and converts it to 13 BTL6 Creating 4-bit binary code 10(a) Design a 2 bit binary multiplier to multiply two binary numbers and 06 BTL1 Remembering produce a 4-bit result. 10(b) Construct a 4-bit odd parity generator circuit using gates 07 BTL3 Applying 11 Recall the design procedure for a combinational circuit to perform 13 BTL1 Remembering BCD addition. 12 Define priority encoder and design 8 to 3 priority encoder 13 BTL1 Remembering 13(a) Explain the design procedure for combinational circuits with suitable 07 BTL5 Evaluating examples 13(b) Construct 16X1 multiplexer with two 8X1 and 2X1 multiplexer. Use 06 BTL3 Applying Block diagrams 14(a) Write the HDL gate level description of the priority encoder circuit. 07 BTL2 Understanding 14(b) Find the design procedure for a 4 bit parallel binary adder / subtractor. 06 BTL1 Remembering PART-C Q.no Question Mark BTL Competence 1 How to design a 4 bit magnitude comparator with 3 outputs 15 BTL2 Understanding A>B,A=B,A<B 2a Implement the following function using 8 to 1 multiplexer f(a,b,c,d)= 08 BTL5 Evaluating m(0,1,3,5,9,12,14,15) 2b Implement the following function using multiplexer f(a,b,c,d)= 07 BTL5 Evaluating m(0,1,3,4,8,9,15) 3 Design a binary to gray code converter circuit & a BCD to 7- Segment 15 BTL6 Creating code converter circuit 4 Find the design procedure for binary multiplier 15 BTL6 Creating

7 UNIT III - SYNCHRONOUS SEQUENTIAL LOGIC Sequential Circuits - Storage Elements: Latches, Flip-Flops - Analysis of Clocked Sequential Circuits - State Reduction and Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential Circuits. PART-A Q.no Question BTL Competence 1 Summarize the characteristic table and equation of JK flip flop. (OR) State the BTL2 Understanding excitation table of JK-flip flop 2 Write any two application of shift register. BTL2 Understanding 3 With reference to a JK flip flop what is racing? BTL1 Remembering 4 Identify how many JK- flip-flops are required to design a MOD 35 counter? BTL3 Applying 5 What are the significances of state assignment? BTL1 Remembering 6 How many states are there in a 3-bit ring counter? what are they? BTL5 Evaluating 7 Give block diagram of Master -Slave D Flip flop BTL1 Remembering 8 Draw the diagram of T- Flip flop and discuss its working. BTL3 Applying 9 Classify the shift registers. (OR) What is shift register? BTL4 Analyzing 10 Analyze how many flip-flops are required to design a synchronous MOD 60 BTL4 Analyzing counter? 11 Develop the HDL code to realize a D - flip flop BTL6 Creating 12 State the rules for state assignment BTL1 Remembering 13 Realize a JK flip flop using D flip flop. BTL3 Applying 14 Write down the steps involved in the design of synchronous sequential BTL2 Understanding circuits. 15 Recall the Characteristics equation of JK-flip flop (OR) Characteristics BTL1 Remembering equation of JK-flip flop SR flip flop 16 Explain the difference between the performance of asynchronous and BTL5 Evaluating synchronous counter 17 Differentiate between latch and flip flop. BTL4 Analyzing 18 Define Ripple counter ( OR) What is ring counter? BTL1 Remembering 19 Select and list any two mechanisms to achieve edge triggering of flip flop BTL2 Understanding 20 Design a 4 bit binary synchronous counter with D flip flops. BTL6 Creating PART-B Q.no Question Mark BTL Competence 1 Implement T flip-flop using D flip-flop and JK using D flip flop. 13 BTL5 Evaluating 2 Design a synchronous counter with the following sequence: 0,1,3,7,6,4 and repeats. Use JK Flip flop. 13 BTL6 Creating

8 3 Design a MOD-10 Synchronous counter using JK flip-flop. Write 13 BTL6 Creating execution table and state table. (OR) Design MOD 6 counter circuit. 4(a) How a race condition can be avoided in a flip-flop. 06 BTL1 Remembering 4(b) Realize the sequential circuit for the state diagram shown below. 07 BTL4 Analyzing a/0 X=1 X=0,X=1 X=0 c/1 b/0 X=0,X=1 5a Analyse the difference between a state table, characteristic table and 06 BTL4 Analyzing an excitation table. 5b Write the HDL code for up-down counter using behavioural model. 07 BTL3 Applying 6 Consider the design of a 4 bit BCD counter that counts in the following 13 BTL3 Applying way: 0000, 0010, 0011,., 1001, and back to (i) Draw the state diagram.(04) (ii) List the next state table. (04) (iii) Draw the logic diagram of the circuit.(05) 7 Design a sequence detector to detect the input sequence 13 BTL6 Creating 101(overlapping ).Use JK Flip flops. 8 Write the design procedure for a three bit synchronous counter with T 13 BTL1 Remembering flip flop and draw the diagram. 9 Design the sequential circuit specified by the following state diagram using T flip flops 13 BTL6 Creating 10(a) Write the design procedure for a 3-bit synchronous up counter using JK 06 BTL1 Remembering flip flop and draw the diagram. 10(b) Write the design procedure for 3 bit parallel- in serial-out shift register 07 BTL1 Remembering

9 and write the HDL code to realize it. 11 Illustrate a serial adder using a full adder and a flip flop 13 BTL2 Understanding 12 Explain the operation of master slave flip flop and show how the race 13 BTL5 Evaluating around condition is eliminated in it. 13 Write the HDL description of T flip-flop, JK flip-flop,sr flip flop and 13 BTL2 Understanding D flip-flops. 14(a) Draw the block diagram of Johnson counter and explain. 06 BTL5 Evaluating 14(b) Explain the different types of shift registers with neat diagram. 07 BTL2 Understanding PART-C Q.no Question Mark BTL Competence 1 Design a synchronous counter which counts in the sequence 000,001,010,011,100,101,110,111,000 using D flip-flop. 2 A sequential circuit with two D flip-flops A and B, one input x, and one output z is specified by the following next state and output equations: A(t+1) = A'+B, B(t+1)=B'X, Z =A+B' (i)draw the logic diagram of the circuit. (05) (ii)derive the state table. (05) (iii)draw the state diagram of the circuit.(05) 3 Design sequence detector that detects a sequence of three or more consecutive 1 s in a string of bits coming through an input line and produces an output whenever this sequence is detected. 4 Analyze and design a sequential circuit with two T Flip flop A and B, one input x and one output z is specified by the following next state and output equation is A(t+1)= BX +B X B(t+1)=AB+BX+AX Z=AX +A B X (i)draw the logic diagram of the circuit. (ii) List the state table for the sequential circuit (iii) Draw the Corresponding state diagram. 15 BTL6 Creating 15 BTL5 Evaluating 15 BTL6 Creating 15 BTL6 Creating UNIT IV- ASYNCHRONOUS SEQUENTIAL LOGIC Analysis and Design of Asynchronous Sequential Circuits Reduction of State and Flow Tables Race-free State Assignment Hazards. PART-A Q.no Question BTL Competence 1 Define race around conditions. BTL1 Remembering 2 Define hazards. What are the types of hazards? BTL1 Remembering 3 Define Merger graph. BTL1 Remembering

10 4 How the Moore circuit differ from Mealy circuit? BTL1 Remembering 5 Define flow table in asynchronous sequential circuits BTL1 Remembering 6 Compare asynchronous and synchronous sequential circuit. BTL3 Applying 7 What are race? BTL2 Understanding 8 Compare the critical race and non critical race BTL3 Applying 9 What is lockout? How it is avoided? BTL2 Understanding 10 Estimate the wave forms showing static 1 hazards (OR) Write short notes BTL6 Creating on Static -1 hazards. 11 List the characteristics of fundamental mode circuit. BTL2 Understanding 12 Define primitive flow table BTL2 Understanding 13 Show the diagram for debounce circuit. BTL3 Applying 14 Distinguish between fundamental mode circuit and pulse mode circuit. BTL4 Analyzing 15 Point out the steps involved in the designing an asynchronous sequential BTL1 Remembering circuits. 16 How can we change the hazards into hazards free circuit? BTL5 Evaluating 17 Differentiate transition table and flow table. BTL4 Analyzing 18 Compare static and dynamic hazards. BTL4 Analyzing 19 Is it essential to have race free assignment? Justify. BTL5 Evaluating 20 Differentiate conventional flow table and primitive flow table. BTL4 Analyzing PART-B Q.no Question Mark BTL Competence 1 Explain the steps for the design of asynchronous sequential circuits 13 BTL5 Evaluating with an example. 2 Construct the switching function F= m(1,3,5,7,8,9,14,15) by a static 13 BTL3 Applying hazard free two level AND-OR gate network. 3 What are hazards and its types? How can you design a hazard free 13 BTL1 Remembering circuits, explain with example. 4 Analyze the following clocked sequential circuit and obtain the state equation and state diagram. 13 BTL4 Analyzing

11 5(a) Describe the race free state assignment procedure. 06 BTL1 Remembering 5(b) Reduce the number of state in the following state diagram. Tabulate the reduced state and draw the reduced diagram. 07 BTL3 Applying Present state Next state Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f Explain the hazards in combinational circuit and sequential circuit 13 BTL2 Understanding and also demonstrate a hazards and its removal with example. 7 Discuss about Pulse mode & Fundamental mode asynchronous 13 BTL6 Creating sequential circuits 8 Discuss in detail the procedure for reducing the flow table with an 13 BTL6 Creating example. 9(a) Explain the two types of asynchronous sequential circuit with 06 BTL2 Understanding suitable example. 9(b) What is flow table? Explain with suitable example. 07 BTL1 Remembering 10(a) What is the objective of state assignment in asynchronous circuit? 06 BTL1 Remembering Explain how race to be avoided with an example. 10(b) Summarize about static, dynamic and essential hazards in 07 BTL2 Understanding asynchronous sequential circuits 11 Consider the asynchronous sequential circuits which is driven by the 13 BTL4 Analyzing

12 pulses, as in the following figure. Analyse the circuit 12 Analyze the fundamental mode asynchronous sequential circuit given 13 BTL4 Analyzing 13 BTL4 Analyzing 13 BTL6 Creating in the following figure. 13 Explain with a neat example for minimization of primitive flow table. 14 Design a circuit with inputs A and B to give an output Z=1 when AB=11 but only if A becomes 1before B, by drawing total state diagram, primitive flow table and output map in which transient state is included. PART-C Q.no 1 2 Question Mark An asynchronous sequential circuit is described by the following 15 excitation and output function. Y=X1X2+(X2+X3)Y and Z=Y i. Draw the logic diagram of the circuit. (06) ii. Derive the transition table and output map.(06) iii. Describer the behaviour of the circuit.(03) Design an asynchronous sequential circuit with inputs X1 and X2 and 15 one output Z. Initially and at any time if both the inputs are 0, output is BTL Competence BTL5 Evaluating BTL6 Creating

13 equal to 0.When X 1 or X 2 becomes 1, Z becomes 1. When Second input also becomes 1, Z=0; The output stays at 0 until circuit goes back to initial state. 3 An asynchronous sequential circuit is described by the following excitation and output function. X = (Y 1 Z 1 'W 2 )X + (Y 1 'Z 1 W 2 ') & S = X' (i) Draw the logic diagram of the circuit. (06) (ii) Derive the transition table and output map.(06) (iii) Describe the behavior of the circuit. (03) 4 Design an asynchronous sequential circuit with two input x and y and with one output z whenever y is 1, input x is transferred to z. When y is 0, the output does not change for any change in x. Use SR latch for implementation of the circuit. 15 BTL5 Evaluating 15 BTL6 Creating UNIT V - MEMORY AND PROGRAMMABLE LOGIC RAM Memory Decoding Error Detection and Correction - ROM - Programmable Logic Array Programmable Array Logic Sequential Programmable Devices. PART-A Q.no Question BTL Competence 1 What is memory decoding? BTL1 Remembering 2 Define ASIC. BTL1 Remembering 3 Justify whether PAL is same as PLA. BTL5 Evaluating 4 What is volatile memory? Give example. BTL1 Remembering 5 Differentiate between EEPROM and PROM. BTL4 Analyzing 6 How to detect double error and correct single error? BTL1 Remembering 7 What is memory address register? BTL1 Remembering 8 Write short notes on PLA. BTL2 Understanding 9 A seven bit hamming code is received as What is the correct code? BTL1 Remembering 10 List the types of memories. BTL2 Understanding 11 Define combinational PLD. BTL1 Remembering 12 Compare DRAM and SRAM. BTL5 Evaluating 13 Develop the maximum range of a memory that can be accessed using 10 BTL3 Applying address lines. 14 Identify the comparison between EPROM and PLA BTL3 Applying 15 Differentiate error detection and correction technique. BTL4 Analyzing 16 Give the details about write and read operations in RAM. BTL2 Understanding 17 Design the logic diagram of a memory cell. BTL6 Creating 18 Write down the different types of PLDs. BTL2 Understanding 19 Classify the types of RAM. BTL2 Understanding 20 Differentiate between PLA and ROM. BTL4 Analyzing

14 PART-B Q.no Question Mark BT L Competence 1 Implement the following function using PLA A(X,Y,Z)= m(1,2,4,6), 13 BTL5 Evaluating B(X,Y,Z)= m(0,1,6,7), C(X,Y,Z)= m(2,6) 2 Explain in detail about the Programmable Logic Array & Programmable 13 BTL1 Remembering array logic. 3 Design a BCD to Excess 3 code converter and implement using suitable 13 BTL6 Creating PLA. 4 Recall the concept of working and application of semiconductor 13 BTL1 Remembering memories. 5(a) Write short notes on Address Multiplexing. 06 BTL2 Understanding 5(b) Briefly discuss the sequential programmable devices. 07 BTL2 Understanding 6(a) Implement the following Two Boolean function with a PLA 06 BTL5 Evaluating F1=AB'+AC'+A'BC' F2=(AC+BC+AB)' 6(b) Give the Internal block diagram of 4 x 4 RAM. 07 BTL2 Understanding 7 Implement the following using PAL F1(A,B,C)= (1,2,4,6); F2(A,B,C) 13 BTL5 Evaluating = (0,1,6,7) ; F3(A,B,C)= (1,2,3,5,7) 8 Design a combinational circuit using ROM that accepts a three bit 13 BTL6 Creating binary number and outputs a binary number equal to the square of the input number. 9 Draw a neat sketch showing implementation of Z1= ab d e + 13 BTL3 Applying a b c e+bc+de, Z2= a c e, Z3=bc+de+c d e+db and Z4=a c e +ce using 5*8*4 PLA. 10(a) How to implement the two following Boolean functions using 8X2 06 BTL1 Remembering PROM 10(b) Construct the following two Boolean functions using PLA with 3 inputs, 07 BTL3 Applying 4 Product terms, and 2 outputs. F1= m(3,5,6,7) and F2= m(1,2,3,4) 11 Implement the following using PAL 13 BTL5 Evaluating W(A,B,C,D) = (0,2,6,7,8,9,12,13); X(A,B,C,D) = (0,2,6,7,8,9,12,13,14) ; Y(A,B,C,D) = (2,3,8,9,10,12,13); Z(A,B,C,D)= (1,3,4,6,9,12,14); 12 List the features of PROM, PAL and PLA & Discuss the sequential 13 BTL1 Remembering programmable devices 13(a) Compare PROM, PLA, PAL 07 BTL4 Analyzing 13(b) Compare SRAM and DRAM. 06 BTL4 Analyzing 14 Discuss the various types of RAM and ROM with architecture. 13 BTL2 Understanding PART-C 1 Design the following Boolean function using 8X2 PROM. 15 BTL6 Creating F1= m(3,5,6,7) F2= m(1,2,3,4) 2 Design a 16 bit RAM array (4X4 RAM) and explain the operation. 15 BTL6 Creating 3 Explain about error detection and correction using Hamming codes. 4 The following message have been coded in the even parity hamming code and transmitted through a noisy channel. Decode the message assuming that at most a single error occurred in each codeword. i) (04) ii) (04) iii) (04) iv) (03) 15 BTL5 Evaluating 15 BTL5 Evaluating

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

### DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

### VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

### BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

### SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

### COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

### PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

### (ii) Simplify and implement the following SOP function using NOR gates:

DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

### R07

www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions

### R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

### B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering

### CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all

### KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL

### UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.

### Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### 10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

### R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions

### Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

### HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

### SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### Scheme G. Sample Test Paper-I

Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

### CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

### APPENDIX A SHORT QUESTIONS AND ANSWERS

APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part - A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated

INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input

### KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

### R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean

### Switching Theory & Logic Design/Digital Logic Design Question Bank

Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was

### Hours / 100 Marks Seat No.

17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)

### Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

### DE Solution Set QP Code : 00904

DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and

### CS8803: Advanced Digital Design for Embedded Hardware

CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

### 1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

### DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development

### DIGITAL ELECTRONICS. Vayu Education of India

DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education

### Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9

### DIGITAL ELECTRONICS. P41l 3 HOURS

UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

### Hours / 100 Marks Seat No.

17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,

### UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

### Model EXAM Question Bank

VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam -1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable

### MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the

### CS/IT DIGITAL LOGIC DESIGN

CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) Flip-Flop Answer

### 2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]

Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two n-digit unsigned numbers.

### GATE CSE. GATE CSE Book. November 2016 GATE CSE

GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing

### Presentation 4: Programmable Combinational Devices

Presentation 4: Programmable Combinational Devices Asst. Prof Dr. Ahmet ÖZKURT DEUEEE Based on the Presentation by Prof. Kim, Young Ho Dept. of Information Computer Engineering E-mail : yhkim@hyowon.cs.pusan.ac.kr

### MULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR

STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEW-E-F 1/13 18 FEBRUARY

### SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics

### CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS

Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler

### BHARATHIDASAN ENGINEERING COLLEGE

BHARATHIDASAN ENGINEERING COLLEGE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (FOR COMMON TO 2 SEM CSE & IT) Lecturer notes Prepared by L.Gopinath M.tech Assistant professor UNIT 1 BOOLEAN ALGEBRS AND

### Combinational Circuits

Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

### Logic design Ibn Al Haitham collage /Computer science Eng. Sameer

DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

### NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary

### Digital Logic Design Exercises. Assignment 1

Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

### TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I

TEACHING & EXAMINATION SCHEME For the Examination -2015 COMPUTER SCIENCE THEORY B.Sc. Part-I CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3

### Question Total Possible Test Score Total 100

Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

### St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of

### 1. Draw general diagram of computer showing different logical components (3)

Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the

### Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

Course Batch Semester Subject Code Subject Name B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Part-A 1 Define De-Morgan's theorem. 2 Convert the following hexadecimal number to decimal

### MLR Institute of Technology

MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN

### 3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog

### INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 00 0 ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II - B.

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.

14CS IT302 November,2016 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Discrete Mathematical Structures (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a (Pv~P) is

### SWITCHING THEORY AND LOGIC CIRCUITS

SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra

### Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

### Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR

### PROGRAMMABLE LOGIC DEVICES

PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available

### Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York

Digital Design and Verilo fit HDL Fundamentals Joseph Cavanagh Santa Clara University California, USA CRC Press Taylor & Francis Group Boca Raton London New York CRC Press is an imprint of the Taylor &

### UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

### LOGIC CIRCUITS. Kirti P_Didital Design 1

LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists

### Chapter 2 Combinational Logic Circuits

Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

### MEMORY AND PROGRAMMABLE LOGIC

MEMORY AND PROGRAMMABLE LOGIC Memory is a device where we can store and retrieve information It can execute a read and a write Programmable Logic is a device where we can store and retrieve information

### IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

### QUESTION BANK (DESCRIPTIVE) UNIT I Binary Systems, Boolean Alegebra & Logic Gates. 1. What are the characteristics of Digital Systems.

SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : Digital Logic Design(18CS502 ) Year & Sem: I-B.Tech

### NODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY

No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer

### Computer Logical Organization Tutorial

Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer

### CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES This chapter in the book includes: Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders

### Digital System Design with SystemVerilog

Digital System Design with SystemVerilog Mark Zwolinski AAddison-Wesley Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown Sydney Tokyo

### Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

### SECTION-A

M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth ------------------------------------------------------------------------------------- SECTION-A I) An electronics circuit/ device

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

### D I G I T A L C I R C U I T S E E

D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,

### ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics - I SECTION-A Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)

### This tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.

About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional