VLSI for Multi-Technology Systems (Spring 2003)

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1 VLSI for Multi-Technology Systems (Spring 2003) Digital Project Due in Lecture Tuesday May 6th Fei Lu Ping Chen Electrical Engineering University of Cincinnati

2 Abstract In this project, we realized the circuit that takes two 8 bit binary numbers input and produces two output numbers in BCD formant. One is the difference between the two number and another one is the smaller one of the two numbers. The worst case delay is 23 ns and system frequency is 43 MHz. The area is 1388*850= The area delay product A (t d ) 2 is In the comparison part, we realized the subtraction by adding the complementary number. We used XOR and AND gates instead of the full adder to transfer the negative difference to the positive one. In the binary to BCD part, we used the method of divided-by-10 to get each BCD number. We made two improvements here. (1) change the division by 10 to the division by 5; (2)use NAND or NOR gates to realize the division and got the smaller size and the faster speed. 2

3 1. Introduction 1.1 Problem Statement In this project, we need to design a circuit that takes two 8 bit binary numbers as input and produces as an output two numbers in binary coded decimal (BCD) format. The first output is the smaller of the two input numbers and the second output is the difference between the two numbers. We can divide the project into two main parts. The first part will take two 8-bit binary numbers and output the difference and the smaller number in binary format. The second part will convert each 8-bit binary number into a 3-digit BCD number. The block diagram is shown in figure 1. 8-bit Binary Input A 8-bit Binary Input A Compare A and B, output the smaller number and the difference 8-bit Binary Output of the smaller number 8-bit Binary Output of the difference 8-bit binary-to- BCD conversion 8-bit binary-to- BCD conversion Output 3-digit BCD number Output 3-digit BCD number Figure 1 Block diagram of circuit comparing two 8-bit binary numbers and producing output of the difference and small number in BCD format Area delay product A (t d ) 2 will be used to characterize the performance of the design where A is the area of the circuit and t d is the worst case delay between input of a binary number and output of binary coded decimal values. 1.2 Background Information The first part of comparing and producing the difference can be found in every textbook 3

4 and easily implemented using mainly full-adder and multiplex cells. We'll discuss the optimization to the circuit in the next section. The second part of binary-to-bcd conversion is relatively difficult. There are two ways to realize the conversion. The first algorithm is based on calculation like this, for a n-bit input: BCD_output = a x2 +a x a x2 +a x2 n-1 n n-1 n =(...((a x2+a )x2+a )x2+...)+a )x2+a n-1 n-2 n The multiply-by-2 operation can be realized by left shift register and the add operation must be realized by a BCD adder. That is, we need to set carry to 1 when the sum is bigger than 10 or 100, etc. Using BCD adder, the final result after all sum and shift will be a valid BCD output. The other algorithm is also very straightforward, like this: integer_in_binary : 1010B = (quotient_1, remainder_1) quotient_1 : 1010B = (quotient_2, remainder_2) quotient_2 : 1010B = (quotient_3, remainder_3)... quotient_n-1 : 1010B = (quotient_n, remainder_n) The principle is to perform the calculation step by step. At each step the remainder and the quotient in a division by ten are computed. The remainder is given directly in binary form which is smaller than 10. The steps are done by combinational circuit. Each step performs calculations on the quotient generated by the previous step. At each step the quotient is an input for the next step and the remainder is a final result. After processing the binary number can be presented as n+1 positional decimal digit, represented by remainders: number_in_bcd = remainder_n, remainder_3, remainder_2, remainder1 Both algorithms are simple in theory. But further structure decomposition or function decomposition is needed to get it work efficiently in binary world. Generally, from other's previous work, the size and execution time is more efficient using the division method for 8-bit binary input. We'll go into details in the section to simplify the algorithm and realize an efficient binary-to-bcd converter. 4

5 2. Methods and Procedures In this section, we'll concentrate on the circuit implementation and theoretical analysis. Necessary diagrams and schematics are given to help illustrate the operation of the project. From figure 1 in last section, we can see that the project can be divided into two parts: comparer part and binary-to-bcd part. We'll discuss them separately. 2.1 Implementation and theoretical analysis of comparer part Implementation The comparer part will take two 8-bit binary numbers as input and generate two outputs. One output is the smaller of the two input numbers and the other is the difference between the numbers. 8-bit Binary Input A 8-bit Binary Input B Carry bit, 1 if A>B, 0 if A<B Get 1's Complement of B Add A to 1's Complement of B with input carry = 1, the result is SUM Get 2's Complement of SUM 2x8MUX Output B if Carry=1, A if Carry=0 2x8MUX Output SUM if Carry=1, output 2's Complement of SUM if Carry=0 Figure 2 Block diagram of comparer Figure 2 is the block diagram of the comparer. First we add 8-bit binary input A to the 1's 5

6 complement of input B with carry set. The sum will actually be the difference of A and B if A is greater than or equal B. If A is smaller than B, the difference will equal to the 2's complement of the output of the adder. From above overall analysis, we need to realize: (1) Unit to calculate 1's complement, which can be realized using 8 inverters; (2) An 8-bit full adder unit, which can be realized using 8 1-bit full adder in standard cell library and connect their carry out to carry in from LSB to MSB, the carry in of the LSB full adder is set to 1 because we use addition of 1's complement, the carry out of the MSB full adder will be used to judge if A is greater than B; (3) 2's complement unit, which can be realized by simple combinational logic circuits; (4) Also we need two 2x8 multiplexer to select the desired output, which can be easily implemented with 21mux standard cell. Figure 3 Schematic of the one bit realization of the comparer unit Figure 3 is the circuit schematic of the one bit realization of the comparer unit. The left subtract block made up of one 1-bit full adder and one inverter will realize the subtract operation with carry in from higher bit and carry out to lower bit. The center block of figure 3 is 2's complement cell. Generally, for a 8-bit binary input, we can write the logic expression for calculate 2's complement b0 a0 1 b1 a1 a0... b7 a7 ( a6* a5* a4* a3* a2* a1* a0) With some small techniques, The 2's complement logic expression can be write in a 6

7 recursive form b0 a0 1; cout0 1 b1 a1 ( a0* cout0); cout1 a0* cout0 b2 a2 ( a1* cout1); cout2 a1* cout1... b6 a6 ( a5* cout5); cout6 a6* cout5 b7 a7 ( a6* cout1); cout7 a1* cout1 With above expression, now we can realize the 2's complement block with one inverter, one NAND gate and one XOR gate for each bit as shown in figure 3. The right block of figure 3 is comprised of two 2 1-bit input multiplexer, the selector will be connected together to the carry out of the MSB full adder. This block ensures right output of the difference and smaller number whether A is greater than B or not. The n-bit comparer unit can be implemented by connecting n above cells together. In figure 4, we give one example of four bit comparer unit. 8-bit comparer can be realized similarly. Figure 4 Schematic of 4-bit comparer unit 7

8 2.1.2 Theoretical analysis With above comparer design, we can layout n-bit comparer easily with high density. Moreover, it also benefits in the delay consideration. Generally, the full adder cell created the longest delay. As shown in figure 4, before pass the multiplexer, each bit of the 2's complement unit is calculated directly after the sum output of full adder for that bit which greatly saves computation time. So the total time delay can be estimated as t( total delay) t ( inverter) t(8- bit full adder) t( inverter) t( XOR gate) t(21 mux) Since the delays in inverter, XOR gate and 21mux are relatively small. So the total delay of our comparer is about equal to the delay in an 8-bit full adder. 2.2 Implementation and theoretical analysis of binary-to-bcd converter Implementation From the discussion in last section, we think use division is more efficient for 8-bit binary input. Also as we can see later, with some simplification, the circuit can be realized with combination logic. Compared to sequential logic, this implementation saves space for registers and saves time to add control circuits and debug. 8-bit Binary Input Divide by 10 Store the remainder in [units] Divide the result by 10 Store the remainder in [tens] Store the result in [hundreds] 8

9 Figure 5. Block diagram of 8-bit binary to 3-digit BCD Conversion The basic block diagram for division implementation of binary-to-bcd is shown in figure 5. We need to realize a divider to continue. Usually, division is realized by restoring or non-restoring trial subtraction. However, using very simple transformations it is needed to compute the quotient and remainder only by 5 instead of 10: (A%10) = ((A/2)%5)*2 + (A%2) (A/10) = ((A/2)/5) The divide-by-2 or multiple-by-2 can be realized by shift left or right one bit. So we can implement the circuit using combinational blocks performing division by 5. Figure 6 give the implementation to help illustrate this. Figure 6 Schematic of 8-bit binary-to-bcd converter In figure 6, each div5 cell works on 4 bits input number. These 4 bits code a number smaller than 10. The quotient by 5 is 1 or 0. The remainder is smaller than 5. This remainder is extended by a least significant bit taken from the input vector. In the input the first three bits are extended by a zero most significant bit. This maintains the condition that the input is smaller than 10. Each cell is a simple combinational circuit with 4 inputs and 4 outputs. The truth table can be easily represented as in table 1 where q is the quotient bit and r2, r1, r0 the remainder bits. From the truth table we can derive the logic expressions to implement in circuit (table 2). For these complex logic functions, we need to adjust the logic functions to get faster speed and accommodate the standard cell library. In general, the delay of And-Or-Invert (AOI) logic implementation for these relatively 9

10 complex logic functions can be significantly lower than a simple logic gate implementation. However this requires full-custom design and need much effort. In our design, we'll use standard cell library for most units and only do custom design for the critical parts. But with carefully adjusted logic functions, we can construct our divide-by-5 cell with only NAND or NOR or complex invert gates. This saves both the size and time delay. x3 x2 x1 x0 q r2 r1 r Table 1 Truth table of division-by-5 cell q x3x2 x3x1x0 x3 x2( x1 x0) r2 x2x0 x1x0 x3x0 x2x1 x0 x3x0 r1 x3x1 x2x0 x3x0 x0 x2 x1 x0 x3 r0 x3x1x0 x3x0 x2x0 x2x1x0 x0 x2x3 x0 x3x1 x2x1 Table 2 Logic functions for the 4 output of divide-by-5 cell Theoretical analysis For the divide-by-5 cell, after the logic functions optimization, the average delay time from IRSIM is reduced to about one half of that not optimized. It's difficult to judge when we will get the worst case delay since these are complicated logic functions. From our experiments of many data, we found that worst case delay occurs when the input change from 0111 to 1000, t d = 2.04 ns. This is shown in figure 7 and marked the worst case with line. 10

Figure 7 IRSIM result for divide-by-5 cell There are total 7 div5 cells in the binary-to-bcd converter. However, each output will pass as most 6 cells.

11 Figure 7 IRSIM result for divide-by-5 cell There are total 7 div5 cells in the binary-to-bcd converter. However, each output will pass as most 6 cells. So the total time delay can be estimated as t( total delay) 6 t( div5 cell) From our simulations, we found the total delay is somewhat bigger than 6 times delay of each div5 cell. We think this is caused by the long metal lines. 3. Result. 3.1 Layout result According to the former discussion, we realized and layout our design. Please refer to the Fig.8 which is the component view. The data flow is from the bottom to the top. The component add8 is realizing the subtraction and comparison. Next, a row of compcell s are realizing the inversion and increment of the difference. This part transfer the negative number to the positive one. The following part, a row of muxes, selects the appropriate results as the difference and the smaller number according the comparison result from the component add8. The upper div5 arrays transfer the binary difference to the BCD code. Please refer to the Fig. 9 to get the detailed information about the layout. The layout area is 1388*850= Simulation result 11

12 Please refer to Fig. 10 to get the information of simulation result from IRSIM. We have analyzed the worst case situation in each part. But, this combinational logic consists of several parts. It is really impossible to find one input which is the worst case for all of them. I simulated a lots of inputs (in Fig.10) and found that the longest delay appears when the input B is 1 greater than input A (B-A=1). In fact this situation makes the data go through all the components. In some degree, it is the worst case. In Fig.10, they are a=0e & b=0f and a=92 & b=93. By the way, if this is a pipeline design, it will be very easy to analyze the worst cast situation. But of cause it will occupy more layout area and make the system more complex. We select three groups of inputs to show the functionality of your design. It shows a correct result. Please refer to the Fig.11. For the accurate timing result, we used the HSPICE to simulate our design. Please refer to Fig.12 and 13. From them, we find the worst delay for the output of smaller number is 19ns and for the difference is 23ns. So the worst case delay of our system is 23 ns. The system frequency is 43 MHz. 12

13 4. Appendix: 1. cmd file for the IRSIM simulation. l Gnd! h Vdd! stepsize 50 vector a a{7:0} vector b b{7:0} vector dif2 d2{3:0} vector dif1 d1{3:0} vector dif0 d0{3:0} vector small2 l2{3:0} vector small1 l1{3:0} vector small0 l0{3:0} analyzer a b dif2 dif1 dif0 small2 small1 small0 set a set b set a set b set a set b set a set b set a set b s50 set a set b set a set b set a set b set a set b

14 set a set b set a set b set a set b l Gnd! h Vdd! stepsize 50 vector a a{7:0} vector b b{7:0} vector dif2 d2{3:0} vector dif1 d1{3:0} vector dif0 d0{3:0} vector small2 l2{3:0} vector small1 l1{3:0} vector small0 l0{3:0} analyzer a b dif2 dif1 dif0 small2 small1 small0 set a set b set a set b set a set b spice file for the HSPICE simulation. **..omit the parameter and netlist generated by ext2sim command. *** the following was added by us. VDD vdd gnd 5 V0 a7 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 150ns 5v) 14

15 *011 V1 a6 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 150ns 0v) *100 V2 a5 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 100ns 5v 100.1ns 0v 150ns 0v) *010 V3 a4 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 150ns 5v) *011 V4 a3 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 100ns 0v 100.1ns 5v 150ns 5v) *101 V5 a2 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 100ns 0v 100.1ns 5v 150ns 5v) *101 V6 a1 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 100ns 5v 100.1ns 0v 150ns 0v) *010 V7 a0 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 150ns 0v) *100 V8 b7 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 150ns 5v) *011 V9 b6 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 150ns 0v) *100 V10 b5 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 100ns 5v 100.1ns 0v 150ns 0v) *010 V11 b4 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 150ns 5v) *011 V12 b3 gnd PWL(0ns 5v 150ns 5v) *111 V13 b2 gnd PWL(0ns 0v 100ns 0v 100.1ns 5v 150ns 5v) *001 V14 b1 gnd PWL(0ns 0v 50ns 0v 50.1ns 5v 100ns 5v 100.1ns 0v 150ns 0v) *010 V15 b0 gnd PWL(0ns 5v 50ns 5v 50.1ns 0v 100ns 0v 100.1ns 5v 150ns 5v) *101.OPTIONS POST.OPTIONS LIMPTS=200.TRAN 0.1ns 150ns.print TRAN V(input) v(ouput) ******************************************** 15

16 Reference 1. "Serial Code Conversion between BCD and Binary", by Peter Alfke, Bernie New 2. "AVR204: BCD Arithmetics", Application notes of ATMEL 3. "Comparison of different decomposition techniques of a digital circuit A study case", by M. Rawaski, P. Tomaszewicz, P. Amblard 4. "Binary To BCD Conversion", by M. Ganesh Raaja 16

Week 7: Assignment Solutions

Week 7: Assignment Solutions 1. In 6-bit 2 s complement representation, when we subtract the decimal number +6 from +3, the result (in binary) will be: a. 111101 b. 000011 c. 100011 d. 111110 Correct answer