Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions


 Valerie O’Brien’
 4 years ago
 Views:
Transcription
1 Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming
2 Boolean Cubes for n =, 2, 3, and 4 n = n = 2 n = 3 n = 4 Copyright by Daniel D. Gajski 2
3 Boolean Functions and Boolean Cubes Each Boolean ncube represents a Boolean function of n variables Each vertex represents a minterm Each msubcube represents 2 m minterms, m < n, with the same n m literals Each msubcube of minterm represent a product of n m literals = l l 2 l n m (x n m + x n m + 2 x n + x n m + x n m + 2 x n + + x n m + x n m + 2 x n ) = l l 2 l n m For any Boolean function a prime implicant is a subcube not contained in any other prime implicant As essential prime implicant is a subcube that contains a  minterm that is not included in any other prime implicant Copyright by Daniel D. Gajski 3
4 Representation of Carry and Sum Functions with Boolean Cubes c i x i y i c i + s i Truth Table Carry Function c i + Sum Function s i Copyright by Daniel D. Gajski 4
5 Map Representation (Karnaugh) maps define Boolean functions Map representation is equivalent to truth tables, Boolean expressions and Boolean cube representation Map aid in visually identifying prime implicants and essential prime implicants in each Boolean function Maps are used for manual optimization of Boolean functions Copyright by Daniel D. Gajski 5
6 Boolean Subcubes and Corresponding Karnaugh Maps for n =, 2, 3, and 4 x y x m m n = m 2 m 3 n = 2 xy zw yz x m m m 3 m 2 m m m 3 m 2 m 4 m 5 m 7 m 6 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 n = 3 m m 9 m m n = 4 Copyright by Daniel D. Gajski 6
7 2 variable variable Map x y x y x y x y Subcube x Subcube y xy 2 xy Subcube x Map Organization Example of subcubes Example: x y AND OR XOR Truth Table x y x y x y Copyright by Daniel D. Gajski AND 7 OR XOR
8 Three variable Map x yz x y z 3 2 x y z x yz x yz xy z xy z xyz xyz Map Organization x yz 3 2 Subcube z Subcube z Subcube x Example of 2subcubes x yz 3 2 Subcube x y Subcube yz Subcube xz Example of subcubes Copyright by Daniel D. Gajski
9 Map Representation of Carry and Sum Functions c i x i y i c i + s i c i x i y i Carry Function c i x i y i c i Sum Function s i 7 6 Truth Table Copyright by Daniel D. Gajski 9
10 Four variable Map zw xy 3 2 x y z w x y z w x y zw x y zw x yz w x yz w x yzw x yzw xyz w xyz w xyzw xyzw 9 xy z w xy z w xy zw xy zw Map Organization zw zw xy xy 3 2 Subcube y w 3 2 Subcube x Subcube x y Subcube w Subcube xz Copyright by Daniel D. Gajski Example of 2subcubes Example of 3subcubes
11 Representation of Greaterthan than and Lessthan Functions in Maps x x y y x x y y Greater Less Equal Than Than Truth Table y y x x Greaterthan Function G = x y + x y y + x x y L = x y + x x y + x y y Lessthan Function Copyright by Daniel D. Gajski
12 Five variable variable Map xy zw v = v = x y z w v x y z wv x y zwv x y zw v x y z w v x y z wv x y zwv x y zw v x yz w v x yz wv x yzwv x yzw v x yz w v x yz wv x yzwv x yzw v xyz w v xyz wv xyzwv xyzw v xyz w v xyz wv xyzwv xyzw v xy z w v xy z wv xy zwv xy zw v xy z w v xy z wv xy zwv xy zw v Map Organization xy zw v = v = x vw xz zw Copyright by Daniel D. Gajski 2 Example of 3subsubes and 4subcubes
13 Six variable Map xy zw v = v = xy zw v = v = m 3 2 m m 3 m m 6 m 7 m 9 m m m 5 m 7 m m 2 m 2 m 23 m u = m 2 m 3 m 5 m 4 9 m m 9 m m m 2 m 29 m 3 m m 24 m 25 m 27 m 26 u = x v m 32 m 33 m 35 m m 4 m 49 m 5 m u = m 36 m 37 m 39 m m 44 m 45 m 47 m m 42 m 53 m 55 m m 6 m 6 m 63 m 62 u = xz m 4 m 4 m 43 m m 56 m 57 m 59 m Map Organization z w Example of 4subcubes Copyright by Daniel D. Gajski 3
14 Boolean Simplification with Map Method Truth table, canonical form or standard form Generate map Determine prime implicants Select essential prime implicants Find minimal cover Standard form Copyright by Daniel D. Gajski 4
15 Boolean Simplification with Map Method Example: Problem: xy Maps method Using the map method, simplify the Boolean function zw F = w y z + wz + xyz + w y 3 2 xy zw Map Organization Prime Implicants in the Map Copyright by Daniel D. Gajski PI List: w z, wz,, yz, w y EPI List: w z, wz Cover List: () w z, wz,, yz (2) w z, wz, w y 5
16 Selection of Prime Implicants Example: Problem: Selection of prime implicants Simplify the Boolean function F = w x yz + w xy + wxz + wx y + w x y z xy zw PI List: w x z, w xy, wxz, wx y, x y z, wy z,, xyz, w yz EPI List: empty Cover List: () w x z, w xy, wxz, wx y (2) x y z, wy z,, xyz, w yz Copyright by Daniel D. Gajski 6
17 Don t Care Conditions Completely specified functions have a value assigned for every minterm Incompletely specified functions do not have values assigned for some minterms which are called don t care minterms (d minterms) or don t care conditions Don t care minterms can be assigned any value during simplifications in order to simplify Boolean expressions Copyright by Daniel D. Gajski 7
18 Don t Care Conditions Example: Problem: Don t care conditions Derive Boolean expressions for the 9 s s complement of a BCD digit x 3 x 2 x x x 3 x 2 x x Digits Nine s Complements Decimal BCD BCD Decimal x 3 x 2 x x x 3 x 2 x x Nine s Complement Table x 3 x 2 x x X X X X X X y 3 = x 3 x 2 x y 2 = x 2 x x x x 3 x 2 X X X X X X 4 X 2 X X X X X X X X X X X Copyright by Daniel D. Gajski y = x y = x Map Representation
19 Technology Mapping for Gate Arrays Gate arrays contain only one type of minput gate (such as 3input NOR, 3input NAND) Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type of gate Technology mapping consist of three tasks Conversion replaces each operator with an operator representing the gate function given in the gate array Optimization eliminates unnecessary inverters Decomposition replaces a ninput gate with an minput gate available in the gate array Copyright by Daniel D. Gajski 9
20 Conversion and Optimization Rule : Rule 2: Rule 3: Rule 4: Conversion Rules Rule 5: Conversion Procedure: Optimization Rules Replace AND and OR gates with NAND or NOR gates by using Rules 4, and eliminate double inverters whenever possible Copyright by Daniel D. Gajski 2
21 Translation of Standard Terms to NAND and NOR Schematics Form Type Standard Form Implementation NAND Implementation NOR Implementation Sum of products Product of sums Copyright by Daniel D. Gajski 2
22 Conversion to NAND (NOR) Gates Example: Problem: Conversion to NAND (NOR) gates Derive the NAND and NOR implementations of the carry function x i 2.4 x i.4 x i y i c i 3 2 y i c i c i + y i.4. c i + c i NAND Implementation Map Definition Carry Function c i + c i + = x i y i + x i c i + y i c i c i + = (x i + y i )(x i + c i )(y i + c i ) Standard Forms x i y i x i.4 c i + y i.4. c i + c i 2.4 c i.4 NOR Implementation Copyright by Daniel D. Gajski 22
23 Decomposition of input AND Gate into 3 input 3 AND Gates Level Number Number of Inputs Number of Gates [ / 3] = ( 3([ / 3])) = 4 + (4 3([4 / 3])) = 2 [4 / 3] = [2 / 3] = Input and Gate Computation on Each Level One Possible Decomposition Alternative Decomposition Copyright by Daniel D. Gajski 23
24 Technology Mapping for Gate Arrays Example: Technology mapping for gate arrays Problem: Implement the sum function using 3 input 3 NAND gates c i x i y i c i x i y i s i s i x i y i c i AND OR Implementation Conversion to NAND Network c i x i y i c i x i y i Map Definition Sum Function s i s i s i Copyright by Daniel D. Gajski OR Gate Decomposition 24 Optimized NAND Network
25 Design Retiming g 3 g 2 Example: Design retiming p 2 g Problem: Implement 4 bit 4 carrylook lookahead function c 4 = g 3 + g 2 + p 2 g + p 2 p g + p 2 p p c NAND gates using 3 input3 NAND p p c p 2 g p 2 p c 4 ANDOR Implementation g 3 g 3 g 2 g 2 p 2 g p 2 g p p p 2 g p 2 c 4 p p p 2 g p 2 c 4 c p c p Decomposition of ANDOR Implementation Performance Optimized Decomposition g 3 g 3 g 2. g 2.. p 2 g. p 2 g. p p p 2 g p c 4 p p p 2 g p c 4 c p. c p. NAND Implementation of Above Delay =.2ns Copyright by Daniel D. Gajski 25 Performance Optimized NAND Implementation Delay = 6.4ns
26 Technology Mapping Procedure for Gate Arrays Start Decompose Convert Eliminate invertors I/O delay OK? no yes Done Retime Copyright by Daniel D. Gajski 26
27 Technology Mapping for Custom Libraries Libraries contain gates with different functions and different delays Technology mapping means covering schematic with library gates Minimize delay on critical paths Minimize cost on noncritical paths Copyright by Daniel D. Gajski 27
28 Technology Mapping for Custom Libraries Example: Technology mapping for custom libraries Problem: Convert the expression w z + z(w + y) y into a logic schematic using any of the gates Convert the expression into a logic schematic using any of the gates defined in the digital logic gates, multipleinput input gates, and complex gates libraries y y.4 w z F w z 2. F AND OR Implementation (Delay = 7.2ns, Cost = 2) Alternative A (Delay = 5.4ns, Cost = 2) y w z F y w z F NAND Implementation (Delay =5.2ns, Cost = 22) Alternative B (Delay = 3.ns, Cost = 2) y w z.4 B.4.4 A.4 F y w z F Copyright by Daniel D. Gajski Two Possible Conversions 2 Cost Optimized Alternative B (Delay = 3.ns, Cost = )
29 Conversion Procedure for Custom Libraries Start Convert to NAND schematic Select a path Select gate Select a library component Record replacement gain no no no All paths considered? Recompute Delay Select maximum gain replacement yes All gates considered? yes All components considered? yes Done Copyright by Daniel D. Gajski 29
30 Chapter Summary Simplification of Boolean functions by Map method (visual) Technology mapping for gate arrays Decomposition Conversion Optimization Retiming Technology mapping for custom libraries by schematic covering with complex gates with Time optimization on circuit paths Cost optimization on noncritical paths Copyright by Daniel D. Gajski 3
GateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationNODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationDIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES
DIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the KMap, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationGateLevel Minimization
GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to GateLevel Minimization The Map Method 2345 variable map methods ProductofSums Method Don t care
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationTWOLEVEL COMBINATIONAL LOGIC
TWOLEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms Tolevel simplification Boolean cubes Karnaugh maps QuineMcClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationece5745planotes.txt
ece5745planotes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationGraduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB
CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived
More informationCS February 17
Discrete Mathematics CS 26 February 7 Equal Boolean Functions Two Boolean functions F and G of degree n are equal iff for all (x n,..x n ) B, F (x,..x n ) = G (x,..x n ) Example: F(x,y,z) = x(y+z), G(x,y,z)
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More information1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z
CS W3827 05S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationOutcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps
.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationDr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010
Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010 Instructions: This examination paper includes 9 pages and 20 multiplechoice questions starting on page 3. You are responsible for ensuring that your
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationSpring 2010 CPE231 Digital Logic Section 1 Quiz 1A. Convert the following numbers from the given base to the other three bases listed in the table:
Section 1 Quiz 1A Convert the following numbers from the given base to the other three bases listed in the table: Decimal Binary Hexadecimal 1377.140625 10101100001.001001 561.24 454.3125 111000110.0101
More informationComputer Engineering Chapter 3 Boolean Algebra
Computer Engineering Chapter 3 Boolean Algebra Hiroaki Kobayashi 5/30/2011 Ver. 06102011 5/30/2011 Computer Engineering 1 Agenda in Chapter 3 What is Boolean Algebra Basic Boolean/Logical Operations (Operators)
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationCS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps Kmap Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/kmapswalksandgraycodes/
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms
More informationKarnaugh Maps. Kiril Solovey. TelAviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22
Karnaugh Maps Kiril Solovey TelAviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationDepartment of Electrical and Computer Engineering University of Wisconsin  Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:158:3PM 1. (15 points) (a) (5 points) NAND, NOR
More informationICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design Lecture 10 Eli Bozorgzadeh Computer Science DepartmentUCI Reference Lecture note Ankur Srivastava http://www.enee.umd.edu/class/enee644/ Chapter 7(7.3,7.4) of the
More informationBOOLEAN ALGEBRA. 1. State & Verify Laws by using :
BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More informationCombinational Logic with MSI and LSI
1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010
More informationUnitIV Boolean Algebra
UnitIV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More information/90 TOTAL. 1(a) 8pts. fiv(a,b) is called the function.
Your Name: SID Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer
More informationGATE Exercises on Boolean Logic
GATE Exerces on Boolean Logic 1 Abstract Th problem set has questions related to Boolean logic and gates taken from GATE papers over the last twenty years. Teachers can use the problem set for courses
More information(Refer Slide Time 5:19)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture  7 Logic Minimization using Karnaugh Maps In the last lecture we introduced
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitI 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationINDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator
INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator EXAMINATION ( Mid Semester ) SEMESTER ( Spring ) Roll Number Section Name Subject Number C S 2 1 0 0 2 Subject Name Switching
More informationLecture 22: Implementing Combinational Logic
8 Lecture 22: Implementing ombinational Logic S 5 L22 James. Hoe Dept of EE, MU April 9, 25 Today s Goal: Design some combinational logic circuits Announcements: Read Rizzoni 2.4 and 2.5 HW 8 due today
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationSynthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1
Synthesis 1 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, 1998. Typeset by FoilTEX 1 Introduction Logic synthesis is automatic generation of circuitry
More informationObjectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure
Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationUNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM.
UNCA CSCI 255 Exam 1 Spring 2017 27 February, 2017 This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. Communication with anyone other than the instructor is not allowed during
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationVariable, Complement, and Literal are terms used in Boolean Algebra.
We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem  IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More information