數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷


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1 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷 FuwYi Yang 1
2 Chap 3 GateLevel Minimization 3.1 Introduction 3.2 The Map Method 3.3 FourVariable Map 3.4 FiveVariable Map 3.5 ProductionofSums Simplification 3.6 Don'tCare Conditions 3.7 NAND and NOR Implementation 3.8 Other TwoLevel Implementation 3.9 ExclusiveOr Function 3.10 Hardware Description Language FuwYi Yang 2
3 Chap 3.1 Introduction Gatelevel minimization refers to the design task of finding an optimal gatelevel implementation of the Boolean functions describing a digital circuit. It is important that a designer understand the underlying mathematical description and solution of a problem. FuwYi Yang 3
4 Chap 3.2 The Map Method Boolean expression may be simplified by algebraic means as discussed in Section 2.4. However, this procedure of minimization is awkward because it lacks specific rules to predict each succeeding step in the manipulative process. The map method (also known as the Karnaugh map or Kmap) provides a simple, straightforward procedure for minimizing Boolean functions. FuwYi Yang 4
5 Chap 3.2 The Map Method twovariable map Figure 3.1 TwoVariable map FuwYi Yang 5
6 Chap 3.2 The Map Method twovariable map Figure 3.2 Representation of functions in the map FuwYi Yang 6
7 Chap 3.2 The Map Method threevariable map Figure 3.3 Threevariable map FuwYi Yang 7
8 Chap 3.2 The Map Method Example 3.1 Simplify the Boolean function F(x, y, z) = Σ(2, 3, 4, 5) Figure 3.4 F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy' FuwYi Yang 8
9 Chap 3.2 The Map Method Example 3.2 Simplify the Boolean function F(x, y, z) = Σ(3, 4, 6, 7) Figure 3.5 F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz' FuwYi Yang 9
10 Chap 3.2 The Map Method Example 3.3 Simplify the Boolean function F(x, y, z) = Σ(0, 2, 4, 5, 6) Figure 3.6 F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' + xy' FuwYi Yang 10
11 Chap 3.2 The Map Method Example 3.4 a. Express F as a sum of minterms. b. Find the minimum SOP. Figure 3.7 F = A'C + A'B + AB'C + BC = Σ(1, 2, 3, 5, 7) = C + A'B FuwYi Yang 11
12 Chap 3.3 The Map Method FourVariable Map FuwYi Yang 12
13 Chap 3.3 The Map Method FourVariable Map FuwYi Yang 13
14 Chap 3.3 The Map Method Example 3.5 Simplify F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) Figure 3.9 F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y'+ w' z'+ x z' FuwYi Yang 14
15 Chap 3.3 The Map Method Example 3.5 FuwYi Yang 15
16 Chap 3.3 The Map Method Example 3.6 Simplify F(A, B, C, D) = A'B'C' + B'CD' + A'BCD' + AB'C' Figure 3.10 F = A'B'C' + B'CD' + A'BCD' + AB'C' = B'C' + B'D' + A'CD' see next page FuwYi Yang 16
17 Chap 3.3 The Map Method Example 3.6 FuwYi Yang 17
18 Chap 3.3 The Map Method Prime implicants In choosing adjacent squares in a map, we must ensure that (1) all the minterms of the function are covered when we combine the squares, (2) the number of terms in the expression is minimized, and (3) there are no redundant terms (i.e., minterms already covered by other terms). FuwYi Yang 18
19 Chap 3.3 The Map Method Prime implicants A prime implicant is a product term obtained combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential. Simplify F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) See next pages FuwYi Yang 19
20 Chap 3.3 The Map Method prime Two essential prime implicants: BD and B'D' FuwYi Yang 20
21 Essential prime implicants: BD and B'D' Prime implicants: AD, CD, B'C, and AB' F = BD+B'D' +CD+ AD OR BD+B'D' +CD+ AB' OR BD+B'D' +B'C+ AD OR BD+B'D' + B'C FuwYi Yang 21
22 Chap 3.5 ProductofSums Simplification Example 3.8 Simplify F(A, B, C, D) = Σ(0, 1, 2, 5, 8, 9, 10) into a. sumofproducts form, taking the procedures as described previously, i.e., group the squares marked by 1 s and combine them. b. productofsums form. Group the squares marked by 0 s and combine them, i.e., we obtain F ' in the form of sumofproduct. Because of the generalized DeMorgan s theorem, the productofsums form is also obtained. Procedures see next page FuwYi Yang 22
23 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan s theorem to F', F = (A' + B') + (C' + D') + (B' + D) FuwYi Yang 23
24 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan s theorem to F', F = (A' + B') + (C' + D') + (B' + D) Implementation see next pages FuwYi Yang 24
25 FuwYi Yang 25
26 Chap 3.5 ProductofSums Simplification a. sumofproducts form b. productofsums form These two forms can also obtain from truth table, see next page. FuwYi Yang 26
27 Chap 3.5 ProductofSums Simplification Table 3.2 x y z F m 0, M m 1, M m 2, M m 3, M m 4, M m 5, M m 6, M m 7, M 7 F(x, y, z) = Σ(1, 3, 4, 6) F(x, y, z) = Π(0, 2, 5, 7) = (x' + z') (x + z) See next page, note that we express F directly in the POS form. FuwYi Yang 27
28 F(x, y, z) = Σ(1, 3, 4, 6) F'(x, y, z) = Σ(0, 2, 5, 7) By DeMorgan s Theorem F(x, y, z) = Π(0, 2, 5, 7) = (x' + z') (x + z) FuwYi Yang 28
29 Chap 3.6 Don t Care Conditions Functions that have unspecified outputs for some input combinations are called incompletely specified functions. In most applications, we simply don t care what value is assumed by the function for the unspecified minterms. For this reason, it is customary to call the unspecified minterms of a function don t care conditions. These don t care conditions can be used on a map to provide further simplification of a Boolean expression. FuwYi Yang 29
30 Chap 3.6 Don t Care Conditions Example 3.9 Simplify the Boolean function F(w, x, y, z) = Σ(1, 3, 7, 11, 15) which has the don t care conditions d(w, x, y, z) = Σ(0, 2, 5). FuwYi Yang 30
31 FuwYi Yang 31
32 Chap 3.7 NAND and NOR Implementation Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in the design of digital circuits, rules and procedures have been developed for the conversion from Boolean functions given in terms of AND, OR, and NOT into equivalent NAND and NOR logic diagrams. FuwYi Yang 32
33 Chap 3.7 NAND and NOR Implementation  NAND Circuits The NAND gate is said to be a universal gate because any digital system can be implemented with it. FuwYi Yang 33
34 Chap 3.7 NAND and NOR Implementation  NAND Circuits A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NAND logic. The conversion of an algebraic expression from AND, OR, and complement to NAND can be done by simple circuit manipulation technique that change ANDOR diagrams to NAND diagrams.(minterms) FuwYi Yang 34
35 Chap 3.7 NAND and NOR Implementation  NAND Circuits Two equivalent graphic symbols for the NAND gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NAND expressions. See next page. FuwYi Yang 35
36 Chap 3.7 NAND and NOR Implementation  Three ways to implement F = AB + CD (twolevel) (x')' = x ANDOR Equivalent symbols of NAND Implemented with NAND gates FuwYi Yang 36
37 Chap 3.7 NAND and NOR Implementation  Example 3.10 Twolevel Implement F(x, y, z) = Σ(1, 2, 3, 4, 5, 7) with NAND gates. After simplification, F(x, y, z) = xy' + x'y + z ANDOR (x')' = x Implemented with NAND gates FuwYi Yang 37
38 Chap 3.7 NAND and NOR Implementation  NAND CircuitsMultilevel There are occasions, however, when the design of digital systems results in gating structures with three or more levels. The most common procedure in the design of multilevel circuits is to express the Boolean function in terms of AND, OR, and complement operations. The function can then be implemented with AND and OR gares. After that, if necessary, it can be converted into an allnand circuit. See next page. FuwYi Yang 38
39 Chap 3.7 NAND and NOR Implementation  NAND CircuitsMultilevel ANDOR (x')' = x FuwYi Yang 39
40 NAND CircuitsMultilevel FuwYi Yang 40
41 Chap 3.7 NAND and NOR Implementation  NOR Circuits The NOR gate is said to be a universal gate because any digital system can be implemented with it. FuwYi Yang 41
42 Chap 3.7 NAND and NOR Implementation  NOR Circuits A convenient way to implement a Boolean function with NOR gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NOR logic. The conversion of an algebraic expression from AND, OR, and complement to NOR can be done by simple circuit manipulation technique that change ORAND diagrams to NOR diagrams. (maxterms) FuwYi Yang 42
43 Chap 3.7 NAND and NOR Implementation  NOR Circuits Two equivalent graphic symbols for the NOR gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NOR expressions. See next page. FuwYi Yang 43
44 Chap 3.7 NAND and NOR Implementation  NOR Circuits Implementing F = (A + B) (C + D) E with NOR gates Note that ORAND Equivalent symbols of NOR FuwYi Yang 44
45 Chap 3.7 NAND and NOR Implementation  NOR Circuits Implementing F = (AB' + A'B) (C + D') with NOR gates Note that ORAND Equivalent symbols of NOR FuwYi Yang 45
46 Chap 3.8 Other TwoLevel Implementations The types of gates most often found in integrated circuits are NAND and NOR gates. For this reason, NAND and NOR logic implementations are the most important from a practical point of view. Some NAND and NOR gates allow the possibility of a wire connection between the outputs of two gates to provide a specific logic function. This type of logic is called wired logic. See next pages FuwYi Yang 46
47 Chap 3.8 Other TwoLevel Implementations Wired logic FuwYi Yang 47
48 Chap 3.8 Other TwoLevel Implementations ANDORINVERT FuwYi Yang 48
49 Chap 3.8 Other TwoLevel Implementations ORANDINVERT FuwYi Yang 49
50 Chap 3.8 Other TwoLevel Implementations FuwYi Yang 50
51 Chap 3.8 Other TwoLevel Implementations Example 3.11 Implement the function of the following map with the four 2level forms listed in Table 3.3. FuwYi Yang 51
52 Chap 3.8 Other TwoLevel Implementations Example 3.11 ANDNOR ANDORNOT F' = x'y + xy' + z combined squares of the 0 s. Thus F = (F')' output gate NOR = OR+NOT FuwYi Yang 52
53 Chap 3.8 Other TwoLevel Implementations Example 3.11 NANDAND ANDORNOT F' = x'y + xy' + z combined squares of the 0 s. Thus F = (F')' = (x'y + xy' + z)' = (x'y)' (xy')'z' output gate AND FuwYi Yang 53
54 Chap 3.8 Other TwoLevel Implementations Example 3.11 ORNAND ORANDNOT F = x'y'z' + xyz' combined squares of the 1 s. Thus F = (F')' = ((x + y + z) (x' + y' + z))', orandnot. output gate NAND = AND + NOT FuwYi Yang 54
55 Chap 3.8 Other TwoLevel Implementations Example 3.11 NOROR ORANDNOT F = x'y'z' + xyz' combined squares of the 1 s. Thus F = (F')' = ((x + y + z) (x' + y' + z))' = (x + y + z)' + (x' + y' + z)', output gate OR. FuwYi Yang 55
56 Chap 3.9 ExclusiveOR Function The exclusiveor (XOR), denoted by the symbol, is a logical operation that performs the following Boolean operation: x y = x'y + xy'. It can be shown that the exclusiveor operation is both commutative and associative; that is, x y = y x and (x y) z = x (y z) = x y z. For implementation, see next pages. FuwYi Yang 56
57 Chap 3.9 ExclusiveOR Function ANDORNOT implementation FuwYi Yang 57
58 Chap 3.9 ExclusiveOR Function  NAND implementation FuwYi Yang 58
59 Chap 3.9 ExclusiveOR Function  ODD Function x y = x'y + xy' x y z = xy'z' + x'yz' + x'y'z + xyz The Boolean expression clearly indicates that the XOR functions are equal to 1 if and only if an odd number of variables equal to 1. FuwYi Yang 59
60 Chap 3.9 ExclusiveOR Function Parity Generation and Checking FuwYi Yang 60
61 Chap 3.9 ExclusiveOR Function Parity Generation and Checking x Y z P Four bits are transmitted FuwYi Yang 61
62 Chap 3.9 ExclusiveOR Function Parity Generation and Checking x y z P Four bits are transmitted Check four lines (x, y, z, P) See next page FuwYi Yang 62
63 FuwYi Yang 63
64 Chap 3.10 Hardware Description Language HDL Example 3.1 module Simple_Circuit(A, B, C, D, E); output D, E; input A, B, C; wire w1; and G1(w1, A, B); not G2(E, C); or G3(D, w1, E); endmodule FuwYi Yang 64
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