Index. B Back-annotation, 507 SDF, 508

Transcription

1 $display, 57, 206 example, 69, 225 $fatal, SystemVerilog, 538 $finish, 206, 245 $fullskew timing check, 366 $hold timing check, 366 $info, SystemVerilog, 538 $monitor, 217 $monitor, 57 $nochange timing check, 368 $period timing check, 368 $recovery timing check, 367 $recrem timing check, 368 $removal timing check, 367 $sdf_annotate command, 509 $setup timing check, 366 $setuphold timing check, 367 $skew timing check, 366 $stop, 206, 245 system task, 372 $strobe, 57, 217 example, 225 $time, 57 $timeskew timing check, 366 $warning, SystemVerilog, 538 $width timing check, 368 &&&, in timing check, 371 *, in event control, 71 `default_nettype, 233, 269 `define, scope, 334 `ifdef, example, 49, 104 `include, example, 103 `timescale, 32, 269 >, Event control trigger, SX microprocessor, 476 A Adder vs. counter, 137 ALF language, 529 library format, 149 always block, 44, 221, 246 for concurrency, 253 event control syntax, 54 name = vars preserved, 258 reading rationale, 217 AndOr.v, 18 Arithmetical shift, 156 Array addressing, 118 multidimensional, 117 select, 118 verilog, 116 Arrayed instance, 266 Assertion defined, 57, 363 example, 85 in serdes design, 499 assign, continuous, 18, 31 Assign-deassign, to avoid, 151 assign-deassign, to be avoided, 519 Assignment blocking, 54, 154, 222 nonblocking, 54, 55, 154, 222 Assignment statement, 27 Asynchronous control flip-flop, 74 priority, 74 automatic function recursion, 256 automatic keyword, 256 automatic task or function, 185 B Back-annotation, 507 SDF, 508 J.M. Williams, Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute, 543 DOI / , Springer International Publishing Switzerland 2014

2 544 Index Backus-Naur Format (BNF), 70 BASIC programming language, 522 Behavioral, 135, 136 flowchart, 170 synthesis, 177 Behavioral synch, serial clock, 169 Binary counter preloaded wraparound, 134 programmed wraparound, 134 BIST. See Built-in self-test (BIST) Bit select, 30 Bitwise operators, 28, 33, 33, 46 Block concurrent, 69 procedural, 69 BNF. See Backus-Naur Format (BNF) Boolean operators, 32, 33 Boundary scan, 473 Buffer, three-state, 160 bufif1, 158, 232 better cmos model, 310 cmos model, 310 example, 270 switch-level model, 309 Built-in self-test (BIST), 476 insertioncan, 477 in isolated systems, 478 test pattern example, 483 C Case equality operator, 156, 250 Case-sensitivity, verilog, 25 case statement, 53 example, 156, 158, 250 expression match, 249 casex to be avoided, 251 expression match, 251 casez to be avoided, 253 expression match, 252 wildcard match, 253 cell, configuration keyword, 347 Charge strength, 309, 312 trireg, 149 verilog, 149 Checksum, 122 Chip failures, causes, 527 Clock implementing, 55 serdes embedded, 288, 292, 294, 297 Clock domains, 141 independent, 337 indeterminate sampling, 338 serdes, stage synchronizing ffs, 339 synchronizing latches, 339 Clocked block, 73 Clock generator always, 56 concurrent, 246 forever, 56 restartable, 247 cmos, switch-level primitive, 309 Collapsing test vectors, 471 Comment macro regions, 43, 48 synthesis directive, 43 verilog, 43 Comment tokens, verilog, 26 Compiler directive = macro, 50 verilog list, 521, 521 Concatenation, verilog, 120 Concurrent block, 69 Concurrent block names, Conditional operator, 53, 157 expression match, 250 config, 346 to be avoided, 347 configuration keyword, 346 verilog configuration, 346 Constant, verilog, 68 Contention, 150, 160 in verilog, 149 Continuous assignment, 18, 31, 45, 73 Corner case testing, 473 Counter, 133, 137 behavioral, 144 carry look-ahead, 139 gray code, 140

3 545 one-hot, 134 overclocked, 142 ring, 140 ripple, 138 synchronous, 139 unsigned binary, 133 verilog, 100, 107 Coverage hardware testing, 471 in software, 471 summary, 472 D Dataflow modelling, 136 Datapath, 209 vs. control unit, 197 DC. See Design compiler (DC) Decoder example, 273 tree example, 274 verilog, 158 Decoder example, better, 274 Decoder tree, generate example, 276 Deep submicron effects, 525 default, configuration keyword, 346, 347 defparam, to avoid, 151 defparam, to be avoided, 327, 519 Delay avoiding procedural, 290 blocking, 215 conditional in specify, 354 conflict within specify, 356 declared on net, 350 distributed, 348 full-path, 353 ifnone in specify, 355 intraassignment, 211, 212, 213 lumped, 348, 350 min and max, 306 multivalue, 213, 214, 214, 228, 306 nonblocking, 212, 215 not in UDP, 302 overlap with specify, 356 parallel-path, 353 pessimism, 214, 305 polarity in specify, 355 procedural, 42, 213, 222 regular, 211 SDF always supersedes, 357 with strength, 305 in synthesizable code, 204 timing triplet, 307 transport (VHDL), 212 trireg to 'x,' value in specify, value in specify, 354 vector net, 228 to x, 214 Delay pessimism, moderated in specify, 374 Delay triplet, example, 350 Delay value, units, 29 DesDecoder project synthesizable, 417 purpose, 291 redesign, 407 Deserialization decoder, purpose, 291 Deserializer generic, 289 project schematic, 400 Deserializer, concurrent schematic, 415 Design compiler (DC) flattening logic, 87 macro, predefined, 48 design, configuration keyword, 347 Design for Test (DFT), 469 summarized, 438 Design partitioning rules, for synthesis, 337 design_vision netlist viewer, 23 schematic viewer, 25 D flip-flop from nands, 236, 238, 240 verilog, 61 disable example, 169 task or function, 186 disable statement, 166 D latch, verilog, 61 dont_touch examples, 430

4 546 Index in verilog, 108 Drive strength, verilog, 148 DVE gui, 21 E ECC. See Error-checking and correction (ECC) ECO, example, 293 Edge functional defined, 305 timing defined, 305 endconfig, configuration keyword, 346 Equivalence checking verification, 529 Error-checking and correction (ECC), 120, 122, 123, 126 finite element, 124 parity, 123 simple LFSR, 125 Error-handler, generic, 205 Error limit, pulse filter, 372 Event active, 212, 216, 217 vs. evaluation, 216 future, 217 inactive (#0), 216, 217, 217 $monitor, 217, 217 nonblocking, 217, 217 queue example, 218 regular, 212 event (keyword), 221 Event control, 44 declared, 221 inline, 54 wait, 221 Event 220 Event control, > trigger, 221 Event queue stratified, 215, 216 verilog, 151 Exponentiation, verilog, 156 Expression, defined, 71 F Fault simulator, 471 First-in, first-out (FIFO), 167 bubble diagram, 198 clock domains, 292 dataflow, 191 dual-clocking project, 416 dual-port RAM, 416 introduction, 190 operational details, 192 project states, 198 project synthesizable, 417 read-write parts, 192 schematic, 197 state logic, 199 transition logic, 200, 202, 203 for, 53 ease of use, 249 examples, 248 vs. while, 249 Force-release, to avoid, 151 force-release to be avoided, 519 forever, 246 termination, 246 forever loop, 245 fork-join, 187, 212, 253, 254 example, 188 for loop, 245, 247 in generate, 269 Formal proving verification, 529 Format specifier, 58 example, 58 Frame, serdes project, 98 Full-duplex serdes, 490 Full-path delay, 353 Full scan, 475 Function declaration, 184, 185 Shift1, 289 Shift1 improved, 290 function, 184, 185 automatic, 256 automatic for recursion, 256 example, 186 width indices, 256 G Gate-level, 137 generate block declarations, 272

5 547 conditional, decoder tree, 276 downward hierarchy names, 266 looping, 269, looping example, 270 loop scope quiz, 284 Mem1kx32gen reqts, 282 no nesting, 269 simple decoder, 273 unrolled naming, 272 generate loop, vector, 279 generate statement, 267 genvar example, 270 in looping generate, 269 H Hard macro, defined, 108 Header format, 1995, 42 Header format, 2001, 42 Header formats, contrasted, 41 Hierarchy, in verilog, 263 I Identifier, 69 in ASIC library, 303 escaped, 69 verilog, 69 if, 53, 245 expression match, 249 iff, example, 533 ifnone delay in specify, 355 Inertial delay, 143, 154, 155, 372 PATHPULSE example, 373 simulator errors, 214 initial block, 26, 44, 246 cautions, 56 example, 16, 27, 28 inout, not in UDP, 302 inout port, 234 input port, VHDL or SystemVerilog, 235 Instance arrays, 266 instance, configuration keyword, 347 Instantiation, of module, 29 integer, 68 interface, in SystemVerilog, 335 Interface, partitioning, 335 Internal scan, 475 Intro_Top scan chain, 85 scan I/O, 81 scan outputs, 87 Intro_Top.v, 15 J JTAG port, 76, 78, 80, 88 JTAG standard, 474 K Keywords, lower case, 25 L Lane, defined, 490 Lane, PCIe, lane, 96 large, charge strength, 312 Latch cts assign, 72 flip-flop preferred, 73 glitch-proof, 60 vs. mux, 71 synthesis, 72 synthesizable, 72 verbose synthesis, 72 LFSR. See Linear feedback shift register (LFSR) Liberty language, 529 Liberty, library format, 149 Liberty library timing checks, 364 LIFO, 190 Linear feedback shift register (LFSR), 122, 124, 125, 478 polynomial, 123 simple, 125 Literal, 68 Literal expression, syntax, 28 Literal syntax, 46 Literal, syntax example, 31 Localparam, 281 localparam conditional example, 440 declaration, 324

6 548 Index examples, 343 sized, 428 sized state decs, 428 Logical operators, 28, 32 Logic levels in verilog, 28, 28 M Macro example, 103 recommended usage, 49 Macro (compiler directive), 70 Macro, = compiler directive, 50 medium, charge strength, 312 Memory dual-port DPMem1kx32, 421 ECC, 120 random access, 115 sequential access, 115 Mentor proprietary information, 3 Messaging tasks, 56 Model checking verification, 529 module, 25, 26 ANSI header, 324, 326 for concurrency, 255 output reg ports, 519 scope, 334 traditional header, 324, 326 Module, example, 26 Module header, 27, 27 formats, 40 module instance, scope, 334 MOS resistive strength rules, 308 switch-level primitives, Mux schematic, 63 switch-level model, 315 verilog, 63 N Named block, 165, 166, 186 nand, switch-level model, 316 Net, definition, 67 nmos primitive, 308, 310 Noise estimation problems, 530 none implied net default, 233 nor, switch-level model, 316 noshowcancelled specparam, 375 not example, 270 switch-level model, 311 notif1 example, 270 Notifier, 365 Notifier, in timing check, 364, 371 Notifier reg example, 372, 379 O Observability, hardware testing, 470 Operator precedence, verilog, 157 Operators bitwise vs. logical, 164 verilog table, 156 P Packet serdes, 168 Packet serdes project, 98 Parallel block (fork-join), 187 Parallel-path delay, 353 Parallel-serial converter, 108 Parameter, 48 declaration, 235 override, 235 vs. port declaration, 235 real, 103 signed, 103 parameter, 42, 68, 280 in ANSI header, 324 generic declaration, 324 index range, 324 not in literals, 107 override by name, 325 override by position, 325 real, 324 signed, 324, 325 Parity memory, 121 serdes data, 127 xor ^ operator, 121 Partitioning, analog-digital example, 294 Part select, 30 Pass-switch primitives, 311 Path delays, full and parallel, 353

7 549 PATHPULSE conflict rules, 373 inertial delay control, 373 specparam, 373 PATHPULSE example, 373 PCI Express (PCIe), 96 analogue issues, 97 lane, 96 Phase-locked loop (PLL), 89 clock-comparator, 106 clock extraction, 168 digital lock-in, 93 SerialRx.v, 403 smooth comparator, 93 synthesizable, 384, 400 synthesizable ClockComparator, 388 synthesizable design block diagram, 399 synthesizable sync function, x, x blocks, x schematic, 102 PLI, verilog, 521 PLL. See Phase-locked loop (PLL) PLL 1x, 90 schematic, 90 synthesizable, pmos primitive, 308, 310 Port connection rules, 234 Port declaration, 27 Port map, of module, 29 Power distribution problems, 530 Primitive switch-level logic, 231 verilog gates, 231 primitive, 301 scope, 334 Problems noise estimation, 530 power distribution, 530 Procedural, 135 assignment, 31 block, 69 Procedural block names, Property specification language (PSL), 529 PSL language, 537 pulldown gate, 232 pulldown primitive, 312 pullup gate, 232 pullup primitive, 312 Pulse filtering delay limits, 372 pulsestyle_ondetect inertia, 374 pulsestyle_ondetect specparam, 374 pulsestyle_onevent inertia, 374 pulsestyle_onevent specparam, 374 R Race condition, 74, 152, 153, 215 defined, 152 Race, initial blocks, 154 RAM bidir wrapper, 131 Mem1kx32 schematic, 129 simple verilog, 119 size issues, 116 rcmos primitive, 311 realtime reg type, 375 real variable, 90 Reconvergent fanout, 59 Reduction operator, 33, 34, 46 reg, 30 input port illegal, 42 in output port, 42 vs. trireg, 312 Register Transfer Logic (RTL), 30, 136, 169 defined, 136 Rejection limit, pulse filter, 372 Relational expression, of 'x,' 155 Relational operator, 46, 46 repeat, 247 repeat loop, 247 Replication operator, 157 rnmos primitive, 308 Rounding of decimals, 103 rpmos primitive, 308 rtranif0 primitive, 311 rtranif1 primitive, 311 rtran primitive, 311 S Scan boundary, 78, 473

8 550 Index chain, 84 full, 475 internal, 76, 475 Scan chain, Intro_Top, 85 Scheduled conflicts, 215 SDF annotation messages, VCS, 465 back annotation, 508 delay always prevails, 357 file, 36 file sample, 514 net delays, 508 overrides delays, 508 path delays, 508 summary, 509 syntax, 508, 509 use with simulator, 509 in verilog flow, 508 Serdes class project, 98 clock domains, 167 DesDecoder, 299 embedded clock, 168, 288, 292 FIFO, 97 file organization, final, 448 full-duplex project, 490 packet, 111 project block diagram, 382, 446 SerEncoder, block diagram, 452 Serializer, project schematic, 449 Serial-parallel converter, 287 Set_dont_touch, examples, 430 Shift, arithmetical, 156 Shift register, 58 example, 440 parallel-load, 63 procedural, 64 RTL, 64 schematic, 59, 62, 64 serial load, 62 showcancelled inertia, 375 showcancelled specparam, 374 Simulation unknowns, display values, 31 Simulators, strength spotty, 158 small, charge strength, 312 Soft errors, hardware, 470, 478 Source switch-level models, 312 specify block, 351 summary, value delays, 354 specify, specparam, 351 defined, 352 example, 353, 360 with timing triplets, 353 SPICE, 310 in verilog A/MS, 539 SR latch, 236, 237 SR.latch, 19 SR latch, reset sequence, 241 SR.v, 19 Standard parasitic exchange format (SPEF), 508 State clock generator, synthesizable, 429 State machine design, 189 verilog, 189 Statement, defined, 71 Static serial clock synch, 178 Strength assigning, 150 charge, 149 charge values, 312 with delay, 305 drive, 148 resistive MOS rules, 309 table, 150 String verilog, 68 verilog storage, 56 Structural, 135, 136 supply0 net type, 233 supply1 net type, 233 Switch level model, 149, 307 Synopsys Design Constraint format (SDC), 520 Synopsys proprietary information, 3 Synthesis, importance of, 37 SystemC, can use SDC, 520 System function, 70 System task, 70 System tasks and functions, 521 verilog list, 520 SystemVerilog, 531

9 551 always_comb block, 534 always_ff block, 534 always_latch block, 534 assertion language example, 538 break command, 534 continue command, 535 $fatal, 538 $info, 538 interface example, 536 logic type, new assertion language, new bit type, 533 new gated event control iff, 533 new interface type, new looping commands, new timescale alternatives, 534 primary features, return command, 535 structure, 531 unbased, unsigned ' literals, 533 $warning, 538 T table in sequential UDP, 304 in UDP, TAP controller, 78, 474, 478 TAP port, 527 task, 184, 185 automatic, 256 automatic vars not shared, 256 for concurrency, 253 concurrency example, 254 exercise, 205 local vars static shared, 256 Task data sharing, 185 Task declaration, 184 Task, Unload32, 290 Testbench Intro_Top. example, 16 Test vectors, collapsing, 471 T flip-flop, 138 T flip-flop, 180 Three-state buffer, 157, 160 time reg type, 375 Timescale macro, 29 Timescale specifier, 17 Timing arc defined, 347 examples, 348 Timing check, 70 as assertion, 364 avoiding negative limits, 371 conditional event, 371 data event, 364 feature summary, 364 $fullskew, 366 $hold, 366 Liberty library, 364 limits must be constant, 365 negative limits, 369, 370 $nochange, 368 notifier, 364, 371, 372 $period, 368 in QuestaSim, 366 $recovery, 367 $recrem, 368 reference event, 364, 365 $removal, 367 $setup, 366 $setuphold, 367 $skew, 366 vs. system tasks, 363 table of 12, 365 timecheck event, time limits, 365 $timeskew, 366 timestamp event, 365 $width, 368 Timing paths and arcs, 348 causality, 348 Timing triplets, 307 example, 350 Toggle flip-flop, 138 tranif0 primitive, 311, 315 tranif1 primitive, 311, 315 tran primitive, 311, 312 Transfer-gate primitives, 311 triand net type, 233

10 552 Index tri net type, 233 tri0 net type, 233 tri1 net type, 233 trior net type, 233 trireg charge strength, 149 example, 313 net type, 233 pulse-filter model, 317 switch-level net, 312 vs. tran primitive, 311 TSMC proprietary information, 3 U UDP. See User-defined primitives (UDP) use, configuration keyword, 347 User-defined primitives (UDP), 301 combinational example, 302 sequential example, 303 summary, 304 V VAMS = verilog A/MS, 539 Variable-frequency oscillator (VFO) new comparator sampler, 383 old comparator sampler, 383 project FastClock oscillator, 385 synthesizable, 385, 386 VCD file, 35 VCS, schematic viewer, 23 Vector, 29, 45 bit significance, 32 example, 32 index syntax, 30 logical operator, 46 negative index, 52 select, 119 sign bit, 45 type conversions, 47 verilog, 116 width (type) conversion, 47 Verification equivalence checking, 529 formal, 529 formal proving, 529 functional, 528 model checking, 529 timing, 528 Verilog arrayed instance, 266 attributes unused, 519 clocked block, 222 coding rules, 220, 222 comment directives, 519 compiler directive list, 521, 521 compiler directives, 518 conditional compile, 267 configuration, 346 declaration ordering, 257 declaration regions, 257 hierarchical names, 264, 265, 333 hierarchy path, 263 keywords, 518 named block, 165 old ACC C routines, 523 old TF C routines, 523 operators, 46 PLI, 70, 519, 521 PLI VPI C routines, 523 scope of names, 334 simulator file I/O, 518 synthesizable, 75 synthesizable summary, 517 system task and function list, 520 system tasks and functions, 518 three wiring tricks, 519 UDP (primitive), 301 variable, vs. 2001, 517 Verilog A/MS analog block, 539 analogue FF example, 541 analogue functionality, 540 analogue/mixed signal, 538 applicability, 540 benefits, 541 branch, 540 connectmodule, 540 cross operator, 541 discipline, 540 dual-kernel functionality, 540 I operator, 540

11 553 nature, 540 node, 540 operator, 540 (please insert symbol) SPICE allowed, 539 transition operator, 541 two kernels, 539 = VAMS, 539 verilog-a relationship, 539 V operator, 540 VFO. See Variable-frequency oscillator (VFO) VHDL, can use SDC, 520 W wand net type, 233 Watch-dog device, 260 while vs. for, 248 example, 248 header delay, 249 while loop, 247 Width specifier, 17 wire implied names, 232 implied net, 233 net type, 233 other net types, 233 Wired and, 68 Wired or, 68 Wired-or, verilog, 144 wor gate, verilog, 144 wor net type, 233 Wrapper module methodology, 393 X XorNor.v, 20 Z Z state, not in UDP, 302