Digital VLSI Design. Lecture 5: Logic Synthesis

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Digital VLSI Design Lecture 5: Logic Synthesis Semester A, 206-7 Lecturer: Dr. Adam Teman 5 December 206 Disclaimer: This course was prepared, in its entirety, by Adam Teman.

1 Digital VLSI Design Lecture 5: Logic Synthesis Semester A, Lecturer: Dr. Adam Teman 5 December 206 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited; however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed, please feel free to adam.teman@biu.ac.il and I will address this as soon as possible.

2 2 What is Logic Synthesis? Synthesis is the process that converts RTL into a technologyspecific gate-level netlist, optimized for a set of pre-defined constraints. You start with: A behavioral RTL design A standard cell library A set of design constraints You finish with: A gate-level netlist, mapped to the standard cell library (For FPGAs: LUTs, flip-flops, and RAM blocks) Hopefully, it s also efficient in terms of speed, area, power, etc. Standard Cell Design s module counter( input clk, rstn, load, input [:0] in, output reg [:0] out); clk) if (!rstn) out <= 2'b0; else if (load) out <= in; else out <= out + ; endmodule Synthesis module counter ( clk, rstn, load, in, out ); input [:0] in; output [:0] out; input clk, rstn, load; wire N6, N7, n5, n6, n7, n8; HDDFFPQ out_reg_ (.D(N7),.CK(clk),.Q(out[])); HDDFFPQ out_reg_0 (.D(N6),.CK(clk),.Q(out[0])); HDNAN2DL U8 (.A(out[0]),.A2(n5),.Z(n8)); HDNAN2DL U9 (.A(n5),.A2(n7),.Z(n6)); HDINVDL U0 (.A(load),.Z(n5)); HDOA2DL U (.A(in[0]),.A2(n5),.B(rstn),.C(n8),.Z(N6)); HDOA2DL U2 (.A(in[]),.A2(n5),.B(rstn),.C(n6),.Z(N7)); HDEXNOR2DL U3 (.A(out[]),.A2(out[0]),.Z(n7)); endmodule

alphabet Z: Set of internal states λ: X x Z Z (next state function) δ: X x Z Y

3 What is Logic Synthesis? Given: Finite-State Machine F(X,Y,Z, λ, δ) where: X: Input alphabet Y: Output alphabet Z: Set of internal states λ: X x Z Z (next state function) δ: X x Z Y (output function) Target: Circuit C(G, W) where: G: set of circuit components g = {Boolean gates, flip-flops, etc.} W: set of wires connecting G 3

4 Motivation Why perform logic synthesis? Automatically manages many details of the design process: Fewer bugs Improves productivity Abstracts the design data (HDL description) from any particular implementation technology Designs can be re-synthesized targeting different chip technologies; E.g.: first implement in FPGA then later in ASIC In some cases, leads to a more optimal design than could be achieved by manual means (e.g.: logic optimization) Why not logic synthesis? May lead to less than optimal designs in some cases 4

5 Simple Example module foo (a,b,s0,s,f); input [3:0] a; input [3:0] b; input s0,s; output [3:0] f; reg f; (a or b or s0 or s) if (!s0 && s s0) f=a; else f=b; endmodule 5

6 Goals of Logic Synthesis Minimize area in terms of literal count, cell count, register count, etc. Minimize power in terms of switching activity in individual gates, deactivated circuit blocks, etc. Maximize performance in terms of maximal clock frequency of synchronous systems, throughput for asynchronous systems Any combination of the above combined with different weights formulated as a constraint problem minimize area for a clock speed > 300MHz More global objectives feedback from layout actual physical sizes, delays, placement and routing 6

7 How does it work? 7 Variety of general and ad-hoc (special case) methods: Instantiation: maintains a library of primitive modules (AND, OR, etc.) and user defined modules Macro expansion /substitution: a large set of language operators (+, -, Boolean operators, etc.) and constructs (if-else, case) expand into special circuits Inference: special patterns are detected in the language description and treated specially (e.g.,: inferring memory blocks from variable declaration and read/write statements, FSM detection and generation from (posedge clk) blocks) Logic optimization: Boolean operations are grouped and optimized with logic minimization techniques Structural reorganization: advanced techniques including sharing of operators, and retiming of circuits (moving FFs), and others

8 Basic Synthesis Flow Syntax : Read in HDL files and check for syntax errors. read_hdl verilog sourcecode/toplevel.v : Provide standard cells and IP Libraries. set_attribute library /design/data/my_fab/digital/lib/ttv25c.lib Syntax and Binding : Convert RTL into technology-independent generics. State reduction, encoding, register infering. Bind all leaf cells to provided libraries. elaborate toplevel : Reduce Boolean literals. 8

9 9 Basic Synthesis Flow : Define clock frequency and other design constraints. read_sdc sdc/constraints.sdc : Map generic logic to technology libraries. synthesize to_mapped effort medium : Iterate over design, changing gate sizes, Boolean literals, architectural approaches to try and meet constraints. Report final results with an emphasis on timing reports. report timing num paths 0 > reports/timing_reports.rpt Export netlist and other results for further use. write_hdl > /netlist.v Syntax and Binding

10 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax Compilation but aren t we talking about synthesis?

Compilation: Compiler Recognizes all possible constructs in a formally defined program language Translates them to a

11 Compilation in the synthesis flow Before starting to synthesize, we need to check the syntax for correctness. Synthesis vs. Compilation: Compiler Recognizes all possible constructs in a formally defined program language Translates them to a machine language representation of execution process Synthesis Recognizes a target dependent subset of a hardware description language Maps to collection of concrete hardware resources Iterative tool in the design flow Syntax

12 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax 2

13 It s all about the standard cells Well, we discussed quite a bit about standard cell libraries. The library definition stage is tells the synthesizer where to look for leaf cells for binding and the target library for technology mapping. We can provide a list of paths to search for libraries in: set_attribute lib_search_path /design/data/my_fab/digital/lib/ And we have to provide the name of a specific library, usually characterized for a single corner: set_attribute library TTV25C.lib We also need to provide.lib files for IPs, such as memory macros, I/Os, and others. Syntax Make sure you understand all the warnings about the libs that the synthesizer spits out, even though you probably can t fix them. 3

14 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax Boolean Minimzation to Generics and Libs, Basics of Boolean Minimization (BDDs, Two-Level Logic, Espresso) 4

15 During the next step of logic synthesis, the tool: Compiles the RTL into a Boolean data structure (elaboration) Binds the non-boolean modules to leaf cells (binding), and Optimizes the Boolean logic (minimization). The resulting design is mapped to generic, technology independent logic gates. This is the core of synthesis and has been a very central subject of research in computer science since the eighties. Syntax 5

Two-Level Logic B C Syntax During elaboration, primary inputs and outputs (ports) are defined and sequential elements (flip-flops, latches) are inferred.

16 Two-Level Logic B C Syntax During elaboration, primary inputs and outputs (ports) are defined and sequential elements (flip-flops, latches) are inferred. This results in a set of combinational logic clouds with: Input ports and register outputs are inputs to the logic Output ports and register inputs are the outputs of the logic The outputs can be described as Boolean functions of the inputs. The goal of Boolean minimization is to reduce the number of literals in the output functions. Many different data structures are used to represent the Boolean functions: Truth tables, cubes, Binary Decision Diagrams, equations, etc. A lot of the research was developed upon SOP or POS representation, which is better known as Two-Level Logic B D A C D A C D C D A B D A B C F x 3 F f = x x 2 x x 2 6

Two-Level Logic Minimization In our freshman year we learned about Karnaugh maps: For n inputs, the map contains 2 n entries Objective is to find minimum prime cover However Difficult to automate

17 Two-Level Logic Minimization In our freshman year we learned about Karnaugh maps: For n inputs, the map contains 2 n entries Objective is to find minimum prime cover However Difficult to automate (NP-complete) Number of cells is exponential (<6 variables) A different approach is the Quine-McCluskey method Easy to implement in software BUT computational complexity too high Some Berkeley students fell asleep while solving a Quine-McCluskey exercise. They needed a shot of Espresso. AB CD C X X X B A D Syntax 7

18 Espresso Heuristic Minimizer Start with an SOP solution. Expand Make each cube as large as possible without covering a point in the OFF-set. Increases the number of literals (worse solution) Irredundant Throw out redundant cubes. ESPRESSO(F) { do { reduce(f); expand(f); irredundant(f); } while (fewer terms in F); verify(f); } Remove smaller cubes whose points are covered by larger cubes. Reduce The cubes in the cover are reduced in size. In general, the new cover will be different from the initial cover. expand and irredundant steps can possibly find out a new way to cover the points in the ON-set. Hopefully, the new cover will be smaller. Syntax 8

19 9 Espresso Example AB CD CD C C AB D Initial Set of Primes found by Steps and 2 of the Espresso Method 4 primes, irredundant cover, but not a minimal cover! B A B A AB CD CD C D C AB f AC CD AC CD f AC ACD AC ACD D B A B Result of REDUCE: Shrink primes while still covering the ON-set Choice of order in which to perform shrink is important A D Syntax ESPRESSO(F) { do { reduce(f); expand(f); irredundant(f); } while (F smaller); verify(f); }

20 Espresso Example AB CD 00 CD C AB D C 0 Second EXPAND generates a different set of prime implicants B A B A AB CD 00 CD C 00 0 D 0 AB f AC AD AC CD f AC AD CD D C 0 B A IRREDUNDANT COVER found by final step of espresso Only three prime implicants! B A D Only 6 literals! Syntax ESPRESSO(F) { do { reduce(f); expand(f); irredundant(f); } while (F smaller); verify(f); } 20

21 Multi-level Logic Minimization Two-level logic minimization has been widely researched and many famous methods have come out of it. However, often it is better and/or more practical to use many levels of logic (remember logical effort?). Therefore, a whole new optimization regime, known as multi-level logic minimization was developed. We will not cover multi-level minimization in this course, however, you should be aware that the output of logic minimization will generally be multi-level and not twolevel. Syntax 2

22 Multi-level Logic Minimization For example: Given the following logic set: t = a + bc; t 2 = d + e; t 3 = ab + d; t 4 = t t 2 + fg; t 5 = t 4 h + t 2 t 3 ; F = t 5 ; a+bc d+e ab+d t t 2 + fg t 4 h + t 2 t 3 7 Literals t 5 F Syntax Multi-level Logic Minimization can result in: 3 Literals t = d + e; t 2 = b + h; t 3 = at 2 + c; t 4 = t t 3 + fgh; F = t 4 ; d+e b+h at 2 +c t t 3 + fgh t 4 F 22

23 Binary Decision Diagrams (BDD) BDDs are DAGs that represent the truth table of a given function x x 2 x 3 f(x x 2 x 3 ) Root node x f(x,x 2,x 3 ) ~(x 2 x 3 ) x 2 x x 2 2 ~x 3 Syntax ~x x x 3 ~x x x f(x, x 2, x 3 ) = ~x ~x 2 ~x 3 + ~x ~x 2 x 3 + ~x x 2 ~x 3 + x x 2 ~x 3

24 Binary Decision Diagrams (BDD) The Shannon Expansion of a function relates the function to its cofactors: Given a boolean function f(x,x 2,,x i,,x n ) Positive cofactor: f i = f(x,x 2,,,,x n ) Negative cofactor: f i 0 = f(x,x 2,,0,,x n ) Shannon s expansion theorem states that f = x i f i 0 + x i f i f = (x i + f i 0 )(x i + f i ) This leads to the formation of a BDD: Example: b c + bc f = ac + bc + a b c = a (b c + bc) + a (c + bc) = a (b c + bc) + a (c) f a c Syntax 24

25 Reduced Ordered BDD (ROBDD) BDDs can get very big. So let s see if we can provide a reduced representation. Reduction Rule : Merge equivalent leaves a a a ~(x 2 x 3 ) x x 2 x 2 f(x,x 2,x 3 ) x 2 ~x 3 ~(x 2 x 3 ) x x 2 x 2 f(x,x 2,x 3 ) x 2 ~x 3 Syntax ~x 3 ~x 3 x 3 x 3 x 3 x 3 ~x 3 ~x 3 x 3 x 3 x 3 x f(x, x 2, x 3 ) = ~x ~x 2 ~x 3 + ~x ~x 2 x 3 + ~x x 2 ~x 3 + x x 2 ~x 3 = ~x ~x 2 + ~x x 2 ~x 3 + x x 2 ~x 3 25

26 Reduced Ordered BDD (ROBDD) BDDs can get very big. So let s see if we can provide a reduced representation. Reduction Rule 2: Merge isomorphic nodes x y x z x y x z ~(x 2 x 3 ) x x 2 ~x 3 x 2 x 2 f(x,x 2,x 3 ) f(x,x 2,x 3 ) x ~(x 2 x 3 ) x 2 ~x 3 x 2 x 2 Syntax ~x 3 ~x 3 x 3 x 3 x x 3 3 x 3 x 3 x 3 ~x

27 Reduced Ordered BDD (ROBDD) BDDs can get very big. So let s see if we can provide a reduced representation. Reduction Rule 2: Eliminate Redundant Tests x y y ~(x 2 x 3 ) x x 2 x 2 f(x,x 2,x 3 ) x 2 ~x 3 ~(x 2 x 3 ) x x 2 x 2 f(x,x 2,x 3 ) x 2 ~x 3 Syntax f(x, x 2, x 3 ) = ~x ~x 2 + x 3 ~x 3 x 3 x 3 x 3 ~x 3 ~x x 2 ~x 3 + x x 2 ~x

28 Syntax Binary Decision Diagrams (BDD) Some benefits of BDDs: Check for tautology is trivial. BDD is a constant. Complementation. Given a BDD for a function f, the BDD for f can be obtained by interchanging the terminal nodes. Equivalence check. Two functions f and g are equivalent if their BDDs (under the same variable ordering) are the same. c f = ab+a c+a bd c+bd c root node b c+d c a b b An Important Point: The size of a BDD can vary drastically if the order in which the variables are expanded is changed. The number of nodes in the BDD can be exponential in the number of variables in the worst case, even after reduction d d 0 28

29 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax 29

30 Syntax Following, the design is loaded into the synthesis tool and stored inside a data structure. Hierarchical ports (inputs/outputs) and registers can be accessed by name. set in_ports [get_ports IN*] set regs [get_cells hier *_reg] At this point, we can load the design constraints in SDC format, as we learned in the previous lecture. read_sdc verbose sdc/constraints.sdc Carefully check that all constraints were accepted by the tool! 30

31 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax 3

32 mapping mapping is the phase of logic synthesis when gates are selected from a technology library to implement the circuit. Why technology mapping? Straight implementation may not be good. For example, F=abcdef as a 6-input AND gate causes a long delay. Gates in the library are pre-designed, they are usually optimized in terms of area, delay, power, etc. Fastest gates along the critical path, area-efficient gates (combination) off the critical path. Can apply a minimum cost tree-covering algorithm to solve this problem. Syntax 32

33 Syntax Algorithm Using a recursive tree-covering algorithm, we can easily, and almost optimally, map a logic network to a technology library. This process incurs three steps: Map netlist and tech library to simple gates Describe the netlist with only NAND2 and NOT gates Describe SC library with NAND2 and NOT gates and associate a cost with each gate Tree-ifying the input netlist Tree covering can only be applied to trees! Split tree at all places, where fanout > 2 Minimum Cost Tree matching For each node in your tree, recursively find the minimum cost target pattern at that node. Let us briefly go through these steps 33

34 Syntax. Simple Gate Apply De Morgan laws to your Boolean function to make it a collection of NAND2 and NOT gates. Let s take the example of multi-level logic minimization: 34 t = d + e; t 2 = b + h; t 3 = at 2 + c; t 4 = t t 3 + fgh; F = t 4 ; 2 t d e NAND d, e t b h NAND b, h t at c at c NAND NAND a, t, c t t t fgh NAND t t, fgh fgh fh g fh g NAND NAND f, h, g F t 4 f g d e h b a c t 2 t t 3 fgh F

35 . Simple Gate And then, given a set of gates (standard cell library) with cost metrics (area/delay/power): We need to define the gates with the same NAND2/NOT set: Syntax inv() nand2(2) nand3 (3) aoi2 (3) oai22 (4) nor2(2) nor3 (3) xor (5) 35

36 2. Tree-ifying To apply a tree covering algorithm, we must work on a tree! Is any given logic network a tree? No! We must break the tree at any node with fanout>2 Syntax We get 3 trees 36

37 3. Minimum Tree Covering Now, we can apply a recursive algorithm to achieve a minimum cover: Start at the output of the graph. For each node, find all the matching target patterns. The cost of node i for using gate g is: where k i are the inputs to gate g. For simplicity, we will redraw our graph and show an example: Every NOT is just an empty circle: Every AND is just a full circle: Every input is just a box: i k gi ki cost min cost cost A N I k g i i k k 2 k inputs to g i Syntax 37

38 3. Minimum Tree Covering - Example F AOI2 I y I N f w N z f: NOT 2 + min(w) = 2 + = 3 AND2 4 + min(y)+min(z) = = 2 AOI2 6 + min(x) = = 9 w: NAND2 3 + min(y)+min(z) = = y: NOT 2 z: NAND2 3 + min(x) = = 6 x: NAND2 3 Syntax NAND2 A B C D A B C N x D I N N 2 3 I 4 I N I I 6 I N I I 6 38 NOT NAND2 AND2 NOR2 AOI2

39 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Verilog for Synthesis - revisited 39

Some things we may have missed Now that we ve seen how synthesis works, let s revisit some of the things we may have skipped or only briefly mentioned earlier Let s take a simple 4 2 encoder as an

40 Some things we may have missed Now that we ve seen how synthesis works, let s revisit some of the things we may have skipped or only briefly mentioned earlier Let s take a simple 4 2 encoder as an example: Take a one-hot encoded vector and output the position of the bit. One possibility would be to describe this logic with a nested if-else block: begin : encode if (x == 4'b000) y = 2'b00; else if (x == 4'b000) y = 2'b0; else if (x == 4'b000) y = 2'b0; else if (x == 4'b000) y = 2'b; else y = 2'bxx; end 40 The result is known as priority logic i.e., some bits have priority over others

Some things we may have missed It would have been better

parallel and better yet, synthesis can optimize away the

: encode case (x) 4 b000: y = 2'b00; 4 b000: y = 2'b0;

41 Some things we may have missed It would have been better to use a case construct: all cases are matched in parallel and better yet, synthesis can optimize away the constants and other Boolean equalities: begin : encode case (x) 4 b000: y = 2'b00; 4 b000: y = 2'b0; 4'b000: y = 2'b0; 4'b000: y = 2'b; default: y = 2'bxx; endcase end 4

Some things we may have missed In the previous example, if the encoding was wrong (i.e., not one-hot), we would have propagated an x in the logic simulation.

42 Some things we may have missed In the previous example, if the encoding was wrong (i.e., not one-hot), we would have propagated an x in the logic simulation. But what if we guarantee that the input was one hot encoded? Then we could write our code differently begin : encode if (x[0]) y = 2'b00; else if (x[]) y = 2'b0; else if (x[2]) y = 2'b0; else if (x[3]) y = 2'b; else y = 2'bxx; end In fact, we have implemented a priority decoder (the least significant gets priority) 42

43 A few points about operators Logical operators map into primitive logic gates Arithmetic operators map into adders, subtractors, Unsigned 2 s complement Model carry: target is one-bit wider that source Watch out for *, %, and / Relational operators generate comparators Shifts by constant amount are just wire connections No logic involved Variable shift amounts a whole different story shifter Conditional expression generates logic or MUX Y = ~X << 2 X[3] X[2] X[] X[0] Y[5] Y[4] Y[3] Y[2] Y[] Y[0] 43

44 Datapath Synthesis Complex operators (Adders, Multipliers, etc.) are implemented in a special way Pre-written descriptions can be found in Synopsys DesignWare or Cadence ChipWare IP libraries. 44

45 Global Clock Gating Clock Gating enf FSM As you know, since a clock is continuously toggling, it is a major consumer of dynamic power. Therefore, in order to save power, we will try to turn off the clock for gates that are not in use. Block level (Global) clock-gating If certain operating modes do not use an entire module/component, a clock gate should be defined in the RTL. Register level (Local) clock-gating However, even at the register level, if a flip-flop doesn t change it s output, internal power is still dissipated due to the clock toggling. This is very typical of an enabled signal sampling, and therefore can be automatically detected and gated by the synthesis tool. din en clk d clk ene enm clk Local Clock Gating q qn dout din en clk Execution Unit Memory Control d clk q qn dout 45

46 Clock Gating Local clock gating: 3 methods Logic synthesizer finds and implements local gating opportunities RTL code explicitly specifies clock gating Clock gating cell explicitly instantiated in RTL Global clock gating: 2 methods RTL code explicitly specifies clock gating Clock gating cell explicitly instantiated in RTL Conventional RTL Code //always clock the register (posedge clk) begin if (enable) q <= din; end Low Power Clock Gated RTL >< //only clock the ff when enable is true assign gclk = enable && clk; (posedge gclk) begin q <= din; end Instantiated Clock Gating Cell //instantiate a clock gating cell clkgx i (.en(enable),.cp(clk),.gclk_out(gclk)); (posedge gclk) begin q <= din; end 46

47 Clock Gating Glitch Problem What happens if there is a glitch on the enable signal? clk en gclk What if the glitch happened during the high phase? Ah, we live in a perfect world! Not so Fast! Maybe the world aint so perfect after all 47

48 Solution: Glitch-free Clock Gate By latching the enable signal during the positive phase, we can eliminate glitches: clk en en_out //clock gating with glitch prevention latch (enable or clk) begin if (!clk) en_out <= enable end assign gclk = en_out && clk; gclk 48

49 Merging clock enable gates Clock gates with common enable can be merged Lower clock tree power, fewer gates May impact enable signal timing and skew. E clk E E clk en E enable E 49

assign add_out = A+B; assign shift_out = A<<B; assign out = shift_add?

50 Data Gating While clock gating is very well understood and automated, a similar situation occurs due to the toggling of data signals that are not used. These situations should be recognized and data gated. assign add_out = A+B; assign shift_out = A<<B; assign out = shift_add? shift_out : add_out; 50 assign shift_in_a = A && shift_add; assign shift_in_b = B && shift_add; assign shift_out = shift_in_a << shift_in_b; assign out = shift_add? shift_out : add_out;

Design and Verification HDL Linting 5 HDL Linting tools provide a quick easy check of likely coding inconsistencies: Simulation problems Synthesis Problems Simulation Synthesis mismatches Clock

51 Design and Verification HDL Linting 5 HDL Linting tools provide a quick easy check of likely coding inconsistencies: Simulation problems Synthesis Problems Simulation Synthesis mismatches Clock gating Latch inference Clock Domain Crossing issues Nonsensical assignments / implicit bit widths issues Not for checking syntactic correctness Use your simulator for that. (Will generally be more helpful) Alternatively some synthesis tools will give you basic lint warnings For simulation-synthesis mismatch errors Simulation/Synthesis Miss-matches z = a & b; Latch Inference or b or c) if (c) z = a & b; Clock Gating assign clka = clk & cond; clka) z <= a & b;

52 Intro 2 Compile 3 Lib. Def. 4 Boolean Min 5 SDC 6 Tech. 7 Verilog for Synt. 8 Opt. Syntax Timing 52

53 How can we optimize timing? There are many transforms that the synthesizer applies to the logic to improve the cost function: Resize cells Buffer or clone to reduce load on critical nets Decompose large cells Swap connections on commutative pins or among equivalent nets Move critical signals forward Pad early paths Area recovery Simple example: Double inverter removal transform: Delay = 4 Delay = 2 53

54 54 Resizing, Cloning and Buffering Resize a logic gate to better drive a load: a b Or make a copy (clone of the gate) to distribute the load: a b?? Or just buffer the fanout net: d e f d e f g h a b a b A A B a b d e f g h B a b 0. B C d e d f g h load A B C

55 Redesign Fan-In/Fan-out Trees Redesign Fan-In Tree Arr(a)=4 a Arr(b)=3 b Arr(c)= c Arr(d)=0 d e c Arr(e)=6 d b a e Arr(e)=5 Redesign Fan-Out Tree 3 3 Longest Path = 4 Slowdown of buffer due to load 2 Longest Path = 5 55

56 Decomposition and Swapping Consider decomposing complex gates into less complex ones: Swap commutative pins: Simple sorting on arrival times and delays can help 0 2 c b a a b c

57 Retiming Given the following network: FF D Q FF D Q FF D Q clock Cycle = 0 How would you meet the 0ns clock cycle time? Re-order sequential elements and combinational logic FF FF FF D Q D Q D Q 57 clock Cycle = 0

58 A last point: Topographical Synthesis Also called Physical Aware Synthesis 58

59 Main References Rob Rutenbar From Logic to Layout IDESA Rabaey, Low Power Design Essentials vlsicad.ucsd.edu ECE 260B CSE 24A Roy Shor, BGU Synopsys slides 59

Lecture Outline. Adam Teman, 2018

Lecture Outline. Adam Teman, 2018 Lecture Outline Adam Teman, 208 Digital VLSI Design Lecture 4: Logic Synthesis Part 2 Semester A, 208-9 Lecturer: Dr. Adam Teman November 6, 208 Disclaimer: This course was prepared, in its entirety, by