WINTER 14 EXAMINATION Subject Code: Model Answer Page No: / N

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1 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate may vary but the examiner may try to assess the understanding level of the candidate. 3) The language errors such as grammatical, spelling errors should not be given more Importance (Not applicable for subject English and Communication Skills. 4) While assessing figures, examiner may give credit for principal components indicated in the figure. The figures drawn by candidate and model answer may vary. The examiner may give credit for any equivalent figure drawn. 5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may vary and there may be some difference in the candidate s answers and model answer. 6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept. 1. (A) Attempt any THREE of the following : 12 Marks (a) Give the IC classification according to (i) (ii) (iii) (iv) Circuit technology Design style Design type Circuit size (If answer reflects any classification marks to be awarded, 1 M for Each classification) i. Small sca1e integration (SSI) < 10 components ii. Medium Scale integration (MSI) < 100 components 1

2 iii. Large Scale integration (LSI)> 100 components iv. Very Large Scale Integration (VLSI)> 1000 components OR (i) Circuit technology Unipolar /Bipolar (v) Design style Monolithic/Hybrid (vi) Design type Bipolar :Saturated/Non Saturated Unipolar :CMOS/PMOS/NMOS (vii) Circuit size Small sca1e integration (SSI) < 10 components Medium Scale integration (MSI) < 100 components Large Scale integration (LSI)> 100 components Very Large Scale Integration (VLSI)> 1000 components b. Write the Purpose and material used for following process : (any two) Ans) (1 M Each) Process Purpose Material OXIDATION The oxidation is required for fabrication for isolating the different layers of conducting materials and to prevent unwanted conduction path. OR IC relies on the properties of oxides of silicon i.e. silicon dioxide. Hence oxidation is necessary to form Silicon dioxide(sio2) Silicon 2

3 DIFFUSION The process of junction formation, that is transition from p to n type or vice versa. P type : Borane(B 2 H 6 ) Diffusion of impurity atoms into silicon crystal takes place N type: Phosphine(PH 3) only at elevated temperature, typically 900 to 1100 C. ION IMPLANTATION Is Used to produce a shallow surface region of dopant atoms deposited into a silicon wafer. It is an alternative process to diffusion. Dopant atoms are vaporized, accelerated and directed at silicon substrate. P type : Borane(B 2 H 6 ) N type: Phosphine(PH 3) c. Draw the CMOS inverter circuit diagram and layout ( Diagram 4 Marks) Note:- The layout of CMOS as follows Figure: CMOS inverter circuit diagram 3

4 (d) Write the VHDL code for 4-bit added without component or instantiation. (ENTITY 1 M, Architecture 3 M) LIBRARY IEEE; Use ieee.std_logic_1164.all; Entity full_add_4 is Port(a,b:in std logic _vector(3 downto 0); s:out std_logic_vector (3 downto 0); cout:out std_logic; cin:in std_logic); End full_add_4; Architecture dataflow of full_add_4 is Signal y:std_logic_vector(2 downto 0); BEGIN S(0)<= A(0) XOR B(0) XOR Cin; Y(0)<= (A(0) AND B(0)) OR (A(0) AND Cin) OR (B(0) AND Cin) S(1)<= A(1) XOR B(1) XOR Y(0); Y(1)<= (A(1) AND B(1)) OR (A(1) AND Y(0)) OR (Y(0) AND B(1)); S(2)<= A(2) XOR B(2) XOR Y(1); Y(2)<= (A(2) AND B(2)) OR (A(2) AND Y(1)) OR (Y(1) AND B(2)); S(3)<= A(3) XOR B(3) XOR Y(2); Cout<=(A(3) AND B(3)) OR (A(3) AND Y(2)) OR (Y(2) AND B(3)); End dataflow; 4

5 (B) Attempt any ONE of the following : (a)write the possible values of y For (i) y :OUT BIT; (ii) y :OUT std-logic; (iii)y :OUT integer range 0 to 7 i. 0/1 ( 1Mark) ii. 0 / 1 / U / X / Z / W / L / H / - (Z : high impedance,w; weak unknown,l: weak low H: weak high,-; don care ( any four 4 mark) iii. 0-7 ( 1mark) (b) Explain any four characteristics of any one FPGA. Write one FPGA and CPLD chip name of Xilinx and Atmel. (4 marks and for any valid name of Xilinx: 1 mark, name of Atmel 1 mark) Very high density Generally lower power SRAM devices are reprogrammable ,000 gates Application dependent Very high shift frequencies SRAM-based devices and some EEPROM-based devices All anti-fuse-based devices Very low static Dynamic consumption is application dependent, 0.1-2W typical Field programmable gate array 5

6 Gates more than 10,000 Complex architecture More resister Volatile higher I/O count Flexible routing. Name of FPGA : Xilinx XC 4000 family ATMEL FPGA : AT40K05/K10/K20/K40 Atmel CPLD : CPLD ATF 750,ATF 2500C ATF 15 XX Xilinx : CPLD XC9500 series Q.2 Attempt any FOUR of the following: 6 Marks a) Define- (i) Synthesis (ii) Functional simulator (iii) Timing simulator and (iv) Chip configuration or programming (1 M Each) (i) Synthesis: Synthesis is an automatic method of converting a higher level of abstraction to lower level of abstraction. (ii) Functional simulator: It just checks whether the circuit gives the proper output. Hence it is a functional verification of the design without any delays. Functional Verification of the entity (iii) Timing Simulator: It allows you to check that the implemented design meets all timing requirements and behaves as you expect in the device.: To verify the post synthesis verification for time constraint (iv) Chip configuration or programming: It is a process where you can configure your device, create PROM, System ACE solution, SVF, XSVF, or STAPL files. 6

7 b) List four features of verilog. Write the verilog program architechture for 2- I/P AND gate. (2 marks for listing any 4-features and 2 marks for program) Features of Verilog: (Any 4 points) A general-purpose HDL Easy to learn and use Syntax is similar to C (VHDL is similar to PASCAL) Allows different levels of abstraction to be mixed in the same model In terms of switches, gates, RTL, or behavioral code Need to learn only for stimulus and hierarchical design Most popular logic synthesis tools support Verilog Rich of Verilog HDL libraries Provided by fabrication vendors for postlogic synthesis simulation Allows the widest choice of vendors while designing a chip With powerful PLI (Programming Language Interface) Write custom C code to interact with internal data structure Verilog program architecture for 2- I/P AND gate. module and1(c,a,b); output c; input a,b; assign c=a&b; endmodule c) Define FSM, Moore machine and Mealy machine. Draw the diagram of moore the machine. (Definitions 3 marks each and diagram of moore 1 mark) FSM: A Finite-state machine is defined as; a sequential circuit that has some practical bounds governing the number of different conditions (STATES) in which sequential machine can reside. Moore Machine: Moore machine is the sequential system where output depends only on present state. f (o/p) = f (Present State) Mealy Machine: Mealy machine is the sequential system where output depends on present input and state. f (o/p) = f (i/p, Present State) Diagram: 7

8 d) Draw the EX-OR gate circuit using CMOS. Solution: Ex-OR gate Boolean equation ; Moore machine Figure: diagram of moore the machine. e) Compare signals and variable. (Any four points 1M Each) 8

9 Sr. No Signals Variables Signal objects are used to connect entities together to form models Signals have their values scheduled in the future The keyword signal is followed by one or more signal names Signals can be declared in entity declaration sections architecture declarations and package declarations Signals need more information so more memory Variables are used for local storage in process statements and subprograms. Variables have all assignments to variables occur immediately The keyword variable is followed by one or more variable names Variables can be declared in the process declaration and subprogram declaration sections only. Variables take less memory f) Draw the diagrams for latch-up in CMOS. List how to prevent this. (Diagrams 2 M and prevention 2 M) Diagram: Figure: Latchup diagram How to prevent latch up: (any 4 points) 1. Increase the doping of well and substrate 2. Increase the depth of the well region. 3. Increase the spacing of NMOS / PMOS devices. 4. The source / well contact must be kept nearly to reduce series resistance, 5. Place a substrate contact for every 5-10 transistors, 6. Layout of n and p transistors with packing of n devices towards gnd and p devices toward V DD. 7. Using gold doping in the well region of substrate region. 9

10 8. To avoid undesirable parasitic 9. Guard Rings / channel stops: Additional heavy diffusion region may be same type of material as of substrate or well. 10. Reduce gain: add thin epitaxy layer over substrate. Q 3. Attempt any FOUR of the following: 16 Marks (a) List the methods of CMOS fabrication. What is dynamic power dissipation in CMOS? List the ways to reduce dynamic power dissipation in CMOS. ( Any 4 methods -2 M) The methods for CMOS fabrication are as follows : 1. P-Well 2. N well 3. Twin tub process 4. Silicon on insulator Dynamic power dissipation : ( 1 Mark) Defined as the power dissipated due to 1) Charging and discharging of load capacitances. 2) Short circuit between PMOS and NMOS networks while both are partially ON The ways to reduce dynamic power dissipation in CMOS are : (1 Mark) It depends upon power supply VDD, frequency F and capacitance C. Pavg= C L *VDD 2 *f p By using Minimum size devices. By Reducing supply voltage, Switched capacitance, frequency (b) Explain the architecture of SPARTAN-3 series (any one) with block diagram. (2 M Diagram, 2 M Explanation) 10

11 Generalized Block Diagram of FPGA A field programmable gate array (FPGA) is like a CPLD turned inside out. The logic is broken into a large number of programmable logic blocks that are individually smaller than a PLD. They are distributed across the entire chip in a sea of programmable interconnections, and the entire array is surrounded by programmable I/O blocks. An FPGA s programmable logic block is less capable than a typical PLD but an FPGA chip contains a lot more logic blocks than a CPLD of the same die size has PLDs. (c) Write the tool name in Xilinx-ISE for any two of the following i. compiler ii. simulator iii. implementation-fpga iv. device configuration/program v. pin-out and area constraint editor ( 2 M For any 2) i. compiler- Compxlib ii. simulator- ISim iii. implementation-fpga - NGDBuild iv. device configuration/program implementation v. pin-out and area constraint editor- constraint editor /ISEtext editor/pace/floor plan editor. ( any one) 11

12 (d) Describe the following: (any two) i..pcf file ii..bit file iii..ngd file (Any 2 Description, 2 M Each) i. pcf file - The Physical Constraints (PCF) file contains all the constraints on the design expressed in terms of physical entities. Timing constraints are a subset of the constraints in the PCF. A PCF is automatically generated from the UCF by MAP. ii. bit file File generated by Bit Gen, a program used for generating bit streams required by Xilinx FPGAs (field-programmable gate arrays); saved in a binary format and contains the configuration information for the circuit; used for uploading the configuration data to the FPGA device, which can be completed using the impact GUI provided with the Xilinx software. iii. NGD file- The Logical Design (NGD) file is an optional file which is used for cross probing to the Constraints Editor. The Timing Wizard Report (TWR) is an ASCII report containing timing analysis results e) Compare if statement and case statement. ( Each Explanation 2 M,, it can be in tabular form also with 4 points of comparison) The IF statement is used to conditionally execute a statement or a block of statements. The syntax of the IF statement is as follows: IF expression THEN statement [ ELSE statement ] OR IF expression THEN BEGIN statements ENDIF [ ELSE BEGIN statements ENDELSE ] CASE The CASE statement is used to select one, and only one, statement for execution, depending upon the value of the expression following the word CASE. This expression is called the case selector expression. The general form of the CASE statement is as follows: 12

13 CASE expression OF expression: statement... expression: statement [ELSE: statement] ENDCASE Each statement that is part of a CASE statement is preceded by an expression that is compared to the value of the selector expression. CASE executes by comparing the CASE expression with each selector expression in the order written. If a match is found, the statement is executed and control resumes directly below the CASE statement. The ELSE clause of the CASE statement is optional. If included, it matches any selector expression, causing its code to be executed. For this reason, it is usually written as the last clause in the CASE statement. The ELSE statement is executed only if none of the preceding statement expressions match. If an ELSE clause is not included and none of the values match the selector, an error occurs and program execution stops. The BREAK statement can be used within CASE statements to force an immediate exit from the CASE. f) Write the program for 4:1 MUX using if-else if statement. (4 M) (VHDL or Verilog program) Verilog Program module multiplexer4_1 ( din,sel,dout ); output dout ; reg dout ; input [3:0] din ; wire [3:0] din ; input [1:0] sel ; wire [1:0] sel ; (din or sel) begin if (sel==0) dout = din[3]; else if (sel==1) dout = din[2]; else if (sel==2) dout = din[1]; else dout = din[0]; 13

14 end endmodule OR VHDL Program Q4. (A) Attempt any THREE of the following: 12 Marks (a) Why a polysilicon gate is preferred over metal gate in VLSI? Why silicon (Si) is used instead of germanium (Ge) in VLSI? ( 2 Reasons 2 M) Polysilicon gate is preferred over metal gate in VLSI ( 2 reasons 2 M) Long polysilicon wires have distributed series R and C for cascaded pass transistors due to which the signal propagation is slowed down. But with metal wires,the signal propagation will be more slower due to value of capacitor C I\becomes very high. So due to polysilicon wires 1) The speed increases 2) The sensitivity to noise also reduces Silicon (Si) is used instead of germanium (Ge) in VLSI ( 2 points 2 mks) 1.Si devices can operate upto 150 degree celcius as compared to 100 degrees for Ge 2. Si grows a stable oxide SiO2 which is important in the fabrication of ICs as 14

15 compared to Ge oxide which is unsuited. 3. Ge is costly than Si. 4. Ge is difficult to dope as compared to Si. Ge is more sensitive for temp Ge has low Vknee voltage (b) Write the stable table and draw the state diagram for a synchronous counter whose o/p drives stepper motor. - The following schematic shows the different blocks in a circuit to drive a unipolar stepper motor. The 2 blocks are 1) 2 bit synchronous counter - Inputs are D (direction) and CLK. D will determine the direction of rotation and the CLK frequency will set the rotation speed. 2) Motor Driver circuit and Unipolar Stepper Motor - the Motor Driver circuit translate the Q A and Q B digital signals to appropriate drive currents required by the stepper motor. A common stepper motor is the four-coil unipolar. They are called unipolar because they require only that their coils be driven on and off. ( 1 M) State table Figure: State diagram for a synchronous counter ( 1 M) The following state diagram describes the stepper motor sequence. ( 1 M) 15

16 Stable table- ( 1 M) (c) Draw the following signal x for the statement (i) y= transport X after 5 ns; (ii) z= X after 6ns; (4 M) (d) What is FPGA? Explain. (2 M Diagram,2 M Explanation) A field programmable gate array (FPGA) has large number of programmable logic blocks that are individually smaller than a PLD. the basic structure of a FPGA is shown in the fig. below: 16

17 Figure: General block diagram of FPGA chipset. The programmable logic blocks are arranged in the matrix form with programmable interconnections and the entire array is surrounded by programmable I/O blocks. Each logic block is less capable than a typical PLD, but it has lot more logic blocks than a CPLD of same size. (B) Attempt any ONE of the following: 6 Marks (a) Draw (i) NAND gate using NMOS logic. (ii) AND gate using CMOS logic. (3 marks for NAND gate and 3 marks for AND gate) NMOS NAND gate (any one diagram out of 3 will do) AND gate using CMOS logic : 17

18 (b) (i) write the VHDL code to implement 4:1 MUX using with select statement - ( 1 mark) library IEEE; use IEEE.std_logic_1164.all; entity MUX4_1 is port (A: in Std logic_vector (3 down to 0) S:in std_logic_vector (1 down to 0) Y:out std_logict); end MUX4_1; architecture MUX_body of MUX4_1 is begin with S select Y<= A(0) when 00, 18

19 A(1) when 01, A(2) when 10, A(3) when 11, 0 when others ;-- optional end MUX_body; (2 Mark) (ii) Draw the design flow for Xilinx software or CAD/EDA software. ( 3 M for proper diagram) Figure: Design flow for Xilinx software 19

20 Q 5. Attempt any FOUR of the following : (a) List the parameters of which threshold voltage is a function.comment on W/L ratio 16 Marks (parameters 2M, comment on W/L 2M) Parameters Work function difference between the gate and the channel The gate voltage to change surface potential The gate voltage to offset depletion region charge The voltage component to offset the fixed charges in the gate oxide and in the silicon oxide interface W/L Ratio W: width of the channel L :; length of the channel The β is the mos transistor gain factor which depends on process parameter and geometry of the device. The W/L ratio is nothing but the geometry of the device. Which actually depend on the dimension of the layout. b. Write any two parameters each,which are enhanced and reduced with VLSI technology. (Any 2 parameters -2 M Each) c. Draw the CMOS transistor logic circuit for f = X 1 + X 2. X 3. (CMOS based circuit for NAND- 4 marks) Diagram: 20

21 Figure: CMOS transistor logic circuit d. Write the VHDL code for MOD-5 counter. Ans : ( The below is a MOD 5 counter, 4marks to be awarded for any other design too) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk : in std_logic; reset : in std_logic Q : out std_logic_vector(2 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(2 downto 0); begin process (Clk) begin if reset= 1 then tmp<= 000 ; end if; if (Clk event and Clk= 1 ) then if (tmp< 100 ) then tmp <= tmp + 1; else tmp<= 000 ; end if; end if; end process; 21

22 Q <= tmp; end archi; e. Which element /array is programmable in (i)pla (ii)pal (iii)cpld (iv)fpga ( 4 marks to be awarded to any 4 correct answers) Device AND Array OR Array PROM Fixed Programmable PLA Programmable Programmable PAL Programmable Fixed CPLD FPGA Functional Blocks Configurable Logic Blocks f. Compare Moore and Melay machine. (1 mark for each difference) Mealy Machine Moore Machine In a Mealy machine the output depends on the present state and present set of inputs In a Moore machine the output depends on the present state only. 22

23 Number of states required in the design of a Mealy is less in comparison to a Moore machine. Number of states required in the design of a Moore is more in comparison to a Mealy machine. Next state = F (Current state, input) Output = G (Current state, input) In a state diagram the output is represented on the transition along with input. Mealy machines are slow in comparison to a Moore Machine. Next state = F (Current state, input) Output = G (Current state) In a state diagram the output is represented in the state itself. Moore machines are faster in comparison to a Mealy Machine. Q. 6 Attempt any FOUR of the following: 16 Marks a) Write the temperature of any two process in C-Z method (or IC fabrication)- i) CVD process ii) Epitaxial growth iii) Silicon ingot formation (Any two, 2 marks each) i) CVD process ~ C C ii) Epitaxial growth ~ >800 0 C iii) Silicon ingot formation ~ C C 23

24 b) Write the etching material for any twoi) SiO2 ii) Poly-Silicon iii) Metal i) SiO2 HF Acid (Chemical etch) or plasma etch (dry etch) ii) Poly-Silicon- He / O2 iii) Metal- Chlorine or Bromine (Any two, 2 marks each) c) Write the VHDL code for a one digit BCD adder. (4 M) entity BCDadder is Port ( bcd1 : in std_logic_vector(3 downto 0); bcd2 : in std_logic_vector(3 downto 0); bcdcarryin : in std_logic; bcdsum : out std_logic_vector(3 downto 0); bcdcarryout : out std_logic); end BCDadder; architecture Behavioral of BCDadder is component adder4bit is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); carryin : in std_logic; sum : out std_logic_vector(3 downto 0); carryout : out std_logic); end component adder4bit; signal s,x: std_logic_vector(3 Downto 0); signal c,k : std_logic; begin u1:adder4bit port map(a(3)=>bcd1(3),a(2)=>bcd1(2),a(1)=>bcd1(1),a(0)=>bcd1(0), b(3)=>bcd2(3),b(2)=>bcd2(2),b(1)=>bcd2(1),b(0)=>bcd2(0), carryin=>bcdcarryin,sum(3)=>s(3),sum(2)=>s(2),sum(1)=>s(1),sum(0)=>s(0),carryout=>c); K <= (s(3)and s(2))or(s(3)and s(1))or(c); x <= "0110" when k ='1' else "0000"; u2 :adder4bit port map(a(3)=>s(3),a(2)=>s(2),a(1)=>s(1),a(0)=>s(0),b(3)=>x(3),b(2)=>x(2),b(1)=>x(1),b(0)=>x(0),carryin=>'0', sum(3)=>bcdsum(3),sum(2)=>bcdsum(2),sum(1)=>bcdsum(1),sum(0)=>bcdsum(0), carryout=>bcdcarryout); end Behavioral; 24

25 d) Why polysilicon gate is used instead of metal gate? (any 4 points 1 marks each) Fabrication processes after the initial doping required very high temperature annealing. Metal gates would melt under such conditions whereas polysilicon would not. Using polysilicon allowed for a one-step process of etching the gates compared to elaborate multisteps that we see today in metal-gate processes. Threshold voltage of the MOSFET inversion layer is correlated with the work-function difference between the gate and the channel. Using metal would result in a higher Vt compared to polysilicon since a polysilicon gate would be of the same or similar material composition as the bulk silicon channel. Conductivity is high in polysilicon gate compared to metal gate. e) What is hot electron effect? How to reduce it? (2 M for explanation 2 M for reduction) In MOSFETs, hot electron have sufficient energy to tunnel through the thin oxide gate to show up as gate current, or as a substrate leakage current. The hot electrons may jump from the channel region or from the drain for instance and into the gate or the substrate. These high energy electrons can enter the oxide where they can be trapped, giving rise to oxide charging that can accumulate with time and degrade the device performance by increasing VTO and affect adversely the gate s control on the drain current. When electrons are accelerated in the channel, they gain energy along the mean free path. How it is reduced: It is reduced by running lower supply at longer channel, "drain engineering" to stand off field at greater distance from the gate / spacer, better quality oxides that have fewer traps, circuit design that avoids peak HCE stress or transitions through that region as quickly and infrequently as possible (every switching event in digital spends a tiny slice of time in that region; analog might camp out, which would be bad). 25

26 f) Compare CPLD & FPGA. (any 4 points 1 marks each) Sr. FPGA CPLD No. 1 It is field programmable gate arrays. It is complex programmable logic device. 2 Capacity is defined in terms of number of gates available. Capacity is defined in terms of number of macro-cells available. 3 FPGA consumes less power than CPLD CPLD consumes more power than FPGA devices. 4 Numbers of input and output pins on FPGA are less than CPLD. Numbers of input and output pins on CPLD are high. 5 FPGA is suitable for designs with large number of simple blocks with few CPLD are ideal for complex blocks with large number of inputs. numbers of inputs. 6 FPGA based designs require more board space and layout complexity is more. CPLD based designs need less board space and less board layout complexity. 7 It is difficult to predict the speed performance of design. It is easier to predict speed performance of design. 8. FPGA are available in wide density range. CPLDs contain fewer registers but have better performance. 26