Verilog HDL:Digital Design and Modeling. Chapter 3. Keywords

Transcription

1 Chapter 3 Keywords 1 Verilog HDL:Digital Design and Modeling Chapter 3 Keywords

2 Chapter 3 Keywords 2 Page 80 //4:1 multiplexer using a //case statement module mux_4_1_case (sel, data, out); input [1:0] sel; input [3:0] data; output out; reg out; (sel or data) case (sel) (0) : out = data[0]; (1) : out = data[1]; (2) : out = data[2]; (3) : out = data[3]; case module Figure 3.3 Multiplexer design using a case statement. Page 81 //example of defparam module def_param1; parameter x1 = 0; $display ("value=%d", x1); module value = 8 value = 4 value = 0 (a) (c) //define top level module //for defparam1 module top_level; defparam value1.x1 = 4; defparam value2.x1 = 8; def_param1 value1 ( ); def_param1 value2 ( ); module (b) Figure 3.4 Verilog code to illustrate the use of the defparam keyword: (a) parameter keyword, (b) defparam keyword to change the value, and (c) the outputs.

3 Chapter 3 Keywords 3 Page 86 //example of the repeat keyword module repeat_example; integer count; count = 0; repeat (8) $display ("count = %d", count); count = count + 1; module Figure 3.5 Example of the repeat keyword for loop control. count = 0 count = 1 count = 2 count = 3 count = 4 count = 5 count = 6 count = 7 Figure 3.6 Outputs for the Verilog code of Figure 3.5.

4 Chapter 3 Keywords 4 Page 88 //illustrates the use of the while statement module while_example; integer count; count = 0; while (count < 16) $display ("count = %d", count); count = count + 1; module Figure 3.7 Example of the while keyword for loop control. Page 89 count = 0 count = 1 count = 2 count = 3 count = 4 count = 5 count = 6 count = 7 count = 8 count = 9 count = 10 count = 11 count = 12 count = 13 count = 14 count = 15 Figure 3.8 Outputs for the Verilog code of Figure 3.7.

5 Chapter 3 Keywords 5 Page 91 //example of specify block with delays module specify_block (x1, x2, z1); input x1, x2; output z1; nor (z1, x1, x2); specify specparam tplh = 0.55 : 0.90 : 1.20, tphl = 0.50 : 0.70 : 1.55; //min : typ : max specify (x1 => z1) = tplh, tphl; (x2 => z1) = tplh, tphl; module Figure 3.10 Example of a specify block. Page 96 //used-defined primitive for a 2-input OR gate primitive udp_or2 (out, a, b); //list output first //declarations output out; input a, b; //must be output (not reg) //for comb logic //state table definition table //inputs are in same order as input list // a b : out; comment is for readability 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 1; table primitive Figure 3.12 A UDP for a 2-input OR gate.

6 Chapter 3 Keywords 6 Page 98 //module showing use of wire //connecting logic primitives module log_diag_eqn4 (x1, x2, x3, z1, z2); input x1, x2, x3; output z1, z2; wire x1, x2, x3; wire z1, z2; and inst1 (net1, x1, ~x2); and inst2 (net2, ~x1, x2); not inst3 (net3, ~x3); or inst4 (net4, net1, net2); or inst5 (net5, net2, net3); assign z1 = net4; assign z2 = net5; module //define internal nets as wire wire net1,net2,net3,net4,net5; //instantiate the built-in //primitives Figure 3.14 Module showing the use of wires to connect logic primitives. Page 99 //logic diagram test bench module log_diag_eqn4_tb; reg x1, x2, x3; wire z1, z2; //display variables $monitor ("x1x2x3 = %b, z1 = %b, z2 = %b", {x1, x2, x3}, z1, z2); //apply stimulus #0 x1=1'b0; x2=1'b0; x3=1'b0; #10 x1=1'b0; x2=1'b0; x3=1'b1; #10 x1=1'b0; x2=1'b1; x3=1'b0; #10 x1=1'b0; x2=1'b1; x3=1'b1; #10 x1=1'b1; x2=1'b0; x3=1'b0; #10 x1=1'b1; x2=1'b0; x3=1'b1; #10 x1=1'b1; x2=1'b1; x3=1'b0; #10 x1=1'b1; x2=1'b1; x3=1'b1; #10 $stop; //instantiate the module into //the test bench log_diag_eqn4 inst1 (.x1(x1),.x2(x2),.x3(x3),.z1(z1),.z2(z2) ); module Figure 3.15 Test bench for the module of Figure 3.14.

7 Chapter 3 Keywords 7 Page 99 x1x2x3 = 000, z1 = 0, z2 = 0 x1x2x3 = 001, z1 = 0, z2 = 1 x1x2x3 = 010, z1 = 1, z2 = 1 x1x2x3 = 011, z1 = 1, z2 = 1 x1x2x3 = 100, z1 = 1, z2 = 0 x1x2x3 = 101, z1 = 1, z2 = 1 x1x2x3 = 110, z1 = 0, z2 = 0 x1x2x3 = 111, z1 = 0, z2 = 1 Figure 3.16 Binary outputs for the module of Figure Figure 3.17 Waveforms for the test bench of Figure 3.15.

8 Chapter 3 Keywords 8 Page 105 //procedure for loading memory with //binary data from file icache.instr module mem_load (pc, ic_data_out); //list inputs and outputs input pc; output ic_data_out; //list wire and reg wire [2:0] pc; reg [7:0] ic_data_out; //a program counter to address 8 words //define memory size //instr_cache is an array of eight 8-bit regs reg [7:0] instr_cache [0:7]; //define memory contents //load instr_cache from file icache.instr $readmemb ("icache.instr", instr_cache); //use a program counter to access the instr_cache (pc) ic_data_out = instr_cache [pc]; module Verilog module to illustrate the use of $readmemb to load an instruc- Figure 3.12 tion cache.

9 Chapter 3 Keywords 9 Page 106 //mem_load test bench module mem_load_tb; integer i;//used to display contents reg [2:0] pc; wire [7:0] ic_data_out; //assign values to the program counter #0 pc = 3'b000; #10 pc = 3'b001; #10 pc = 3'b010; #10 pc = 3'b011; #10 pc = 3'b100; #10 pc = 3'b101; #10 pc = 3'b110; #10 pc = 3'b111; #15 $stop; //display the contents of the instruction cache for (i=0; i<8; i=i+1) #10 $display ("address %h = %b", i, ic_data_out); #150 $stop; //instantiate the module into the test bench mem_load inst1 (.pc(pc),.ic_data_out(ic_data_out) ); module Figure 3.22 Test bench for the module of Figure 3.21.

10 Chapter 3 Keywords 10 Page _ _ _ _ _ _ _ _1111 Figure 3.23 Instruction cache file icache.instr saved as a separate file. It is saved in the project folder without the.v extension. address = address = address = address = address = address = address = address = Figure 3.24 Outputs obtained from the test bench of Figure Page 108 Figure 3.25 Waveforms for the test bench of Figure 3.22.