Datapath & Control. Readings: Computer Processor. Control. Input. Datapath. Output

Transcription

1 Datapath & Control Readings: Computer Processor Devices Control Input Datapath Output Datapath: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions. 70

2 Simple CPU Develop complete CPU for subset of instruction set : LDUR, STUR Branch: B Opcode DAddr9 00 Rn Rd Opcode BrAddr26 Conditional Branch: CBZ Opcode CondAddr19 Rd Arithmetic: ADD, SUB Opcode Rm SHAMT Rn Rd Most other instructions similar 71

3 Execution Cycle Fetch Decode Operand Fetch Execute Result Store Next Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction 72

4 Processor Overview Overall Dataflow fetches instructions s select operand registers, ALU immediate values ALU computes values Load/Store addresses computed in ALU Result goes to register file or Data memory Register File Data 73

5 RTL & Processor Design Convert instructions to Register Transfer Level (RTL) specification RegA = RegB + RegC; RTL specifies required interconnection of units, control Math unit example: (add): A = A + B; I++; (mult): A = A * B: I++; (hold): A = A; I++; (init): A = Din; I++; A I 74

6 Fetch Address 75

7 Add/Subtract RTL Add instruction: ADD Rd, Rn, Rm Subtract instruction: SUB Rd, Rn, Rm Opcode Rm SHAMT Rn Rd 76

8 Add/Subtract Datapath Address 4 Aw Ab Aa Da Dw RegFile Db 77

9 Load RTL Load : LDUR Rd, [Rn, DAddr9] Opcode DAddr9 00 Rn Rd 78

10 Datapath + Load Address 4 Rd Rm Rn Aw Ab Aa Da Dw RegFile Db ALUOp Addr Dout Data 79

11 Store RTL Store : STUR Rd, [Rn, DAddr9] Opcode DAddr9 00 Rn Rd 80

12 Datapath + Store Address 4 Rd Rm Rn Aw Ab Aa Da Dw RegFile Db DAddr9 ALUOp ALUSrc Addr Dout Data MemToReg 81

13 Branch RTL Branch : B BrAddr BrAddr26 82

14 Datapath + Branch Address 4 Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg 83

15 Conditional Branch RTL Conditional Branch : CBZ Rd, CondAddr Opcode CondAddr19 Rd 84

16 Datapath + Conditional Branch Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address BrAddr26 4 ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 85

17 Control Identify control points for pieces of datapath Fetch Unit ALU Memories Datapath muxes Etc. Use RTL for determine per-instruction control assignments 86

18 Complete Datapath UncondBr Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 87

19 Control Signals Opcode[31:26] Opcode[25:21] xxxxx xxx ADD SUB LDUR STUR B CBZ 88

20 ADD Control = Mem[]; Reg[Rd] = Reg[Rn] + Reg[Rm]; = + 4; Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 UncondBr 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 89

21 SUB Control = Mem[]; Reg[Rd] = Reg[Rn] - Reg[Rm]; = + 4; Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 UncondBr 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 90

22 LDUR Control = Mem[]; Addr = Reg[Rn] + SignExtend(DAddr9); Reg[Rd] = Mem[Addr]; = + 4; Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 UncondBr 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 91

23 STUR Control = Mem[]; Addr = Reg[Rn] + SignExtend(DAddr9); Mem[Addr] = Reg[Rd]; = + 4; Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 UncondBr 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 92

24 B Control = Mem[]; = + SignExtend(BrAddr26)<<2; UncondBr Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 93

25 CBZ Control = Mem[]; Cond = (Reg[Rd] == 0); if (Cond) = + (CondAddr19)<<2; else = + 4; Reg2Loc RegWrite Rd Aw Ab Aa Da Dw RegFile Db WrEn DAddr9 Rm Rn Address CondAddr19 BrAddr26 UncondBr 4 Zero ALUOp ALUSrc MemWrite WrEn Addr Din Dout Data MemToReg <<2 1 0 BrTaken 94

26 Advanced: Exceptions Exception = unusual event in processor Arithmetic overflow, divide by zero, Call an undefined instruction Hardware failure I/O device request (called an interrupt ) user program Exception: System Exception Handler Approaches Make software test for exceptional events when they may occur ( polling ) Have hardware detect these events & react: Save state (Exception Program Counter, protect the GPRs, note cause) Call Operating System If (undef_instr) = C If (overflow) = C If (I/O) = C return from exception 95

27 Performance of Single-Cycle Machine CPI? ADD, SUB Instr. mux Reg Read mux ALU mux Reg Setup LDUR Instr. Reg Read ALU Data mux Reg Setup STUR Instr. Reg Read ALU Data CBZ Instr. mux Reg Read mux ALU mux setup B Instr. mux setup 96

28 Reducing Cycle Time Cut combinational dependency graph and insert register / latch Do same work in two fast cycles, rather than one slow one storage element Acyclic Combinational Logic storage element Acyclic Combinational Logic (A) storage element Acyclic Combinational Logic (B) storage element storage element 97

29 Pipelined Processor Overview Divide datapath into multiple stages IF Fetch RF Register Fetch EX Execute MEM Data WB Writeback Instr. Register File Data Register File 98