Computers and processors

Transcription

1 T224 Computers and processors Reference manua Author: Mirabee Waker

2 This pubication forms part of an Open University course T224, Computers and Processors. Detais of this and other Open University courses can be obtained from the Course Information and Advice Centre, PO Box 724, The Open University, Miton Keynes MK7 6ZS, United Kingdom: te (0) , e-mai genera-enquiries@open.ac.uk Aternativey, you may visit the Open University website at where you can earn more about the wide range of courses and packs offered at a eves by The Open University. To purchase a seection of Open University course materias visit the webshop at or contact Open University Wordwide, Michae Young Buiding, Waton Ha, Miton Keynes MK7 6AA, United Kingdom for a brochure. te (0) ; fax + 44 (0) ; e-mai ouwenq@open.ac.uk The Open University Waton Ha, Miton Keynes MK7 6AA First pubished Second edition Copyright # 2007 The Open University A rights reserved. No part of this pubication may be reproduced, stored in a retrieva system, transmitted or utiized in any form or by any means, eectronic, mechanica, photocopying, recording or otherwise, without written permission from the pubisher or a icence from the Copyright Licensing Agency Ltd. Detais of such icences (for reprographic reproduction) may be obtained from the Copyright Licensing Agency Ltd of 90 Tottenham Court Road, London W1T 4LP. Open University course materias may aso be made avaiabe in eectronic formats for use by students of the University. A rights, incuding copyright and reated rights and database rights, in eectronic course materias and their contents are owned by or icensed to The Open University, or otherwise used by The Open University as permitted by appicabe aw. In using eectronic course materias and their contents you agree that your use wi be soey for the purposes of foowing an Open University course of study or otherwise as icensed by The Open University or its assigns. Except as permitted above you undertake not to copy, store in any medium (incuding eectronic storage or use in a website), distribute, transmit or re-transmit, broadcast, modify or show in pubic such eectronic materias in whoe or in part without the prior written consent of The Open University or in accordance with the Copyright, Designs and Patents Act Typeset in India by Aden Prepress Services, Chennai. Printed and bound in the United Kingdom by Hobbs The Printers, Brune Road, Totton, Hampshire. SUP

3 Contents 1 The simuated processor Overview Registers Instruction set Description of the instructions Interrupt mechanism 17 2 Memoryassociated with the simuated processor 19 3 Input output associated with the simuated processor Overview Description of the input output faciities 21 4 The simuation environment The program editor The program memory The registers The data memory The menus 27 Appendix: ASCII codes 31 Important You wi be required to take this reference manua into the T224 examination with you, and when you dosoitmust be free of a notes and/or highighting. Therefore do not write in it or highight anything whie you are studying the course.

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5 Section 1: The simuated processor 5 1 The simuated processor 1.1 Overview The simuated processor has a oad store, Harvard architecture. It is essentiay a 16-bit machine, in that a the genera-purpose registers are 16-bit, as are the data and address buses to data memory and the address bus to program memory. The exception is the data bus between the processor and program memory, which is 24 bits wide because the instruction codes are a 24-bit. It uses memory-mapped input output. It offers a two-eve interrupt-handing faciity. 1.2 Registers The simuated processor has 17 registers (see Figure 1): 14 genera-purpose registers, each 16 bits wide 1 instruction pointer (IP), 16 bits wide 1 stack pointer (SP), 16 bits wide 1 status register, 16 bits wide but ony the east-significant 4 bits are used. The 14 genera-purpose registers are known, using the hexadecima numbering system, as Register r1, Register r2, Register r3, up to Register re. Register rf can act as a fifteenth genera-purpose register when the stack is not being used, but otherwise is the stack pointer. The status register has four fags: negative fag (N); zero fag (Z); interrupt 1 fag (IF1); interrupt 2 fag (IF2). The interrupt fags are impemented ony on the extended version of the simuated processor. 1.3 Instruction set The simuated processor offers eight data-move instructions, eeven arithmetic/ogic instructions and nine contro instructions. It is competey symmetric across a fourteen genera-purpose registers; that is, any of these fourteen registers may be used in any instruction which refers to registers. In Tabes 1and 2, R refers to aregister, abeed with asuffix if more than one is referenced, and nnnn refers to a 2-byte hexadecima address or data item.

6 6 Computers and processors: Reference manua 16 bits r1 r2 r3 r4 r5 r6 14 genera-purpose registers r7 r8 r9 ra rb rc rd re stack pointer SP (can aso function as genera-purpose register rf) instruction pointer IP status register 4 bits Figure 1 The programmer s mode of the simuated processor

7 Section 1: The simuated processor 7 Tabe 1 The instruction set in aphabetica order Instruction add immediate Instruction code (hexadecima) ARnnnn add register 020R 1 R 2 R 3 AND immediate CRnnnn AND register 040R 1 R 2 R 3 ca absoute compement register 85nnnn 05000R copy register 2A00R 1 R 2 jump absoute jump if negative reative jump if zero reative jump reative oad direct oad immediate 81nnnn 83nnnn 84nnnn 82nnnn ERnnnn DRnnnn oad register-indirect 2E00R 1 R 2 no-op OR immediate 9Rnnnn OR register 010R 1 R 2 R 3 pop register 26000R push register 250R00 return returnfrom interrupt shift eft register 06000R shiftright register 07000R stop store direct FRnnnn store register-indirect 2F0R 1 R 2 0 subtract immediate BRnnnn subtract register 030R 1 R 2 R 3

8 8 Computers and processors: Reference manua Tabe 2 The instruction set in instruction-code order Instruction code (hexadecima) Instruction no-op 010R 1 R 2 R 3 OR register 020R 1 R 2 R 3 add register 030R 1 R 2 R 3 subtract register 040R 1 R 2 R 3 AND register 05000R compement register 06000R shift eft register 07000R shiftright register 250R00 push register 26000R pop register 2A00R 1 R 2 copy register 2E00R 1 R 2 oad register-indirect 2F0R 1 R 2 0 store register-indirect 81nnnn jump absoute 82nnnn jump reative 83nnnn jump if negative reative 84nnnn jump if zero reative 85nnnn ca absoute return returnfrom interrupt stop 9Rnnnn OR immediate ARnnnn add immediate BRnnnn subtract immediate CRnnnn AND immediate DRnnnn oad immediate ERnnnn oad direct FRnnnn store direct

9 Section 1: The simuated processor Description of the instructions add immediate Hexadecima instruction code ARnnnn Assemby anguage equivaent add immediate rr nnnn Increase the instruction pointer s contents by 1. Add the vaue nnnn to the contents of Register rr and put the resut in Register rr. Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. add register Hexadecima instruction code 020R 1 R 2 R 3 Assemby anguage equivaent add register rr 1 rr 2 rr 3 Increase the instruction pointer s contents by 1. Add the contents of Register rr 1 to the contents of Register rr 2 and put the resut in Register rr 3 (it is permissibe for R 3 to be the same as R 1 or R 2 ). Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. AND immediate Hexadecima instruction code CRnnnn Assemby anguage equivaent AND immediate rr nnnn Increase the instruction pointer s contents by 1. Perform an AND operation between the vaue nnnn and the contents of Register rr and put the resut in Register rr. Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag.

10 10 Computers and processors: Reference manua AND register Hexadecima instruction code 040R 1 R 2 R 3 Assemby anguage equivaent AND register rr 1 rr 2 rr 3 Increase the instruction pointer s contents by 1. Perform anand operation between the contents of Register rr 1 and the contents of Register rr 2 and put the resut in Register rr 3 (it is permissibe for R 3 to be the same as R 1 or R 2 ). Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. ca absoute Hexadecima instruction code 85nnnn Assemby anguage equivaent ca absoute nnnn Increase the instruction pointer s contents by 1. Copy the new contents of the instruction pointer into the ocation in data memory whose address is in the stack pointer. Increase the stack pointer s contents by 1. Put nnnn into the instruction pointer. Do not change the zero or negative fags. compement register Hexadecima instruction code 05000R Assemby anguage equivaent compement register rr Increase the instruction pointer s contents by 1. Compement the contents of Register rr. Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag.

11 Section 1: The simuated processor 11 copy register Hexadecima instruction code 2A00R 1 R 2 Assemby anguage equivaent copy register rr 1 rr 2 Increase the instruction pointer s contents by 1. Copy the contents of Register rr 1 into Register rr 2. Do not change the zero or negative fags. jump absoute Hexadecima instruction code 81nnnn Assemby anguage equivaent jump absoute nnnn Put nnnn into the instruction pointer. Do not change the zero or negative fags. jump if negative reative Hexadecima instruction code 83nnnn Assemby anguage equivaent jump if negative reative nnnn If the negative fag is set to 1 Increase the instruction pointer s contents by 1. Add nnnn to the incremented contents of the instruction pointer and put the resut in the instruction pointer. Do not change the zero or negative fags. If the negative fag is ceared to 0 Increase the instruction pointer s contents by 1. Do not change the zero or negative fags. jump if zero reative Hexadecima instruction code 84nnnn Assemby anguage equivaent jump if zero reative nnnn

12 12 Computers and processors: Reference manua If the zero fag is set to 1 Increase the instruction pointer s contents by 1. Add nnnn to the incremented contents of the instruction pointer and put the resut in the instruction pointer. Do not change the zero or negative fags. If the zero fag is ceared to 0 Increase the instruction pointer s contents by 1. Do not change the zero or negative fags. jump reative Hexadecima instruction code 82nnnn Assemby anguage equivaent jump reative nnnn Increase the instruction pointer s contents by 1. Add nnnn to the incremented contents of the instruction pointer and put the resut in the instruction pointer. Do not change the zero or negative fags. oad direct Hexadecima instruction code ERnnnn Assemby anguage equivaent oad direct rr nnnn Increase the instruction pointer s contents by 1. Copy the contents of the ocation in data memory whose address is nnnn into Register rr. Do not change the zero or negative fags. oad immediate Hexadecima instruction code DRnnnn Assemby anguage equivaent oad immediate rr nnnn Increase the instruction pointer s contents by 1. Load the vaue nnnn into Register rr. Do not change the zero or negative fags.

13 Section 1: The simuated processor 13 oad register-indirect Hexadecima instruction code 2E00R 1 R 2 Assemby anguage equivaent oad register-indirect via rr 1 rr 2 Increase the instruction pointer s contents by 1. Copy the contents of the ocation in data memory whose address corresponds to the contents of Register rr 1 into Register rr 2. Do not change the zero or negative fags. no-op Hexadecima instruction code Assemby anguage equivaent no-op Increase the instruction pointer s contents by 1. OR immediate Hexadecima instruction code 9Rnnnn Assemby anguage equivaent OR immediate rr nnnn Increase the instruction pointer s contents by 1. Perform an OR operation between the vaue nnnn and the contents of Register rr and put the resut in Register rr. Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. OR register Hexadecima instruction code 010R 1 R 2 R 3 Assemby anguage equivaent OR register rr 1 rr 2 rr 3 Increase the instruction pointer s contents by 1.

14 14 Computers and processors: Reference manua Perform anoroperation between the contents of Register rr 1 and the contents of Register rr 2 and put the resut in Register rr 3 (it is permissibe for R 3 to be the same as R 1 or R 2 ). Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. pop register Hexadecima instruction code 26000R Assemby anguage equivaent pop register rr Increase the instruction pointer s contents by 1. Decrease the stack pointer s contents by 1. Copy the contents of the ocation in data memory whose address is in the stack pointer into Register rr. Do not change the zero or negative fags. push register Hexadecima instruction code 250R00 Assemby anguage equivaent push register rr Increase the instruction pointer s contents by 1. Copy the contents of Register rr into the ocation in data memory whose address is in the stack pointer. Increase the stack pointer s contents by 1. Do not change the zero or negative fags. return Hexadecima instruction code Assemby anguage equivaent return Decrease the stack pointer s contents by 1. Copy the contents of the ocation in data memory whose address is in the stack pointer into the instruction pointer. Do not change the zero or negative fags.

15 Section 1: The simuated processor 15 return from interrupt This instruction is avaiabe ony in the extended version of the simuated processor. Hexadecima instruction code Assemby anguage equivaent return from interrupt Decrease the stack pointer s contents by 1. Copy the contents of the ocation in data memory whose address is in the stack pointer into the instruction pointer. Decrease the stack pointer s contents by 1. Copy the contents of the ocation in data memory whose address is in the stack pointer into the status register. shift eft register Hexadecima instruction code 06000R Assemby anguage equivaent shift eft register rr Increase the instruction pointer s contents by 1. Shift the contents of register rr one bit to the eft (towards the mostsignificant bit); fi the east-significant bit with 0. Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. shift right register Hexadecima instruction code 07000R Assemby anguage equivaent shift right register rr Increase the instruction pointer s contents by 1. Shift the contents of register rr one bit to the right (towards the eastsignificant bit); fi the most-significant bit with 0. Set the zero fag if the resut is 0; otherwise cear the zero fag. Cear the negative fag.

16 16 Computers and processors: Reference manua stop Hexadecima instruction code Assemby anguage equivaent stop Increase the instruction pointer s contents by 1. Hat execution of the processor. store direct Hexadecima instruction code FRnnnn Assemby anguage equivaent store direct rr nnnn Increase the instruction pointer s contents by 1. Copy the contents of Register rr into the ocation in data memory whose address is nnnn. Do not change the zero or negative fags. store register-indirect Hexadecima instruction code 2F0R 1 R 2 0 Assemby anguage equivaent store register-indirect via rr 1 rr 2 Increase the instruction pointer s contents by 1. Copy the contents of Register rr 2 into the ocation in data memory whose address corresponds to the contents of Register rr 1. Do not change the zero or negative fags. subtract immediate Hexadecima instruction code BRnnnn Assemby anguage equivaent subtract immediate rr nnnn Increase the instruction pointer s contents by 1. Subtract the vaue nnnn from the contents of Register rr and put the resut in Register rr. Set the zero fag if the resut is 0; otherwise cear the zero fag.

17 Section 1: The simuated processor 17 Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. subtract register Hexadecima instruction code 030R 1 R 2 R 3 Assemby anguage equivaent subtract register rr 1 rr 2 rr 3 Increase the instruction pointer s contents by 1. Subtract the contents of Register rr 1 from the contents of Register rr 2 and put the resut in Register rr 3 (it is permissibe for R 3 to be the same as R 1 or R 2 ). Set the zero fag if the resut is 0; otherwise cear the zero fag. Set the negative fag if the most-significant bit of the resut is 1; otherwise cear the negative fag. 1.5 Interrupt mechanism The interrupt faciities are avaiabe ony in the extended version of the simuated processor. There are two eves of interrupt, Interrupt 1and Interrupt 2. Interrupt 1 has the higher priority. The interrupt vector for Interrupt 1 is at 0FFF and has defaut vaue 0D00. The interrupt vector for Interrupt 2 is at 0FFE and has defaut vaue 0E00. Both of these defaut vaues can be changed by the user. Interrupt fags IF1 and IF2 in the processor s status register indicate whether Interrupt 1 and Interrupt 2 respectivey are enabed. An interrupt can ony betaken if it is enabed that is, its fag is set to 1. Further, an interrupt on Interrupt 2 can ony be taken if both interrupts are enabed. When an interrupt occurs on Interrupt 1, then at the start ofthe next fetch execute sequence the processor wi automaticay and in this order: save the status register s contents on the stack; cear both IF1 and IF2 to 0; save the instruction pointer s contents on the stack; set the instruction pointer to the vaue of the interrupt vector for Interrupt 1. The procedure is simiar for an interrupt on Interrupt 2, except that ony IF2 is ceared to 0and that the instruction pointer is set to the vaue of the interrupt vector for Interrupt 2. The interrupt service routines for both Interrupt 1 and Interrupt 2 must end with a return from interrupt instruction.

18 18 Computers and processors: Reference manua When an input device causes an interrupt its status register is automaticay set to 1. The program needs to cear the register to 0after the interrupt has been serviced. More than one device can be assigned to Interrupt 1 simutaneousy. In such cases, software must be used to determine the priority of the devices within the interrupt service routine. Simiary, more than one device can be assigned to Interrupt 2 simutaneousy.

19 Section 2: Memory associated with the simuated processor 19 2 Memory associated with the simuated processor In the simuation, the processor has been impemented with 4096 (4K) 16-bit ocations of data memory. These ocations have hexadecima addresses 0000 to 0FFF incusive. The simuated processor has aso been impemented with 4096 (4K) 24-bit ocations of program memory. These ocations have hexadecima addresses 0000 to 0FFF incusive. In the extended version of the simuated processor, data memory addresses 0F00 to 0FFF (hexadecima) are reserved for the memorymapped addresses of status and data registers reating to input and output devices.

20 20 Computers and processors: Reference manua 3 Input output associated with the simuated processor The input output faciities are avaiabe ony in the extended version of the simuated processor. 3.1 Overview In the simuation, the processor is impemented with the foowing input devices: a bank of 8 switches a scaepan input an interrupt button and with the foowing output devices: a bank of 8 ight-emitting diodes a simpe 4-digit 7-segment dispay a smart 4-digit 7-segment dispay abuzzer an anaogue gauge. Tabe 3 shows the memory-mapped addresses for these devices registers. Tabe 3 Memory-mapped addresses for the registers in the input and output devices Device Register Memory-mapped address simpe 4-digit 7-segment dispay smart 4-digit 7-segment dispay data data 0F00 (east-significant digit) to 0F03 (most-significant digit) 0F04 buzzer data 0F05 bank of 8 ight-emitting diodes data 0F06 anaogue gauge data 0F07 interrupt button status 0F10 scaepan data 0F11 scaepan status 0F12 bank of 8 switches data 0F13 bank of 8 switches status 0F14 The processor offers two eves of interrupt, Interrupt 1 and Interrupt 2. Interrupt 1 has the higher priority.

21 Section 3: Input output associated with the simuated processor Description of the input output faciities Bank of 8 switches (input) By seecting the hardware tab for this device, the user can set each switch independenty to on (up) or off (down) by cicking on it. Data register Memory-mapped address 0F13. Ony the east-significant eight bits are used, with the east-significant bit corresponding to the rightmost switch. 1 corresponds to on and 0 to off. Status register Memory-mapped address 0F14. The east-significant bit is set to 1when an interrupt (see beow) has occurred. Interrupt faciity This faciity can be switched on (activated) or switched off, using the properties tab. The defaut setting is off. When the interrupt faciity is on, an interrupt is caused when any one of the switches changes its state. Using the properties tab, the switch bank s input can be set up to cause an interrupt on either Interrupt 1 or Interrupt 2. The defaut setting for the interrupt faciity is Interrupt 1. When an interrupt occurs, the status register is set to Scaepan (input) By seecting the hardware tab for this device, the user can dupicate the effects of pacing different weights in the scaepan by cicking with the mouse to move the scaepan up or down. Data register Memory-mapped address 0F11. The contents are set to the digita equivaent of the vertica position of the scaepan, with 0000 corresponding to the highest position. In 3-bit mode (see beow) the three east-significant bits of the data register are used; in 8-bit mode the eight east-significant bits are used. Status register Memory-mapped address 0F12. The east-significant bit is set to 1when an interrupt (see beow) has occurred. Interrupt faciity This faciity can be switched on (activated) or switched off, using the properties tab. The defaut setting is off.

22 22 Computers and processors: Reference manua When the interrupt faciity is on, this device causes an interrupt on Interrupt 2. When an interrupt occurs, the status register is set to bit and 8-bit working By seecting the properties tab, the user can choose between 3-bit and 8-bit working modes. In 3-bit mode the anaogue position of the scaepan is converted into a 3-bit binary representation before being stored in the data register; in 8-bit mode the anaogue position of the scaepan is converted into an 8-bit binary representation. The defaut setting is 8-bit working. Interrupt button (input) Cicking on this button causes an interrupt on Interrupt 1. Status register Memory-mapped address 0F10. When an interrupt occurs, the status register is set to Bank of 8 ight-emitting diodes (output) Each of these ights can be independenty it by setting the corresponding bit in the data register to 1. Data register Memory-mapped address 0F06. Ony the east-significant eight bits are used, with the east-significant bit corresponding to the rightmost LED. 1 corresponds to on and 0 to off. Simpe 4-digit 7-segment dispay (output) Each of the segments in each 7-segment dispay can be independenty it by setting the appropriate bit in the appropriate data register to 1. bit 6 bit 3 bit 7 bit 1 bit 0 bit 5 bit 4 bit 2 Figure 2 The reationship between the segmentsand the bits of the data registers Data registers Memory-mapped addresses 0F00 to 0F03; the base address is 0F00. 0F00 is used for the east-significant, rightmost, digit of the dispay and 0F03 for the most-significant, eftmost, digit. In each of these registers, bits correspond to segments as shown in Figure 2. Smart 4-digit 7-segment dispay (output) This device takes the vaue in its data register and converts it to either the denary equivaent or the hexadecima equivaent, as chosen by the user, before dispaying it on the four 7-segment dispays.

23 Section 3: Input output associated with the simuated processor 23 Leading zeros are inserted for hexadecima dispays, but not for denary ones. The error message Err is dispayed if denary mode has been chosen and the binary number in the data register is greater than denary Data register Memory-mapped address 0F04. Denary and hexadecima modes These are seected by the user via the properties tab. The defaut is denary mode. Buzzer (output) This device buzzes when the east-significant bit of its data register is set to 1. It is sient when the east-significant bit of its data register is ceared to 0. There is aso an associated on-screen graphic. Data register Memory-mapped address 0F05. Anaogue gauge (output) This device takes the vaue in its data register and dispays it on a horizonta anaogue scae. Data register Memory-mapped address 0F07. Ony the east-significant eight bits are used, so ony vaues from 0000 to 00FF can be dispayed correcty (higher vaues are dispayed as if they were 00FF).

24 24 Computers and processors: Reference manua 4 The simuation environment 4.1 The program editor The Program editor window is shown in Figure 3. This window can be re-sized verticay and/or moved around the screen using the mouse. Adupicate of the window can be opened via the View menu, thus enabing the user to work with two different program fragments simutaneousy. Figure 3 The Program editor window IP fied The eftmost fied of the window, IP, shows a c symbo aongside the address corresponding to the instruction pointer s contents. By doubecicking in this fied aongside a different address, the user can move the highight and aso change the instruction pointer s contents to that address. Address and Contents fieds The next two fieds of the window, Address and Contents, show the address and the contents respectivey of ocations in the program memory. The defaut contents are , which correspond to the no-op instruction. Instruction fied The rightmost fied of the window, Instruction, shows the instruction corresponding to the adjacent instruction code in the Contents fied. The user can change this instruction by first doube-cicking on the instruction

25 Section 4: The simuation environment 25 aready present and then either singe-cicking on items in the drop down menus (using the t symbo to open the menus where necessary) or typing in a hexadecima number, as appropriate. A doube-cick wi terminate the entry at any time. The instructions can be edited using the cut, copy and paste faciities in the Edit menu. Singe instructions or bocks of instructions can be deeted by first highighting the instruction or instructions and then cutting. No-op instructions repace the cut instructions. Singe instructions can be moved from one ocation to another by first highighting the instruction, then cutting, then cicking on the ine where the instruction is to go, then pasting. Bocks of instructions can be moved by first highighting them, then cutting, then cicking on the first ine where the instructions are to go, then pasting. Individua instructions or bocks of instructions can aso be copied and pasted esewhere in program memory. A instructions can be simutaneousy changed to no-ops by seecting Reset from the Options menu and then seecting Program memory. This action cears the contents of a ocations in program memory to Run button By cicking on the Run button at the bottom of the window, the user causes the simuated processor to execute instructions, starting with the one in the ocation whose address is in the instruction pointer. Whie the processor is running in this way, the Run button becomes astop button and cicking on this button stops the processor. Step button By cicking on the Step button at the bottom of the window, the user causes the simuated processor to execute the instruction in the ocation whose address is in the instruction pointer. Trace button By cicking on the Trace button at the bottom of the window, the user causes the simuated processor to execute instructions, starting with the one in the ocation whose address is in the instruction pointer.this execution is sufficientysow that the user can foow what is happening, and the trace speed can be set to Fast, Medium or Sow from the Options menu. The defaut is Fast. Whie the processor is tracing in this way, the Trace button becomes astop button and cicking on this button stops the processor. Go to IP button Cicking on the Go to IP button at the bottom of the window causes the Program editor window to scro to show a bock of program memory which incudes the ocation whose address is currenty in the instruction pointer.

26 26 Computers and processors: Reference manua Go to button Cicking on the Go to button at the bottom of the window opens a diaogue box which prompts the user to enter an address in program memory; the Program editor window then scros to show the contents of ocations at and near that address. 4.2 The program memory The Program memory window is shown in Figure 4. This window can be resized verticay and/or moved around the screen using the mouse. The defaut contents of a ocations in program memory are The user can return the contents of a ocations to this defaut vaue by seecting Reset from the Options menu and then seecting Program memory. This action aso changes a instructions in the Instruction fied of the Program editor window to no-ops. The user cannot ater the contents of individua ocations in program memory via the Program memory window; a changes to individua ocations in program memory must be made by entering, deeting or moving instructions in the Instruction fied in the Program editor. Figure 4 The Program memory window Cicking on the Go to button at the bottom of the window opens a diaogue box which prompts the user to enter an address in program memory; the Program memory window then scros to show that address. 4.3 The registers The Registers window is shown in Figure 5. This window can be moved around the screen using the mouse. The defaut contents of a registers are 0000, except for the stack pointer, whose defaut contents are The user can return the contents to these defaut vaues at any time by seecting Reset from the Options menu and then seecting Registers. The user can ater the contents of any ofregisters r1 to re, aong with the stack pointer (Register rf) and the instruction pointer, by doube-cicking in the Contents fied aongside them and then entering the new contents and pressing Enter. The current contents of the status register are indicated by four fags at the bottom of the Registers window: N(negative); Z(zero); IF1 (interrupt 1); IF2 (interrupt 2). Atick indicates that the fag s vaue is 1; a bank indicates that it is zero. Ony the negative and zero fags are shown in the basic version of the simuated processor. Fags are set or ceared by the processor during norma program operation. The user can aso set or cear fags whie testing aprogram, by cicking under N, Z, IF1 or IF2 as appropriate. 4.4 The data memory The Data memory window is shown in Figure 6. This window can be re-sized verticay and/or moved around the screen using the mouse. Adupicate of the window can be opened via the View menu, thus enabing the user to view two different bocks ofdata simutaneousy.

27 Section 4: The simuation environment 27 Figure 5 The Registers window: (a) in the basic simuated processor; (b) in the extended simuated processor The defaut contents of a ocations in data memory are The user can return the contents of a ocations to this defaut vaue by seecting Reset from the Options menu and then seecting Data memory. The user can ater the contents of any ocation in data memory by doube-cicking in the Contents fied aongside the address of that ocation and then entering the new contents and pressing Enter. The contents can be edited using the cut, copy and paste faciities in the Edit menu. Bocks of data can be deeted by first highighting them in the Contents fied and then cutting. The contents of these ocations become Bocks of data can be moved by first highighting them in the Contents fied, then cutting, then cicking in the Contents fied aongside the first address which is to hod the data bock, then pasting. Data can aso be copied and pasted esewhere in program memory. Cicking on the Go to button at the bottom of the window opens a diaogue box which prompts the user to enter an address in data memory; the Data memory window then scros to show that address. Figure 6 The Data memory window 4.5 The menus The Fie menu Open This aows the user to open an existing fie, which wi contain a program and associated data memory contents and register contents.

28 28 Computers and processors: Reference manua The defaut sub-foder the first time the Open command is chosen is the CT programs sub-foder. This sub-foder wi have been created as part of the software instaation process and resides within the hierarchy of foders My Documents\T224\Simuated processor\ uness stipuated otherwise by the user during the instaation process. CT programs remains the defaut sub-foder for the Open command unti the user opens a program from another sub-foder. When the new program and data are oaded, any previous instructions, data vaues and register contents which the user may have been working with are ost. Hence the user is prompted, where necessary, to save any work before the new program is oaded. Merge This brings in aprogram from aspecified fie and appends it to the program aready in the program memory and shown in the Program editor window. If the new program and the existing program have instructions in the same ocations(s) in program memory, the instructions in the new program wi overwrite the instructions in the existing program in those ocations. Merge aso brings in any associated data and appends it to the data aready in the data memory. If the new program and the existing program have associated data in the same ocations(s) in data memory, the data associated with the new program wi overwrite the data associated with the existing program in those ocations. The registers are not affected by the Merge command. If appropriate, the user is prompted to save any work before the new program is merged. Save If a program was retrieved from the CT programs sub-foder, it is necessary touse the Save As option to save it to another foder (thus preventing programs suppied by the course team from being overwritten). Otherwise, Save saves the program and associated data memory contents and register contents with the same fie name as the fie from which they were retrieved, thus over-writing the previousy saved version of the program, data memory and register contents. Save As This opens adiaogue box so that the user can enter the new fie name and/or choose a new foder. The defaut sub-foder the first time the command is chosen is My programs, which wi be in My Documents\T224\Simuated processor\ uness stipuated otherwise by the user during the instaation process. Save As then saves the program and associated data memory contents and register contents. Save As does not aow fies to be saved to the CT programs sub-foder.

29 Section 4: The simuation environment 29 Save workspace This aows the user to save the current size and window arrangement of the simuated processor screen. These then become the defaut. Print This aows the user to print the contents either of the currenty highighted window or of a windows. Except in the case of the registers, it does not print out any detais for ocations whose contents are zero. When print a is seected, the contents of the Program memory window are not printed, as this woud dupicate what is shown in the contents of the Program editor window. Exit This coses the simuation program. If appropriate, it prompts the user to save the current program first. The Edit menu Cut This aows highighted instructions in the Program editor or highighted contents in the Data memory to be cut. Copy This aows highighted instructions in the Program editor or highighted contents in the Data memory to be copied. Paste This aows cut or copied instructions from the Program editor to be inserted where the user cicks. In the case of abock of instructions, the bock wi be inserted such that the first instruction goes where the user cicks. Paste aso aows cut or copied contents in the Data memory tobe inserted where the user cicks. In the case of abock of data, the bock wi be inserted such that the first data item goes where the user cicks. The Options menu Reset This aows the user to reset any of: Data memory; Program memory; Registers. In the extended version of the simuation it aso aows the user to reset the Interrupt system. A of these can aso be reset simutaneousy. The user is asked to confirm the reset before it is impemented. Reset returns the chosen entity to the state it has when the simuation is first opened. Set trace speed This aows the user to seect from Fast, Medium or Sow for the trace speed. The defaut is Fast.

30 30 Computers and processors: Reference manua The View menu This aows the user to open new Program editor and Data memory windows. If any of the four defaut windows has been cosed, View aows the user to open it again. The Devices menu This menu is avaiabe ony in the extended version of the simuation. Input devices This aows the user to open Scaepan, Switch bank or Interrupt button. It is possibe to have more than one copy of the windows for these devices open simutaneousy. Output devices This aows the user to open LED bank, Anaogue gauge, Simpe 7-segment dispay, Smart 7-segment dispay or Buzzer. It is possibe to have more than one copy of the windows for these devices open simutaneousy. The Hep menu This takes the user to an eectronic version of this Reference Manua via a hyperinked contents page.

31 Appendix: ASCII codes 31 Appendix: ASCII codes ASCII Character Binarycode Hexadecima code Denarycode nu backspace horizonta tab ine feed A 10 carriage return D 13 escape B 27 space ! " # $ % & ( ) * A B 43, C D E 46 / F : A 58

32 32 Computers and processors: Reference manua ; B 59 < C 60 = D 61 > E 62? F A B C D E F G H I J A 74 K B 75 L C 76 M D 77 N E 78 O F 79 P Q R S T U V W X Y Z A 90 [ B 91 \ C 92 ] D 93 ^ E 94 _ F

33 Appendix: ASCII codes 33 a b c d e f g h i j A 106 k B C 108 m D 109 n E 110 o F 111 p q r s t u v w x y z A 122 { B C 124 } D 125 ~ E 126 deete F 127

34 Course team ist Academic staff Bernie Cark, Production Course Chair Geoff Einon David Gorham, Presentation Course Chair Reza Latif-Shabgahi Mike Meade Tony Nixon Adrian Pouton Richard Seaton Mirabee Waker Production staff Deirdre Bethune, Course Secretary Coin Buck, Project Officer Phiippa Broadbent, Buyer, Materias Procurement Roger Courthod, Graphic Artist Sarah Crompton, Graphic Designer Daphne Cross, Assistant Buyer, Materias Procurement Tony Duggan, Learning Projects Manager Joanne Feows, QA Engineer Aison George, Project Manager David Gosne, Software Designer Roger Harris, Production Course Manager Lori Johnston, Editor Karen Lemmon, Compositor Deborah Mairs, Presentation Course Manager Jane Moore, Editor Jon Owen, Graphic Artist Va Price, Rights Executive Coin Thomas, Software Designer

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