! Memory. " Periphery. " Serial Access Memories. ! Design Methodologies. " Hierarchy, Modularity, Regularity, Locality. ! Implementation Methodologies

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline Memory Periphery Lec 22: April 11, 2017 Memory Overview, Memory Periphery Serial Access Memories Design Methodologies Hierarchy, Modularity, Regularity, Locality Implementation Methodologies Custom, Semi-Custom (cell-based, array-based) Design Quality Variation Packaging 2 Array Architecture Memory Periphery 2 n words of 2 m bits each Good regularity easy to design Very high density if good cells are used 4 Array Architecture Array Architecture 2 n words of 2 m bits each 2 n words of 2 m bits each Good regularity easy to design Very high density if good cells are used Good regularity easy to design Very high density if good cells are used 5 6 1

2 Array Architecture Column Circuitry & Bit-line Conditioning 2 n words of 2 m bits each Good regularity easy to design Very high density if good cells are used 8 Column Circuitry Bitline Conditioning Some circuitry is required for each column Bitline conditioning Precharging Driving input data to bitline Sense amplifiers Column multiplexing (AKA Column Decoders) Precharge bitlines high before reads φ BL bit bit_b BL What if pre-charged to Vdd/2? Pros: reduces read-upset Challenge: generate Vdd/2 voltage on chip 9 10 Sense Amplifiers Differential Pair Amp Bitlines have many cells attached Ex: 32-kbit SRAM has 128 rows x 256 cols 128 cells on each bitline t pd (C/I) ΔV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors in each memory cell (small I) Sense amplifiers are triggered on small voltage swing V (ΔV) BL V(1) Differential pair requires no clock But always dissipates static power P1 sense_b bit BL N1 N3 P2 sense N2 bit_b BL V PRE ΔV V(0) Sense amp activated Word line activated t

3 Voltage Controlled Consider V ctrl as an analog input between 0 and V dd -V th What does this do? How does the voltage on V ctrl control operation? DC Transfer Out In What does this do? Inverter Output when: Input low In=Gnd? Pulls itself up In=V dd? Transfer curve? Until V dd -V TP Input high Like ratioed device with V ctrl low DC Transfer Function Differential Sense Amp

4 Differential Sense Amp Differential Sense Amp se sense enable Inputs precharged to common value After read operation is initiated, one bitline begins to drop After bitlines have reached sufficient differential value, se is enabled and amplifier evaluates Differential Sense Amp Differential Sense Amp DC Transfer /in with in=0.5v Differential Sense Amp Does need to be sized There is a ratioed logic effect here NMOS must overcome pullup resistance

5 Regenerative Feedback bit-lines disconnected at sensing to avoid their high capacitive load The regenerative feedback loop is now isolated When sense clock is high the values stored in bit-lines are regenerated, while the lines are disconnected, speeding up response sense_clk bit sense bit_b sense_b isolation transistors regenerative feedback Array Architecture Details 25 Column Drivers: Memory Bank Tristate Buffer Typically used for signal traveling, e.g. bus Ideally all devices connected to a bus should be disconnected except for active device reading or writing to bus Use high-impedance state to simulate disconnecting Input En Output Input En Ouptut 0 0 Z 1 0 Z Active-high buffer Tristate Buffer Tristate Inverters En Input Output Input Output Input En Vdd Output En En En Input Output En Input Output CMOS circuit

6 8x4 Memory with column decoder Read/Write Memory A1 (A2) Column Select 2-to-4 Decoder Row Decoder x4 Memory 0 1 CS 1-to-2 Decoder Column Decoder Tristate Buffer (read) D0 D1 D2 D3 A1 Rd/Wr (A2) Column Select 2-to-4 Row Decoder CS 8x4 Memory to-2 Column Decoder D0 D1 D2 D Read/Write Memory Read/Write Memory 0 8x4 Memory 0 8x4 Memory 2-to-4 Row Decoder to-4 Row Decoder 1 2 A1 3 A1 3 Rd/Wr = 0 Rd/Wr = 1 (A2) = 0 Column Select CS to-2 Column Decoder D0 D1 D2 D3 (A2) = 1 Column Select CS to-2 Column Decoder D0 D1 D2 D Serial Access Memories Serial Access Memories Serial access memories do not use an address Shift Registers Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) 36 6

7 Shift Register Shift registers store and delay data Simple design: cascade of registers clk Din 8 Dout Denser Shift Registers Flip-flops aren t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk counter counter readaddr writeaddr Din dual-ported SRAM reset Dout Serial In Parallel Out Parallel In Serial Out 1-bit shift register reads in serial data Load all N bits in parallel when shift = 0 After N steps, presents N-bit parallel output Then shift one bit out per cycle clk Sin shift/load clk P0 P1 P2 P3 Sout P0 P1 P2 P Queues FIFO, LIFO Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) WriteClk ReadClk Also called a stack WriteData FULL Queue ReadData EMPTY Use a single stack pointer for read and write

8 Ideas Minimize area of repeated cell Compensate with periphery Amplification (regeneration/restoration) Match periphery pitch to cell row/column Decoders Column Circuitry Bitline Precharge Bit Line Drivers (write circuitry) Sense Amplifiers VLSI Design Methodologies and Variation 43 Three Domain View of VLSI Design Flow at One Level Design Strategies FUNCTIONAL DESIGN Verilog/Spectre Verilog/Cadence Verilog/Spectre Metrics for Design Success: Performance Specs logical function, speed, power, area Time to Design engineering cost and schedule Ease of Test Generation and Testability engineering cost, manufacturing cost, schedule Extract Parasitic Elements LAYOUT VERIFICATION 1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check 3. Post layout simulation (PLS) SPICE Spectre (Spectre) Cadence (Virtuoso) PLS 45 Design is a continuous tradeoff to achieve performance specs with adequate results in the other metrics 46 Structured Design Strategies Modularity Strategies common for complex hardware and software projects Hierarchy: Subdivide the design in several levels of submodules Modularity: Define sub-modules unambiguously and well defined interfaces Regularity: Subdivide to max number of similar submodules at each level Locality: Max local connections, keeping critical paths within module boundaries Adds to the hierarchy and regularity Unambiguous functions Well defined behavioural, structural, and physical interfaces Enables modules to be individually designed and evaluated Eg. 4b Adder

9 Hierarchical & Modular 4-bit Adder Hierarchical & Modular Layout add sum carry add4 add add add sum carry sum carry sum carry b a c a b c b a c + co sum carry s s co b[3:0] a[3:0] c0 + add co3 s[3:0] b[3] a[3] b[2] a[2] b[1] a[1] b[0] a[0] (0,0) c0 add[3] add[2] add[1] add[0] co3 (100,400) s[3] (100,300) s[2] (100,200) s[1] (100,100) s[1] (0,100) (0,75) (0,25) (0,0) add1 Cell (50,100) b[i] c[i] add[i] s[i] a[i] co[i] (50,0) (100,100) (100,50) (100,0) nand nor nand nor nand nor nand inor n v 49 add4 Module 50 Floorplanning: Map Structural into Physical Regularity Design the chip reusing identical modules, circuits, devices. Unused die area -> inefficient layout Structural Hierarchy 1 mapped poorly into Physical Hierarchy. Better mapping Mis-mappings between Structural and Physical Hierarchies usually avoided by using automatic layout system. Regularity can exist at all levels of the design hierarchy Circuit Level: Uniform transistor sizes rather than manually optimizing each device Logic Level: Identical gate structures rather than customize every gate Architecture Level: construct architectures that use a number of identical sub-structures Locality (Physical) Implementation Methodologies TIME LOCALITY: modules are synchronized by common clock. Critical timing paths are kept within module boundaries Place modules to minimize large or global inter-module signal routes Take care to realize robust clock generation and distribution Signal routes between modules with large physical separation need sufficient time to traverse route Replicate modules, if necessary, to alleviate delay issues caused by long intermodule signal routes. Standard Cells Compiled Cells Digital Circuit Implementation Approaches Custom Cell-based Ma cro Cells Semicustom Pre-diffused (Gate Arrays) Array-based Pre-wired (FPGA's) 53 9

10 CMOS Chip Design Options Prewired Arrays Design Time and Cost Decreasing (for a given application) Performance Increasing, Die Area Decreasing, Power Dissipation Increasing (for a given application) Categories of prewired arrays (or field-programmable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based 55 Array-Based Programmable Logic Programming a PROM 1 X 2 X 1 X 0 I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array I 3 I 2 I 1 I 0 Programmable OR array I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array Fixed AND array Programmable AND array O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 PLA PROM PAL Indicates programmable connection Indicates fixed connection : programmed node NA NA f 1 f 0 Field-Programmable Gate Arrays Fuse-based Field-Programmable Gate Arrays RAM-based FPGA Features Configurable I/O Configurable Logic Programmable Interconnect/routing I/O Buffers I/O Buffers Program/Test/Diagnostics Vertical routes I/O Buffers Horizontal routing channel CLB CLB switching matrix Interconnect point Rows of logic modules Routing channels CLB CLB I/O Buffers Vertical routing channel 10

11 Standard-Cells Based Design Predominant custom design style Standardization is achieved at the logic or function level Specific designs for each gate are developed and stored in a software database of cell library Bahavioural, structural, and physical domain descriptions per cell Layout is usually automatically placed and routed using CAD software Standard Cell Library Contents SSI logic nand, nor, xor, inv, buffers, latches, registers each gate can have multiple implementations to provide proper drive for different fan-outs, eg. standard size, 2x, 4x MSI logic decoders, encoders, adders, comparators Datapath ALUs, register files, shifters Memories RAM, ROM System level multipliers, microcontrollers Cell-based Design (or standard cells) Standard Cell - Example Feedthrough Cell Logic Cell Rows of Cells Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies Automatic Cell Generation Design Quality Achieve specifications (static and dynamic) Die Size Power dissipation Testability Yield and Manufacturability Reliability Random-logic layout generated by CLEO cell compiler (Digital) 66 11

12 Variation Types Many reasons why variation occurs and shows up in different ways Scales of variation Wafer-to-wafer, die-to-die, transistor-to-transistor Correlations of variation Systematic, spatial, random (uncorrelated) 67 Source: Noel Menezes, Intel ISPD2007 Random Transistor-to-Transistor Impact Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Changes parameters Change transistor behavior 68 Transistors differ from each other in random ways W, L, tox, Vth W? L? tox? W %) V2, IDS = µn COX $ '+(VGS VT )VDS DS. # L &* Vth 65nm Impact of Vth Variation? Higher Vth? [Bernstein et al, IBM JRD 2006] 71 Not drive as strongly Id,vsat (Vgs-Vth) Performance? 72 12

13 Impact Performance V th # I ds # Delay (R on * C load ) Impact of V th Variation? Lower V th? Not turn off as well # leaks more # I DS = I S W & % ( e $ L ' # V GS V T & % $ nkt / q ' (# 1 e % $ # V DS & % ( $ kt / q ' & ( 1+ λv DS ' ( ) Variation See a range of parameters L: L min L max V th : V th,min V th,max Variation Margin for expected variation Must assume V th can be any value in range Speed # assume V th slowest value I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Probability Distribution V TH Variation See a range of parameters L: L min L max V th : V th,min V th,max Validate design at extremes Work for both V th,min and V th,max? Design for worst-case scenario Margining Also margin for Temperature Voltage supply Aging: end-of-life

14 Process Corners Simple Corner Example Many effects independent Many parameters With N parameters, Look only at extreme ends (low, high) How many cases? Try to identify the {worst,best} set of parameters Slow corner of design space, fast corner Use corners to bracket behavior Vthp 350mV 150mV What happens at various corners? 150mV Vthn 350mV Process Corners Many effects independent Many parameters Try to identify the {worst,best} set of parameters E.g. Lump together things that make slow Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners Slow corner of design space Use corners to bracket behavior 81 Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Probability Distribution Delay 82 Speed Binning Design Quality Probability Distribution Sell Premium Delay Sell nominal Sell cheap Discard Testability generation of good test vectors design of testable chip Yield and Manufacturability functional yield parametric yield Reliability threshold variation premature aging power and ground bouncing ESD/EOS -> can compensate in padframe noise and crosstalk

15 Packaging Technology Package Bonding Techniques Parasitics in an Electronic Package Summary of Package Types PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Admin Final Project Design memory (SRAM) EC for best figure of merits (FOM = Area*Power*Delay 2 ) # of points depends on teams reported Can propose extra work for extra credit Due 4/25 (last day of class) Everyone gets an extension until 5/3 (day of final exam) Absolutely doable by 2 people by 4/25 Final Project Schedule Posted now April 6 th report teams to instructor April 18 th extra credit proposals due to instructor April 25 th final report due Must be submitted via Canvas May 3 rd extension for reports (also day of final) All deadline times are midnight that day