ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Transcription

1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 22: April 11, 2017 Memory Overview, Memory Periphery

2 Lecture Outline! Memory " Periphery " Serial Access Memories! Design Methodologies " Hierarchy, Modularity, Regularity, Locality! Implementation Methodologies " Custom, Semi-Custom (cell-based, array-based)! Design Quality " Variation! Packaging 2

3 Memory Periphery

4 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used 4

5 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used 5

6 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used 6

7 Column Circuitry & Bit-line Conditioning

8 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used 8

9 Column Circuitry! Some circuitry is required for each column " Bitline conditioning " Precharging " Driving input data to bitline " Sense amplifiers " Column multiplexing (AKA Column Decoders) 9

10 Bitline Conditioning! Precharge bitlines high before reads BL bit φ BL bit_b! What if pre-charged to Vdd/2? " Pros: reduces read-upset " Challenge: generate Vdd/2 voltage on chip 10

11 Sense Amplifiers! Bitlines have many cells attached " Ex: 32-kbit SRAM has 128 rows x 256 cols " 128 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) BL V(1) V PRE ΔV Sense amp activated Word line activated V(0) t 11

12 Differential Pair Amp! Differential pair requires no clock! But always dissipates static power sense_b bit BL P1 N1 N2 P2 sense bit_b BL N3 12

13 Voltage Controlled! Consider V ctrl as an analog input between 0 and V dd -V th! What does this do?! How does the voltage on V ctrl control operation? 13

14 DC Transfer Out In 14

15 What does this do?! Output when: " In=Gnd? " In=V dd? " Transfer curve? 15

16 Inverter! Input low " Pulls itself up " Until V dd -V TP! Input high " Like ratioed device with V ctrl low 16

17 DC Transfer Function 17

18 Differential Sense Amp 18

19 Differential Sense Amp! se sense enable " Inputs precharged to common value " After read operation is initiated, one bitline begins to drop " After bitlines have reached sufficient differential value, se is enabled and amplifier evaluates 19

20 Differential Sense Amp 20

21 Differential Sense Amp 21

22 Differential Sense Amp 22

23 DC Transfer /in with in=0.5v 23

24 Differential Sense Amp! Does need to be sized! There is a ratioed logic effect here " NMOS must overcome pullup resistance 24

25 Regenerative Feedback! bit-lines disconnected at sensing to avoid their high capacitive load! The regenerative feedback loop is now isolated sense_clk! When sense clock is high the values stored in bit-lines are regenerated, while the lines are disconnected, speeding up response bit sense bit_b sense_b isolation transistors regenerative feedback 25

26 Array Architecture Details

27 Column Drivers: Memory Bank 27

28 Tristate Buffer! Typically used for signal traveling, e.g. bus! Ideally all devices connected to a bus should be disconnected except for active device reading or writing to bus! Use high-impedance state to simulate disconnecting Input En Output Input En Ouptut 0 0 Z 1 0 Z Active-high buffer

29 Tristate Buffer En Input Output Input Output Vdd En Input En Output En CMOS circuit 29

30 Tristate Inverters En En Input Output Input Output 30

31 8x4 Memory with column decoder 2-to-4 Decoder 0 8x4 Memory 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0 Row Decoder bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit (A2) Column Select CS to-2 Decoder Column Decoder Tristate Buffer (read) D0 D1 D2 D3 A0 31

32 Read/Write Memory 0 8x4 Memory 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0 2-to-4 Row Decoder bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr (A2) Column Select CS to-2 Column Decoder D0 D1 D2 D3 A0 32

33 Read/Write Memory 0 8x4 Memory 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0 2-to-4 Row Decoder bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 0 (A2) = 0 Column Select CS to-2 Column Decoder D0 D1 D2 D3 A0 33

34 Read/Write Memory 0 8x4 Memory 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0 2-to-4 Row Decoder bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit Rd/Wr = 1 (A2) = 1 Column Select CS to-2 Column Decoder D0 D1 D2 D3 A0 34

35 Serial Access Memories

36 Serial Access Memories! Serial access memories do not use an address " Shift Registers " Serial In Parallel Out (SIPO) " Parallel In Serial Out (PISO) " Queues (FIFO, LIFO) 36

37 Shift Register! Shift registers store and delay data! Simple design: cascade of registers clk Din 8 Dout 37

38 Denser Shift Registers! Flip-flops aren t very area-efficient! For large shift registers, keep data in SRAM instead! Move read/write pointers to RAM rather than data " Initialize read address to first entry, write to last " Increment address on each cycle clk Din counter counter readaddr writeaddr dual-ported SRAM reset Dout 38

39 Serial In Parallel Out! 1-bit shift register reads in serial data " After N steps, presents N-bit parallel output clk Sin P0 P1 P2 P3 39

40 Parallel In Serial Out! Load all N bits in parallel when shift = 0 " Then shift one bit out per cycle shift/load clk P0 P1 P2 P3 Sout 40

41 Queues! Queues allow data to be read and written at different rates.! Read and write each use their own clock, data! Queue indicates whether it is full or empty! Build with SRAM and read/write counters (pointers) WriteClk WriteData FULL Queue ReadClk ReadData EMPTY 41

42 FIFO, LIFO Queues! First In First Out (FIFO) " Initialize read and write pointers to first element " Queue is EMPTY " On write, increment write pointer " If write almost catches read, Queue is FULL " On read, increment read pointer! Last In First Out (LIFO) " Also called a stack " Use a single stack pointer for read and write 42

43 Ideas! Minimize area of repeated cell! Compensate with periphery " Amplification (regeneration/restoration)! Match periphery pitch to cell row/column " Decoders " Column Circuitry " Bitline Precharge " Bit Line Drivers (write circuitry) " Sense Amplifiers 43

44 VLSI Design Methodologies and Variation

45 Three Domain View of VLSI Design Flow at One Level FUNCTIONAL DESIGN Verilog/Spectre Verilog/Cadence Verilog/Spectre Extract Parasitic Elements LAYOUT VERIFICATION 1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check 3. Post layout simulation (PLS) SPICE Spectre (Spectre) Cadence (Virtuoso) PLS 45

46 Design Strategies! Metrics for Design Success: " Performance Specs " logical function, speed, power, area " Time to Design " engineering cost and schedule " Ease of Test Generation and Testability " engineering cost, manufacturing cost, schedule! Design is a continuous tradeoff to achieve performance specs with adequate results in the other metrics 46

47 Structured Design Strategies! Strategies common for complex hardware and software projects " Hierarchy: Subdivide the design in several levels of submodules " Modularity: Define sub-modules unambiguously and well defined interfaces " Regularity: Subdivide to max number of similar submodules at each level " Locality: Max local connections, keeping critical paths within module boundaries 47

48 Modularity! Adds to the hierarchy and regularity! Unambiguous functions! Well defined behavioural, structural, and physical interfaces! Enables modules to be individually designed and evaluated! Eg. 4b Adder 48

49 Hierarchical & Modular 4-bit Adder add4 c add add add add b a + s sum carry sum carry sum carry sum carry c a b c b a co sum carry s co nand inor nor nand nor nand nor nand n v 49

50 Hierarchical & Modular Layout b[3:0] a[3:0] c0 + add co3 s[3:0] b[3] a[3] b[2] a[2] b[1] a[1] b[0] a[0] (0,0) c0 add[3] add[2] add[1] add[0] co3 (100,400) s[3] (100,300) s[2] (100,200) s[1] (100,100) s[1] (0,100) (0,75) (0,25) (0,0) add1 Cell (50,100) b[i] c[i] add[i] a[i] co[i] (50,0) s[i] (100,100) (100,50) (100,0) add4 Module 50

51 Floorplanning: Map Structural into Physical Unused die area -> inefficient layout Structural Hierarchy 1 mapped poorly into Physical Hierarchy. Better mapping! Mis-mappings between Structural and Physical Hierarchies usually avoided by using automatic layout system. 51

52 Regularity! Design the chip reusing identical modules, circuits, devices.! Regularity can exist at all levels of the design hierarchy " Circuit Level: Uniform transistor sizes rather than manually optimizing each device " Logic Level: Identical gate structures rather than customize every gate " Architecture Level: construct architectures that use a number of identical sub-structures 52

53 Locality (Physical)! TIME LOCALITY: modules are synchronized by common clock. " Critical timing paths are kept within module boundaries " Place modules to minimize large or global inter-module signal routes " Take care to realize robust clock generation and distribution " Signal routes between modules with large physical separation need sufficient time to traverse route " Replicate modules, if necessary, to alleviate delay issues caused by long intermodule signal routes. 53

54 Implementation Methodologies Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Compiled Cells Ma cro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's)

55 CMOS Chip Design Options Design Time and Cost Decreasing (for a given application) Performance Increasing, Die Area Decreasing, Power Dissipation Increasing (for a given application) 55

56 Prewired Arrays Categories of prewired arrays (or field-programmable devices):! Fuse-based (program-once)! Non-volatile EPROM based! RAM based

57 Array-Based Programmable Logic I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array I 3 I 2 I 1 I 0 Programmable OR array I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array Fixed AND array Programmable AND array O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 PLA PROM PAL Indicates programmable connection Indicates fixed connection

58 Programming a PROM 1 X 2 X 1 X 0 : programmed node NA NA f 1 f 0

59 Field-Programmable Gate Arrays Fuse-based FPGA Features Configurable I/O Configurable Logic Programmable Interconnect/routing I/O Buffers Program/Test/Diagnostics Vertical routes I/O Buffers I/O Buffers Rows of logic modules Routing channels I/O Buffers

60 Field-Programmable Gate Arrays RAM-based CLB CLB Horizontal routing channel switching matrix Interconnect point CLB CLB Vertical routing channel

61 Standard-Cells Based Design! Predominant custom design style! Standardization is achieved at the logic or function level! Specific designs for each gate are developed and stored in a software database of cell library " Bahavioural, structural, and physical domain descriptions per cell! Layout is usually automatically placed and routed using CAD software 61

62 Standard Cell Library Contents! SSI logic " nand, nor, xor, inv, buffers, latches, registers! MSI logic " each gate can have multiple implementations to provide proper drive for different fan-outs, eg. standard size, 2x, 4x " decoders, encoders, adders, comparators! Datapath " ALUs, register files, shifters! Memories " RAM, ROM! System level " multipliers, microcontrollers 62

63 Cell-based Design (or standard cells) Feedthrough Cell Logic Cell Rows of Cells Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers

64 Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies

65 Automatic Cell Generation Random-logic layout generated by CLEO cell compiler (Digital)

66 Design Quality! Achieve specifications (static and dynamic)! Die Size! Power dissipation! Testability! Yield and Manufacturability! Reliability 66

67 Variation Types!! Many reasons why variation occurs and shows up in different ways Scales of variation "! Wafer-to-wafer, die-to-die, transistor-to-transistor Correlations of variation " Systematic, spatial, random (uncorrelated) Penn ESE 570 Spring Khanna 67

68 Source: Noel Menezes, Intel ISPD2007 Penn ESE 570 Spring Khanna 68

69 Random Transistor-to-Transistor! Random dopant fluctuation! Local oxide variation! Line edge roughness! Etch and growth rates! Transistors differ from each other in random ways Penn ESE 570 Spring Khanna 69

70 Impact! Changes parameters " W, L, t OX, V th! Change transistor behavior " W? " L? " t OX? I DS = µ n C OX " $ # W L %) ' ( V & GS V T )V DS V 2 DS + * 2,. - Penn ESE 570 Spring Khanna 70

71 V th 65nm [Bernstein et al, IBM JRD 2006] Penn ESE 570 Spring Khanna 71

72 Impact of V th Variation?! Higher V th? " Not drive as strongly " I d,vsat (V gs -V th ) " Performance? Penn ESE 570 Spring Khanna 72

73 Impact Performance! V th # I ds # Delay (R on * C load ) Penn ESE 570 Spring Khanna 73

74 Impact of V th Variation?! Lower V th? " Not turn off as well # leaks more # I DS = I S "% W $ L & ( e ' # % $ V GS V T nkt / q & (# ' 1 e % $ # V DS & % ( $ kt / q ' & ( 1+ λv DS ' ( ) Penn ESE 570 Spring Khanna 74

75 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max Penn ESE 570 Spring Khanna 75

76 Variation! Margin for expected variation! Must assume V th can be any value in range " Speed # assume V th slowest value I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Probability Distribution V TH Penn ESE 570 Spring Khanna 76

77 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max! Validate design at extremes " Work for both V th,min and V th,max? " Design for worst-case scenario Penn ESE 570 Spring Khanna 77

78 Margining! Also margin for " Temperature " Voltage supply " Aging: end-of-life Penn ESE 570 Spring Khanna 78

79 Process Corners! Many effects independent! Many parameters! With N parameters, " Look only at extreme ends (low, high) " How many cases?! Try to identify the {worst,best} set of parameters " Slow corner of design space, fast corner! Use corners to bracket behavior Penn ESE 570 Spring Khanna 79

80 Simple Corner Example 350mV What happens at various corners? Vthp 150mV 150mV Vthn 350mV Penn ESE 570 Spring Khanna 80

81 Process Corners! Many effects independent! Many parameters! Try to identify the {worst,best} set of parameters " E.g. Lump together things that make slow " Vthn, Vthp, temperature, Voltage " Try to reduce number of unique corners " Slow corner of design space! Use corners to bracket behavior Penn ESE 570 Spring Khanna 81

82 Range of Behavior! Still get range of performances! Any way to exploit the fact some are faster? Probability Distribution Delay Penn ESE 570 Spring Khanna 82

83 Speed Binning Probability Distribution Sell Premium Sell nominal Sell cheap Discard Delay Penn ESE 570 Spring Khanna 83

84 Design Quality! Testability " generation of good test vectors " design of testable chip! Yield and Manufacturability " functional yield " parametric yield! Reliability " threshold variation " premature aging " power and ground bouncing " ESD/EOS -> can compensate in padframe " noise and crosstalk Penn ESE 570 Spring Khanna 84

85 Packaging Technology Penn ESE 570 Spring Khanna 85

86 Package Bonding Techniques Penn ESE 570 Spring Khanna 86

87 Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring Khanna 87

88 Summary of Package Types 88

89 Admin! Final Project " Design memory (SRAM) " EC for best figure of merits (FOM = Area*Power*Delay 2 ) " # of points depends on teams reported " Can propose extra work for extra credit " Due 4/25 (last day of class) " Everyone gets an extension until 5/3 (day of final exam) " Absolutely doable by 2 people by 4/25 89

90 Final Project Schedule! Posted now! April 6 th report teams to instructor! April 18 th extra credit proposals due to instructor! April 25 th final report due " Must be submitted via Canvas! May 3 rd extension for reports (also day of final)! All deadline times are midnight that day 90