3DIC & TSV interconnects

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Jerome Williamson
5 years ago
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Semiconductor chip packaging market evolution

(Intel, Samsung, TI, STMicro, TSMC, Qualcomm )

Advanced Packaging DIP QFP PGA WB BGA FC BGA /

5D interposer FO WLP FO PoP FO SiP Moving to

collective wafer-levelpackaging technique

2 Semiconductor chip packaging market evolution The pace of innovation in chip packaging industry has never been faster! Today driven by semiconductor company giants (Intel, Samsung, TI, STMicro, TSMC, Qualcomm ) along with Top 5 biggest packaging subcontractors (ASE, Amkor, SPIL, STATschippac, PTI ) PoP / PiP SiP 3D WLP 3DIC Advanced Packaging DIP QFP PGA WB BGA FC BGA / CSP WL CSP 2.5D interposer FO WLP FO PoP FO SiP Moving to highperformance, high-density, low cost, collective wafer-levelpackaging technique standards LCC SOT / TSOP QFN Embedded SiP 1970s 1980s 1990s 2000s 2010s 2020s Copyrights Yole Développement SA. All rights reserved.

3 Scope of today s presentation Today s presentation! FOWLP Fan-in WLCSP 3D WLCSP 2.5D Interposers 3DIC ST Elpida Flip Chip Xilinx 3D FOWLP This report is focused on the three middle-end technological platforms in which TSV is used as a vertical interconnect: 3D WLCSP, 2.5D Interposer and 3DIC Copyrights Yole Developpement SA. All rights reserved.

4 TSV / WLP Reality in Low-End, FSI CMOS Image Sensors Most low-end CIS (CIF, VGA to 2MPixels resolutions) are adopting 3D WLCSP packaging: STMicro s WLCamera with TSV / WLP OnSemi / Cypress s3d WLCSP of medical CMOS image sensor Galaxycore s 3D WLCSP of CMOS image sensors SK Hynix WLP / TSV in CMOS image sensors Samsung s TSV / WLP in mobile phone CIS BYD s CSP camera module Toshiba s WLCamera with TSV / WLP Sharp s WLCamera with TSV / WLP Copyrights Yole Developpement SA. All rights reserved. Omnivision s WLCamera with TSV / WLP SuperPix s TSV package in 2MPixels CMOS image sensors

5 TSV / WLP Reality in High-End, BSI CMOS Image Sensors In high-end applications (video cameras, DSC, Smart phones) with > 5-8Mpixel sensor resolutions, BSI architectures are using front-side etched TSV to reach the BEOL metal layers Samsung s TSV trench TSV in BSI image sensors found in Galaxy SII Smart phone product (Courtesy of System Plus Consulting, Chipworks) Copyrights Yole Developpement SA. All rights reserved. Toshiba s redundant TSV interconnects in BSI image sensors found in Fujifilm camera (Courtesy of Chipworks)

6 TSV Implementation in MEMS Accelerometer STMicroelectronics Accelerometer with TSV in MEMS IC Device was introduced in 2011 and can be found in Nokia s mobile phone Courtesy of System Plus Consulting TSV Copyrights Yole Developpement SA. All rights reserved.

Revenues (M$) 2011 Global 3D TSV activity - Breakdown by top players 2011 global 3D TSV actvity* - Including internal production lines - * Middle-end activity or revenues including TSV etching, Via

7 Revenues (M$) 2011 Global 3D TSV activity - Breakdown by top players 2011 global 3D TSV actvity* - Including internal production lines - * Middle-end activity or revenues including TSV etching, Via Filling, RDL, Bumping, wafer test & wafer level assembly total 3D TSV activity revenues ~ $340 Million 3DIC 2.5D Interposer 3D WLCSP Copyrights Yole Developpement SA. All rights reserved.

Global 3DIC & TSV interconnects roadmap Hybrid Memory Cube DDR stack Stacked Memories Wide IO stack NAND Flash stack DDR3 stack 3D SiP GPU DDR3 Logic 3D SiP/SoC Digital APE Analog Ultimate

8 Global 3DIC & TSV interconnects roadmap Hybrid Memory Cube DDR stack Stacked Memories Wide IO stack NAND Flash stack DDR3 stack 3D SiP GPU DDR3 Logic 3D SiP/SoC Digital APE Analog Ultimate Heterogeneous 3DIC CPU Wide IO RF Mem. Digital Analog MEMS ASIC Logic RF Mem. Logic 3D SoC Digital FPGA FPGA FPGA Analog FPGA FPGA Wide IO Wide IO APE HB-LED modules Power, Analog & RF LED LED LED IPD LED LED LED Driver Driver IGBT & Power MOSFET PA 3D IPD MEMS & Sensors Capping MEMS Capping Sapphire or Silicon MEMS Logic MEMS MEMS ASIC ASIC MEMS Capping Power GaN MOSFET IPD Capping Analog/RF FBAR < BSI DSP Copyrights Yole Développement SA. All rights reserved. SOC CIS CIS BSI CIS DSP + mem CIS SOC CIS SOC CIS 3D WLCSP FSI SOC CIS Imaging & Opto 2015 LED 2016 DSP mem

9 Wafer count (12 eq.) 10,000,000 Global TSV chip wafer forecast Global TSV Chip Wafer Forecast (All 3D Platforms) Breakdown by Segment (12''eq wafers) Yole Developpement July D Stacked NAND Flash 3D Wide IO Memory 8,000,000 Logic 3D SiP / SoC 6,000,000 3D Stacked DRAM MEMS / Sensors 4,000,000 LED 2,000,000 RF, Power, Analog & Mixed signal Imaging & Optoelectronics Copyrights Yole Developpement SA. All rights reserved.

5D Glass / Silicon interposers are emerging as key substrate elements for connecting the nanometer to millimeter

10 Why 2.5D glass / silicon interposers are needed? 2.5D Glass / Silicon interposers are emerging as key substrate elements for connecting the nanometer to millimeter worlds in future semiconductor chip packaging assembly (12-28nm) (5-45um) (5-100um) (Glass / Silicon substrate) (0,5-5µm) Wiring / RDL Micro-bump Pitch = 45µm Bump Pitch = µm BGA laminate (40-250um) C4 Bump (0,4 0,8 mm) BGA balls PCB / PWB Copyrights Yole Développement SARL. All rights reserved.

11 2.5D interposer solution for Large die Logic applications (FPGA, ASICs, DSP, etc ) 4 slices instead of one die 3D-SOC re-partionned logic design Increase back of CMOS manufacturing yield (because of smaller die size) High density wiring at the surface of the 4 layer copper damascene silicon interposer wafer breakthrough in COST versus POWER CONSUMPTION versus PERFORMANCE Logic n Logic n+1 Logic n+2 Logic n+3 Silicon interposer BGA Laminate PCB Copyrights Yole Développement SARL. All rights reserved.

12 2.5D interposer solution for Logic + Memory integration (FPGA, ASICs, DSP, CPU / GPU, etc ) Breakthrough in bandwidth & performance versus power consumption Massive parallel DDR memory integration close to logic IC and interconnected through high density / high speed silicon interposer wiring layers Unprecedented level of computing performance and thermal management possible (side by side) Memory CPU / GPU Memory Silicon interposer BGA Laminate PCB Copyrights Yole Développement SARL. All rights reserved.

2.5D interposers for large CPUs / GPUs Power 8 by IBM to be based on 2.

5D interposers for computing with lots of on board memory and ultra large data bus

silicon interposer. (Courtesy of SemiAccuracte.

13 2.5D interposers for large CPUs / GPUs Power 8 by IBM to be based on 2.5D Interposers Haswel, Intel GPU on 2.5D interposers for computing with lots of on board memory and ultra large data bus IBM Power 7+: four 32nm CMOS multi-core CPU dies are placed side by side on a silicon interposer. (Courtesy of SemiAccuracte.com) Cross section pictures of an IBM 3D stacked module demonstrator with TSVs in the thinner die (courtesy of Chipworks) Copyrights Yole Développement SARL. All rights reserved.

interposer with a 512-wide data bus and on interposer memory Will probably be

Future gaming platforms will offer 3D imagery, which requires fast & high

14 GPU in 2.5D for gaming console applications Sony PS4 (2013) will have a GPU on interposer with a 512-wide data bus and on interposer memory Will probably be an AMD chip. Future gaming platforms will offer 3D imagery, which requires fast & high bandwidth computing power. 2.5D is unanymously praised as the solution for this purpose An interposer module for GPU demonstrator Courtesy of Global Foundries, Copyrights Yole Développement SARL. All rights reserved.

digital single packaged ICs Log (I/O count) >5,000 1,000 High-end

processors, low-end CPUs 20mm 2 50mm 2 100mm 2 500mm 2 Log

likely to take on most of today s fcbga market Logic-only 3D

15 Logic-only 2.5D interposer competing solutions for high performance / large digital single packaged ICs Log (I/O count) >5,000 1,000 High-end CPUs, GPUs Mobile phone baseband ICs Mobile phone application processors, low-end CPUs 20mm 2 50mm 2 100mm 2 500mm 2 Log (unpackaged IC size) Fan-out WLP and fcbga with copper pillars are likely to take on most of today s fcbga market Logic-only 3D interposers are only expected to develop for very high I/O density and I/O count processors Copyrights Yole Développement SARL. All rights reserved.

16 Revenues (B$) 2.5D Interposer Penetration rate 2.5D Interposer Platform Revenues 2.5D Glass & Silicon Interposer Platform Revenues Comparison with laminate substrate industry (B$) 12 15% 10 Yole Developpement July % 6 4 5% Organic IC packaging substrate revenues $ 8.3 B $ 8.5 B $ 8.7 B $ 8.8 B $ 9.0 B $ 9.2 B $ 9.4 B $ 9.6 B Glass/Silicon interposer substrate revenues $ 0.01 B $ 0.02 B $ 0.05 B $ 0.18 B $ 0.42 B $ 0.65 B $ 0.97 B $ 1.36 B 2.5D Interposer technology penetration rate 0.2% 0.3% 0.6% 2.1% 4.7% 7.1% 10.3% 14.2% 0% By 2017, we expect 2.5D interposer revenues to reach 14% of the packaging substrate market value Copyrights Yole Developpement SA. All rights reserved.

17 Qualcomm CPU roadmap: from PoP to 2.5D / 3DIC Mobile applications Tablet / Gaming / Smart TV applications Courtesy of Qualcomm Qualcomm is actively developing the 2.5D interposers & 3DIC architectures Copyrights Yole Développement SARL. All rights reserved.

18 Wide IO memories - Coming Soon! Focus on Samsung s recent announcement Samsung foundry announced it will be ready next year to release 3D TSV Technology and Wide IO Memory! Switching from a conventional PoP approach to 3D stack with wide IO memory will enable package size reduction by 35%, and power consumption by 50% Bandwith is expected to increase by 8 Courtesy of Samsung Copyrights Yole Développement SA. All rights reserved.

19 Logic 2.5D / 3D SoC verus SiP packaging roadmap 3D-SiP Performancedriven Game console DDR3 GPU DDR3 stack GPU Server Data center Industrial applications DDR3 CPU DDR3 stack CPU Industrial & networking applications FPGA Wide IO «Hybrid» 3D-SiP/SoC 3DIC Tablets Smartphones APE Wide IO Wide IO APE System Partitioning Logic Logic Ultimate Heterogeneous 3DIC «powerpoint concept» MEMS ASIC RF Mem. Digital Analog Mobile Analog Digital 3D-SoC Cost & Performance driven Smart TV Set-top box Network FPGA FPGA FPGA FPGA RF Mem. Digital Analog > Copyrights Yole Développement SA. All rights reserved.

supply chain: availability of a second source 3D packaging service provider is critical before starting any production.

need to be in place for 3D SiP applications involving multiple-party ICs (memory, logic, interposer ) LPDDR3 Logic I/O

Such specifications need to be defined in order to establish a standardized and flexible supply chain (e.g.

reliability: in many applications such as stacking of DRAM modules, SSD for enterprise market and memory + logic stacking

through the whole package Shift in the Design / Test method paradigm & system co-design: heterogeneous functions, packaging, new

20 Roadblocks toward 2.5D / 3DIC commercialization in HVM There are 5 main challenges ahead for a wide adoption of 3DICs: Infrastructure availability & supply chain: availability of a second source 3D packaging service provider is critical before starting any production. Additionally, key strategic alliances / partnerships between memory suppliers, Logic IDMs, Foundries and Packaging subcontractors need to be in place for 3D SiP applications involving multiple-party ICs (memory, logic, interposer ) LPDDR3 Logic I/O standardization between interfaces such as memory / logic / interposer layers is also critical. Such specifications need to be defined in order to establish a standardized and flexible supply chain (e.g. of JEDEC initiative for defining Wide IO memory standards for 3D TSV in consumer applications) Thermal management & interconnect reliability: in many applications such as stacking of DRAM modules, SSD for enterprise market and memory + logic stacking applications, thermal management is certainly the biggest barrier to entry for 3D if we cannot manage to dissipate heat well through the whole package Shift in the Design / Test method paradigm & system co-design: heterogeneous functions, packaging, new CAD tools (thermal & mechanical simulation), test for KGD and new design architectures are required to get the full benefits of 3D Cost: depending on end-product, 3D TSV manufacturing cost should be reasonable and reduced in order to make it widely occurring in cost sensitive applications Copyrights Yole Développement SA. All rights reserved.

TSV manufacturing tool-box Technology Readiness Dashboard Ready for HVM Ready for initial ramp-up Not ready TSV Middle Manufacturability TSV Lithography TSV etching TSV isolation Barrier & Seed layer

21 TSV manufacturing tool-box Technology Readiness Dashboard Ready for HVM Ready for initial ramp-up Not ready TSV Middle Manufacturability TSV Lithography TSV etching TSV isolation Barrier & Seed layer TSV filling CMP Passiv./ UBM & Bumping Process performance (vs technical requirements) Repetability Uniformity & process Window Tool availability & maturity Throughput & cost of Ownership TSV Middle Manufacturability Stacking / Bonding C2C C2W W2W Temporary bonding to carrier Thinning / grinding TSV nailing Carrier debonding Inspection & metrology Testing (probing & final test) Process performance (vs technical requirements) Repetability Uniformity & process Window Tool availability & maturity Throughput & cost of Ownership Copyrights Yole Développement SA. All rights reserved.

22 Complex IC packaging supply chain (main business models) Research Institutes (acting across the complete supply chain) IP houses (related to packaging, accross the complete supply chain) Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate laminate suppliers PWB suppliers (motherboard) Design of chip & package Silicon Manufacturing «Front-end» Wafer Level Packaging «Middle -end» Package Assembly & Final test «Back-end» Sub-Module / Sub-systems Design & Assembly System / Product Fab-less IC players IDMs (Integrated Device Manufacturers) Wafer foundries Wafer Bumping houses BE assembly & Test houses WLP houses (no need for traditional substrate) SiP module houses Test houses OSATs (Open Source Assembly & Test houses) SiP design houses ODM / EMS / DMS (electronic design & manufacturing services) OEMs (Original Equipment Makers) Front-end related materials suppliers FE related equipment suppliers BE Packaging materials suppliers BE Packaging equipment suppliers Passive comp. & SMT materials SMT equipment suppliers Copyrights Yole Développement SARL. All rights reserved.

TSMC s Integrated Supply-Chain for efficient 2.

wafer manufacturing to bumping, packaging, assembly & test will

23 TSMC s Integrated Supply-Chain for efficient 2.5D Interposer integration TSMC s vertical integration move from wafer manufacturing to bumping, packaging, assembly & test will tackle the supply chain challenge related to the commercialization of 2.5D/3DIC modules Altera s FPGA supported by TSMC s CoWoS 2.5D interposer platform Copyrights Yole Développement SA. All rights reserved.

24 ASE 2.5D silicon interposer platform ASE (TW) is developing coarse type of 2.5D silicon interposer substrate solution with high electrical performances 5/5µm to 10/10µm Line/Spaces ( supported by RDL technology) µm thick silicon Via diameters of 30-50µm (DRIE or laser drilled) Copper via plating Copyrights Yole Développement SARL. All rights reserved.

inspection cleaning TSV Wafer test handling

COLLABORATIVE supply-chains between wafer

25 profits profits Emerging 2.5D / 3DIC Open Ecosystems of Virtual IDMs chip / package Design $$$$ implant FE Middle-end BE $$ etch CVD PVD CMP inspection cleaning TSV Wafer test handling RDL bumping thinning underfill C2W C2C / C2S molding dicing Final test BGA? VERTICALLY INTEGRATED wafer + package manufacturing foundries? Fab-less / Fab-light chip companies COLLABORATIVE supply-chains between wafer foundries & packaging subcontractors VIRTUAL IDM new ecosystems Copyrights Yole Développement SA. All rights reserved.

Silicon & Glass 2.5D Interposers: Who is doing what?

/panel supply TSV/TGV making Wiring (BEOL, RDL)

test Silicon substrate makers Glass substrate makers

IPD wafer foundry) OSATs PCB manufacturers New ASE

26 Silicon & Glass 2.5D Interposers: Who is doing what? Coarse-pitch Interposers Fine-pitch Interposers Wafer /panel supply TSV/TGV making Wiring (BEOL, RDL) Interposer test Bumping Packaging & assembly Final test Silicon substrate makers Glass substrate makers IC wafer foundry New TSMC model MEMS wafer foundry (or IPD wafer foundry) OSATs PCB manufacturers New ASE model IDMs Copyrights Yole Développement SA. All rights reserved.

27 manufacturing value (in B$) Middle-end versus Back-end 2.5D / 3DIC opportunity $10.0B $9.0B Global 3D TSV semiconductors packaging, assembly & test market value Yole Developpement July 2012 $8.0B $7.0B $6.0B $5.0B $4.0B $3.0B $2.0B $1.0B Back-end' assembly & test processing value $0.1B $0.2B $0.3B $0.6B $1.3B $2.3B $3.7B $5.8B Global 'Middle-end' wafer processing value $0.2B $0.3B $0.5B $0.7B $1.2B $1.8B $2.6B $3.5B CAGR 81% 46% The role sharing between each party is not obvious Indeed, the middle-end space is almost a zero-margin business, while front-end wafer manufacturing as well as back-end assembly & test remain profitable enough areas for sustainable business. We estimate that the global 3D TSV semiconductors packaging, assembly and test markets will reach $9B in business by Copyrights Yole Développement SA. All rights reserved.

28 business business Middle-end place in the future landscape of 2.5D / 3DIC integration Middle-end place in the future landscape of 2.5D / 3DIC chip to package manufacturing A vision of value distribution by 2017 > B12$ implant FE wafer manufacturing PVD CMP etch inspection cleaning CVD TSV Wafer test RDL / wiring bumping handling 2.5D & 3DIC Middle-end BE assembly & test ~ B6$ It is clear from this picture that the OSAT suppliers have a defined role to play in the future landscape for 2.5D & 3DIC packages: First in the back-end area, where their large infrastructure and expertise in advanced assembly & test will be key in the successful ramp-up of ever more complex 3D package products Secondly, in the middle-end area by establishing strategic collaborations with key IDM and wafer foundries in the IC industry, in order to partner tactically while leveraging the high capacity of investment of these powerful semiconductor chip companies thinning ~ B3.5B inspection Taken alone, the back-end space represents a clear opportunity for sustainable growth for major OSAT suppliers in this emerging 2.0 advanced packaging industry. However, this segment won t be accessible without the settlement of a viable ecosystem, including putting the back-end to middle-end processing together. Expect vertically integrated and collaborative models to emerge as the most successful in this game! W2W dicing C2W C2C / C2S underfill molding Final test BGA Copyrights Yole Développement SA. All rights reserved.

3DIC & TSV interconnects business update

3DIC & TSV interconnects business update ASET presentation. Infineon VTI Xilinx Synopsys Micron CEA LETI 2012 Copyrights Yole Developpement SA. All rights reserved. Fields of Expertise Yole Developpement