International Technology Roadmap for Semiconductors

Transcription

1 International Technology Roadmap for Semiconductors 2007 ITRS ORTC [12/5 Makuhari Japan ITRS Public Conference] A.Allan, Rev 0.0 (For IRC Review) 10/29/07 1

2 Agenda Moore s Law and More Definitions Technology Trends Update Models Update ITRS Function Size Models ITRS Functions/Chip Models ITRS Chip Size Models ITRS Technology Demand Tracking [SICAS] Summary 2

3 2007 ITRS Executive Summary Fig 5 [updated for 2007] Moore s Law & More [2007 add Definitions; Update Graphic] Traditional ORTC Models More Moore: Miniaturization Scaling (More Moore) [Geometrical & Equivalent scaling] Baseline CMOS: CPU, Memory, Logic 130nm 90nm 65nm 45nm 32nm 22nm.. V Functional More Diversification than Moore: Diversification (More than Moore) Analog/RF Information Processing Digital content System-on-chip (SoC) HV Power Passives Beyond CMOS HV Power Passives Sensors Actuators Interacting with people and environment Non-digital content System-in-package (SiP) Combining SoC and SiP: Higher Value Systems Biochips Continuing SoC and SiP: Higher Value Systems 3

4 Baseline CMOS 2007 ITRS Moore s Law and More Alternative Definition Graphic Memory RF HV Power More Moore Passives Sensors, Actuators More than Moore Bio-chips, Fluidics Computing & Data Storage Sense, interact, Empower Heterogeneous Integration System on Chip (SOC) and System In Package (SIP) Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC) 4

5 PIDS/FEP - Simplified Transistor Roadmap [Examples of Equivalent Scaling from ITRS PIDS/FEP TWGs] poly SiON metal high k gate stack electrostatic control bulk PDSOI planar FDSOI MuGFET MuCFET 3D stressors + substrate engineering + high µ materials 65nm 45nm 32nm 22nm [ ITRS DRAM/MPU Timing: 2007/ ] Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC) 5

6 2007 ITRS Definitions: More Moore and More than Moore 1. Scaling ( More Moore ) a. Geometrical (constant field) Scaling refers to the continued shrinking of horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers. b. Equivalent Scaling which occurs in conjunction with, and also enables, continued Geometrical Scaling, refers to 3-dimensional device structure ( Design Factor ) Improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip. 2. Functional Diversification ( More than Moore ) Functional Diversification refers to the incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law," but provide additional value to the end customer in different ways. The "Morethan-Moore" approach typically allows for the non-digital functionalities (e.g. RF communication, power control, passive components, sensors, actuators) to migrate from the system board-level into a particular package-level (SiP) or chip-level (SoC) potential solution. 6

7 2007 Definition of the Half Pitch - unchanged [No single-product node designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2 Poly Pitch DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Metal Pitch 8-16 Lines Typical flash Un-contacted Poly Typical DRAM/MPU/ASIC Metal Bit Line Source: 2005 ITRS - Exec. Summary Fig 2 7

8 Fig 3 Production Ramp-up Model and Technology Cycle Timing Volume (Parts/Month) 100M 10M 1M 100K 10K 1K Alpha Tool Development Beta Tool First Conf. Papers Production Tool Production First Two Companies Reaching Production Unchanged 200K 20K 2K Volume (Wafers/Month) Source: 2005 ITRS - Exec. Summary Fig 3 0 Months

9 ORTC Overview 2007 ITRS Summary of Updates ORTC Table 1a,b - Flash Poly (Un-contacted dense lines) 2-year Technology Cycle* (0.5x/4yrs) Extended to nm/2000; 130nm/2002; 90nm/2004; 65nm/2006; 45nm pull-in to 2008 Then return to 3-year Technology Cycle* 2 years ahead of DRAM DRAM M1 will NO LONGER be the standard TWG table technology header** 2007 ITRS Update DRAM 3-year cycle stagger-contacted Unchanged, However, Bits/chip delayed 1yr; 6f ; 56% Area Efficiency pull-in 2 yrs ORTC Table 1a,b - MPU/ASIC M1 Half-Pitch Trend Unchanged Stagger-contacted, same as DRAM 2.5-year Technology Cycle* (.5x/5yrs) 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM) Then continue on a 3-year Technology Cycle*, equal to DRAM ORTC Table 1a,b MPU/ASIC Printed Gate Length per FEP and Litho TWG ratio relationship to Final Physical Gate Length 2005 ITRS target for (3-year cycle* after 2005 Unchanged. **TWG table Product-specific technology trend driver header items, as required by TWGS, will be added in 2007 to individual TWG tables from ORTC Table 1a&b Chip Size/Function Size/Density Models [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)] are updated and aligned to the latest DRAM and Flash proposals Products: Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU; hp ASIC *Note: Cycle = time to 0.5x linear scaling every two cycle periods ~ 0.71x/ cycle 9

10 2007 ( 07-22) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle Year of Production Technology - Contacted M1 H-P (nm) 2000 [Actual] [Actual] Updated Year Technology Cycle [ 98-04] 3-Year Technology Cycle 2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 2yrs ahead of 45nm/ 08 Year of Production 2000 [Actual] [Actual] Technology Uncontacted Poly H-P (nm) IS: Year Technology Cycle [ ] Year Technology Cycle 2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal Year of Production [July 02] 2005 [July 08] Technology - Contacted M1 H-P (nm) 3-2-Yr Cycle] [130] 90 [ 65] Year Technology Cycle 3-Year Technology Cycle 10 11

11 Figure 8 ITRS Product Technology Trends ITRS Product Technology Trends - Half-Pitch, Gate-Length [DRAM &, MPU Unchanged; [Flash 2-yr cycle extended] plus extend all to 2022] Before X/3YR Past Future Product Half-Pitch, Gate-Length (nm) Flash 2YR Extended After X/2YR Flash Poly.71X/2YR MPU M1.71X/2.5YR MPU & DRAM M1 & Flash Poly.71X/3YR DRAM M1 1/2 Pitch MPU M1 1/2 Pitch (2.5-year cycle) Flash Poly 1/2 Pitch MPU Gate Length - Printed Gate Length.71X/3YR Nanotechnology (<100nm) Era Begins GLpr IS = x GLph MPUGate Length - Physical Year of Production ITRS Range 11

12 Cell, Logic Gate Size (um2 ) Figure 9 ITRS Product Function Size 1.E+01 1.E+00 1.E-01 DRAM 6f2 Pull-in to 06 1.E-02 1.E ITRS Product Function Size Trends - Cell Size, Logic Gate(4t) Size Flash: 4f 2 Last Design Physical Area Factor Improvement Flash cell area Reduced due to 2YR cycle Extension Past Future Logic Gate: NO Design Area Factor Improvement (Only Scaling) DRAM: 6f 2 is last Design Area Factor Improvement SRAM: gradual Design Area Factor Improvement Flash: 2 bits/cell = 2f 2 Equivalent Area Factor) 1.E Year of Production Flash 4 bits/cell 1f 2 Beginning ITRS Range [changes to DRAM and Flash; plus extend all to 2022] DRAM Cell Size (u2) MPU SRAM Cell Size (6t)(u2) MPU Gate Size (4t)(u2) Flash Cell Size (u2) SLC Flash Eqv.bit Size(u2) 2bit MLC (@ 2 MLC bits/physical cell area) Flash Eqv.bit Size(u2) 4bit MLC - New (@ 4 MLC bits/physical cell area) 12

13 Chip Size Trends 2007 ITRS Functions/Chip Model Product Functions/Chip [ Giga (10^9) - bits, transistors ] 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E ITRS Product Technology Trends - Functions per Chip (@Volume Production, Affordable Chip Size**) Flash Bits/Chip (Gbits) Multi-Level- Cell (4bit MLC) Flash Bits/Chip (Gbits) Multi-Level- Cell (2bit MLC) Flash Bits/Chip (Gbits) Single-Level- Cell (SLC ) DRAM Bits/Chip (Gbits) MPU GTransistors/Chip - highperformance (hp) MPU GTransistors/Chip - costperformanc (cp) Average Industry "Moores Law : 2x Functions/chip Per 2 Years ** Affordable Production Chip Size Targets: DRAM, Flash < 145mm 2 hp MPU < 310mm 2 cp MPU < 140mm 2 MPU ahead or = Moore s Law 2x Xstors/chip Per 2 years Thru E-04 1.E-05 1.E Year of Production Past Future ITRS Range ** Example Chip Size Targets: 1.1Gt P07h intro in 2004/620mm prod in 2007/310mm 2 ** Example Chip Size Targets: 0.39Gt P07c intro in 2004/280mm prod in 2007/140mm 2 13

14 Figure 10 ITRS Product Functions per Chip 1.E+03 1.E ITRS Product Technology Trends - Functions per Chip Flash MLC 4 bits/chip Added [DRAM and Flash Updated] Flash Bits/Chip (Gbits) Multi-Level-Cell (4bit MLC) Flash Bits/Chip (Gbits) Multi-Level-Cell (2bit MLC) Product Functions/Chip [ Giga (10^9) - bits, transistors ] 1.E+01 1.E+00 Flash SLC Bits/chip for 1-year Pull-in Flash Bits/Chip (Gbits) Single-Level-Cell (SLC ) DRAM Bits/Chip (Gbits) MPU GTransistors/Chip - high-performance (hp) 1.E-01 DRAM Bits/chip 1-year Delay; MPU GTransistors/Chip - cost-performanc (cp) 1.E Average Industry "Moores Law : 2x Functions/chip Per 2 Years Year of Production Past Future ITRS Range 14

15 Chip Size Trends 2005 ITRS DRAM Model Updated 2 Chips per Max Litho Field 2005 ITRS (4x): 417m2 (26x16) (mm2) M Bits/ 200 chip: 64M 100 1G Bits/ chip: 512M 256M 2G 4G 2G 2G 16G 568 8G 32G 64G 4G 8G 16G 32G 16G 128G 256G 4G 8G 32G 64G 16G 1T 128G DRAM Introduction Chip Size Sawada DRAM Production Chip Size IS 4 chips per Litho 572mm2 = 143mm2 (22x6.5) 5 chips per Litho DRAM Des mm2 = 141mm2 Factor: (22x6.4) 0 DRAM M1 HP: Year of Introduction and Production Past Future 32G extend to 2022; plus: DRAM chip size shrinks Due to one-year bits/chip generation Delay; 64G ITRS Range Max Litho Field 2005 ITRS (4x) : 834mm2 (26x32) Intro Cell Area Efficiency (CAE) = 73%-75% Prod Cell Area Efficiency (CAE) = 63%-56% 15

16 Chip Size Trends 2005 ITRS Flash Model - Updated 2005 Proposal 2005: ITRS Flash chip Size (NEW) Model (Allan) (Rev 1K, 06/23/05) 700 [ extend to 2022] Flash Intro Cell Area Efficiency (CAE) =TBD - no model (mm2) Pull-in 1yr & Shrink Flash Prod Cell Area Efficiency (CAE) = 67% Flash SLC Production Chip Size chips per Max Affordable Litho 572mm2 = 143mm2 100 (22x6.5) Flash 5 chips per Max Bits/chip: 64M 256M 1G 2G 4G 8G 16G 32G 64G 128G Affordable Litho DRAM Des. Factor: mm2 = 141mm2 0 Flash SLC DRAM Des.Factor: (22x6.4) HP WAS/IS: Flash: Year of Introduction and Production Past Future ITRS Range 16

17 2 Chips per Max Litho Field 2005 ITRS (4x): 417m2 (26x16) [ extend to 2022] Chip Size Trends 2005 ITRS MPU Model - unchanged % / 2yrs Chip Size Growth p02h 276Mt p04h 552Mt p07h 1.1Bt p10h 2.2Bt p13h 4.4Bt p16h p19h p22h p25h Max Litho Field 2005 ITRS (4x): 834mm2 (26x32) hp MPU = 82% SRAM Transistors, 18% Core Logic Transistors cp MPU = 58% SRAM Transistors, 42% Core Logic Transistors SRAM Cell Efficiency= 60% Logic Gate Efficiency = 50% MPU hp Production Chip Size MPU cp Production Chip Size MPU hp Introduction Chip Size MPU cp Introduction Chip Size (mm2) p98h 69Mt p00c 48Mt p00h 138Mt p02c 96Mt p00c 48Mt p02h 276Mt p04c 192Mt p02c 96Mt p10c 768Mt p04h773mt 552Mt p07c 384Mt 386Mt p04c 192Mt p13c 1.5Bt p07h 1.1Bt 8G p07c 386Mt p10h 2.2Bt p10c 773Mt p16c 3.1 p13c 1.5Bt p19c P22c 12.4Bt p22c p25c P22h 35.4Bt Affordable hp MPU prod Target: 310mm2 Affordable cp MPU prod Target: 140mm2 0 DRAM M1 HP: MPU: Year of Introduction and Production Past Future ITRS Range P22c 12.4Bt [2.5yr Technology Cycle ] 17

18 Feature Size (Half Pitch) (μm) Fig 4 Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution W.P.C = Total Worldwide Wafer Production Capacity; Source: SICAS* = 2005/06 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007 ITRS DRAM Contacted M1 Half-Pitch Target = 2007 ITRS Flash Uncontacted Poly Half Pitch Target 3-Year Cycle 2-Year Cycle Year 3-Yr Cycle ** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published 18by the Semiconductor Industry Association (SIA), as of August, The detailed data are available to the public online at the SIA website, [Updated Through 2Q07] 2007 ITRS MPU/ASIC (2.5-yr Cycle) SIA/SICAS Data**: 1-yr delay from ITRS Cycle Timing to >20% of MOS IC Capacity 2010 Note: The wafer production capacity data are plotted from the Semiconductor Industry Association (SIA) Semiconductor Industry Capacity Statistics (SICAS) 4Q data for each year, except 2Q data for The width of each of the production capacity bar corresponds to the MOS IC production start silicon area for that range of the feature size (y-axis). Data are based upon capacity if fully utilized. ITRS Technology Cycle >0.7μm 720nm μm 510nm μm 360nm μm 255nm μm 180nm μm 127nm <0.12μm 90nm Note: Includes <80nm split-out (ITRS 65nm) to be added In the 2008 ITRS Upcate

19 Will Capacity Demand Remain On A 2-Year Technology Cycle (.71) for <0.8u (65nm)? [SICAS Survey November results needed for 2008 Update] 100% MOS Capacity by Dimensions 4Q04-4Q06 ~40% of Total 2Q05-2Q07 ~22% of Total? >=0.7µ <0.7µ >=0.4µ WSpW x % 60% 40% 20% 0% 3Q 04 4Q Q 05 3Q 05 4Q Q 06 3Q 06 4Q 06 2-yrs to >20% of Total MOS for 0.71x Technology Reduction Cycle 07? 2Q 07 Source: SIA/SICAS Report: <0.4µ >=0.3µ <0.3µ >=0.2µ <0.2µ >=0.16µ <0.16µ <0.16µ >=0.12µ <0.12µ <0.8? [n-2] [130nm] SICAS split-out Available Nov 07 [n-1] [90nm] [n] [65nm]

20 SICAS 300mm Tracking 3Q07 Update: 17.4% YoY 43.0% YoY [100%] [38%] Q Wafer Starts per Week (1K) [100%] [44%] WSpW x1000 (8 inch equivalents) 2Q 3Q 4Q 2003 MOS Capacity MOS Capacity By by Wafer-size Size [Total MOS only 8 Equivalent] 11.8% CAGR 200mm/97 SICAS Tracking Begins (6yrs after Intro) <200mm 200mm 300mm 1991->2001: 10 years intro->intro Wafer Generation Q 3Q mm/04 (3yrs after Intro) 12.5% YoY 71% YoY 3Q 4Q 4Q 2Q 2Q 3Q 3Q 4Q 4Q 2Q 2Q 3Q 3Q 4Q 4Q 2Q 2Q : 300mm = 33% of Total MOS 200mm = 56% of Total MOS <200mm = 11% of Total MOS Source: SIA/SICAS Report:

21 ORTC Summary 2007 Renewal Flash Model un-contacted poly half-pitch Extended on 2-year cycle* to 2 years ahead of DRAM (contacted) in 2008, then 3-year cycle*. DRAM Model stagger-contacted M1 half-pitch unchanged from 2005 ITRS (3- year cycle* after 2004), however Bits/Chip shifted by one year; 6f2/ MPU M1 stagger-contact half-pitch unchanged on a 2.5-year cycle* through 2010/45nm, then 3-year cycle*. Printed MPU/ASIC Gate Length FEP and Litho TWGs ratio agreement, and Physical GL targets are both unchanged and on 3-year cycle* beginning New 2007 Moore s Law and More Definitions : Moore s Law (typically digital computing) Functional and Performance scaling is enabled by both Geometrical and also Equivalent scaling technologies Functional diversification (typically non-digital sensing, interacting) system boardlevel migration/miniaturization is enabled by system-in-package and system-on-chip Total MOS Capacity (SICAS) has been growing ~12% CAGR (SICAS), and 300mm Capacity Demand has ramped to 33% of Total MOS. Historical unchanged chip size models have been updated & connected to latest Product scaling rate model proposals, and include design factors, function size, and array efficiency targets The average of the industry product Moore s Law (2x/chip per 2 years) continues to be met throughout the latest ITRS timeframe [* ITRS Cycle definition = time to.5x linear scaling every two cycle periods] Industry Technology Capacity (SICAS) [3Q07 published status] continues on a on 2-year cycle rate at the leading edge. [plus lower Area efficiency 56% pull-in 2 years] 21

22 WSpW x % CAGR 3Q 04 4Q 04 MOS Capacity by Dimensions 05 2Q % CAGR 3Q 05 4Q Q 06 3Q 06 4Q Q 07 MOS Capacity by Dimensions 4Q04-4Q06 ~40% of Total 100% >=0.7µ <0.7µ >=0.4µ <0.4µ >=0.3µ <0.3µ >=0.2µ <0.2µ >=0.16µ <0.16µ <0.16µ >=0.12µ <0.12µ >=0.7µ <0.7µ >=0.4µ 80% <0.4µ >=0.3µ 60% <0.3µ >=0.2µ 40% <0.2µ >=0.16µ <0.16µ 20% <0.16µ >=0.12µ 0% 3Q 4Q 2Q 3Q 4Q 2Q 3Q 4Q 2Q <0.12µ Source: SIA/SICAS Report: WSpW x