Computer Architecture ELEC2401 & ELEC3441
|
|
- Ezra Dennis
- 5 years ago
- Views:
Transcription
1 Computer Architecture ELEC241 & ELEC3441 Lecture 4 Sigle Cycle Processor Dr. Hayde Kwok-Hay So Departmet of Electrical ad Electroic Egieerig Overview irst implemetatio the RISC-V ISA i this course More variatios to come Sigle cycle processor: Each istructio takes 1 cycle to complete Idealized memory Istataeous read Sigle cycle write Implemets base RV32 2 ull RISCV1Stage path (HW1) br/jmp jalr Jump argge BrJmp argge Brach CodGe br_eq? br_lt? br_ltu? 13 pc_sel val Istructio Mem Ist ir[31], ir[7], ir[3:25], ir[11:8]] ir[31:2] ir[24:2] ir[19:15] Bype Sig ed Iype Sig ed ile cotrol status registers wb_sel ir[11:7] rf_ ile e Op1Sel Aluu Decoder Sigals mem_rw mem_val Mem cpr_e tohost testrig_tohost RV32I RISC-V v2.1 specificatio Execute Stage 3 4
2 Hardre Elemets Combiatioal circuits Mux, Decoder,,... A A 1 A -1. Sel Mux lg() O Sychroous state elemets lipflop, ister, ister file, SRAM, DRAM E Clk D Q Clk E D Q A lg() Decoder. O O 1 O -1 A B OpSelect -, Sub,... - Ad, Or, or, Not,... - G, L, EQ, Zero,... Result Comp? ister E Clk D Q register... D 1 A -bit register ca be costructed by combiig Ds i parallel Each D resposible for read/write of 1 bit of the iput Shared cotrol sigal: Clock, reset, eable, Q 1 D 2 Q D -1 Q -1 D<-1:> D e Q Q<-1:> Edge-triggered: is sampled at the risig edge 5 6 ister ile Reads are combiatioal rd=regfile(ra) i the same cycle Writes take place at risig the clock edge Write oly take place if WE=1 at clock edge Read ess (ra) ad write ess () choose which register to read/write RISCV eeds a register file with 2 read ports ad 1 write port What happe i these cases? =! = 1! Readr1 Readr2 Writer Write Clock WE ister file 2R+1W rd2 Read1 Read2 ister ile Implemetatio reg 1 reg 31 2R + 1W, 32 registers, each 32 bits wide Decoder select 1 out of 32 register depedig o,, O writes: Oly 1 of the 32 register has WE=1 O reads: Oly 1 of the 32 register may output to rd{1,2} bus he same register may output to both ad rd2 bus (e.g. = ) reg rd
3 A Simple Model ress Write WriteEable Clock MAGIC RAM Read Reads ad writes are alys completed i oe cycle a Read ca be doe ay Vme (i.e. combiavoal) a Write is performed at the risig clock edge if it is eabled the write ess ad must be stable at the clock edge 32 Istructio Executio ExecuVo of a RISC-V istrucvo ivolves: 1. istrucvo fetch 2. decode ad register fetch 3. operavo 4. memory operavo (opvoal) 5. write back to register file (opvoal) + the computavo of the ext istruc:o ess Later i the course will preset a more realis:c model of memory 9 1 path: - Istructios ist Ist. Ist<19:15> Ist<24:2> Ist WriteE Write imig? path: -Imm Istructios ist Ist. ist<19:15> ist ist<31:2> WriteE Sig <31:25,14:12> rd () fuc () fuct7 fuct src2 src1 /SL/SLU dest OP src2 src1 AND/OR/OR dest OP src2 src1 SLL/SRL dest OP 1 src2 src1 ENGG3441 SUB/SRA - HS dest OP 11 ist<14:12> rd () op imm imm[11:] fuct I-immediate[11:] src I/SLI[U] dest OP-IMM I-immediate[11:] src ANDI/ORI/ORI dest OP-IMM 12
4 Coflicts i Mergig path Op2 Select If OODE== OP the op2sel = 1 else 1 2 ist Ist. <19:15> <24:2> <31:2> <31:25,14:12> <14:12> WriteE Sig Itroduce muxes fuct7 fuct3 R-type imm[11:] fuct3 I-type imm[11:5] fuct3 imm[4:] opcode S-type Quick Quiz If OODE== OP the op2sel = 1 else How do you implemet op2sel i hardre? opcode OP =? opcode OP =? 1 1 op2sel op2sel How do you implemet this? =? 13 Copyright , he ets of the Uiversity WriteE of Califoria. All rights reserved <19:15> fuct7 fuct7 <24:2> fuct3 fuct3 rd opcode R-type R-type imm[11:] imm[11:] fuct3 fuct3 rd opcode I-type I-type imm[11:5] imm[11:5] ist fuct3 fuct3 imm[4:] imm[4:] opcode opcode S-type S-type imm[12 1:5] imm[12 1:5] fuct3 fuct3 imm[4:1 11] imm[4:1 11] opcode opcode SB-type SB-type Ist. imm[31:12] imm[31:12] rd opcode U-type U-type imm[2 1: :12] imm[2 1: :12] rd opcode UJ-type UJ-type <31:2> Sig RV32I RV32I Base Base Istructio Istructio Set Set imm[31:12] imm[31:12] rd rd LUI LUI rd,imm rd,imm imm[31:12] imm[31:12] rd rd AUI AUI rd,imm rd,imm imm[2 1: :12] imm[2 1: :12] rd rd JAL JAL rd,imm rd,imm imm[11:] imm[11:] rd rd JALR JALR rd,,imm rd,,imm imm[12 1:5] imm[4:1 11] 1111 BEQ,,imm imm[12 1:5] 1 imm[4:1 11] 1111 BNE,,imm imm[12 1:5] 1 imm[4:1 11] 1111 BL,,imm imm[12 1:5] 11 imm[4:1 11] 1111 BGE,,imm op2sel imm[12 1:5] 11 imm[4:1 11] 1111 BLU,,imm / Imm imm[12 1:5] 111 imm[4:1 11] 1111 BGEU,,imm imm[11:] rd 11 LB rd,,imm fuct7 fuct3 R-type imm[11:] 1 rd 11 LH imm[11:] imm[11:] 1 fuct3 rd rd 11 opcode LW rd,,immi-type imm[11:5] imm[11:] 1 fuct3 rd imm[4:] 11 opcode LBU rd,,imm S-type imm[11:] 11 rd 11 LHU rd,,imm imm[11:5] imm[4:] 111 SB,,imm imm[11:5] 1 imm[4:] 111 SH,,imm imm[11:5] 1 imm[4:] 111 SW,,imm imm[11:] rd 111 I rd,,imm Determiig imm[11:] 1 fuctios rd 111 SLI rd,,imm imm[11:5] imm[11:] 1 11 imm[4:] rd SW SLIU,,imm rd,,imm imm[11:] 1 rd 111 I ORI rd,,imm rd,,imm imm[11:] 1 11 rd 111 SLI ORI rd,,imm imm[11:] 111 rd 111 ANDI rd,,imm shamt 1 rd 111 SLLI rd,,shamt shamt 11 rd 111 SRLI rd,,shamt 1 shamt 11 rd 111 SRAI rd,,shamt rd 1111 rd,, 1 rd 1111 SUB rd,, 1 rd 1111 SLL rd,, 1 rd 1111 SL rd,, 11 rd 1111 SLU rd,, All basic iteger R-R istructios 1 rd have opcode 1111 OR = OP rd,, 11 rd 1111 SRL rd,, ( 1111 ) 1 11 rd 1111 SRA rd,, oly fuct3 ad fuct7 are eeded 11 rd to determie 1111 eeded OR rd,, fuctio: 111 rd 1111 AND rd,, pred succ 1111 ENCE E.g. è, 1èShiftLeft, 1èOR,1èSub, 1111 ENCE.I SCALL Immediate istructios 1 requires the same SBREAK fuctio, but 11 has slightly dieret ecodig 1 rd RDCYCLE rd rd RDIME rd rd RDINSRE rd I is same as, except o eed to check for Sub i fuct7 opcode = OP-IMM ( 111 ) Need opcode to help determie fuctio More cases like these come up later
5 Istructios path ist Ist. <19:15> <24:2> <31:2> <3,14:12,6:> WriteE Sig I Load Istructios Use for ess calculatio Mux to select for regfile: mem or imm[11:] f3 oset[11:] base width dest LOAD ist Ist. base oset WriteE Sig Load: (dest) ß M[(base) + oset] / Mem / Imm fuct7 fuct3 R-type imm[11:] fuct3 I-type imm[11:5] fuct3 imm[4:] opcode S-type Store Istructios Also use for ess calculatio No eed to write back to regfile S imm[11:5] f3 imm[4:] opcode oset[11:5] src base width oset[4:] SORE Need to tell memory it is a write è Set to 1 ist Ist. base oset WriteE Sig Store: M[(base) + oset] ß (src) / Mem 17 RISC-V Coditioal Braches imm[12] SB imm[1:5] fuct3 imm[4:1] opcode oset[12,1:5] src2 src1 BEQ/BNE oset[11,4:] BL[U] BGE[U} Requires: 1. Logic to compare register values ( ad ) 2. path to calculate brach target ess relative to Curret implemetatio: dedicated logic for both 1 ad 2 Dedicated compariso logic (=, <, [, ]) Dedicated adder for jump target calculatio May use for (2) above Performace tradeo imm[11] if ( BR_OP ) the jump to + brach_imm BRANCH
6 Coditioal Braches (BEQ/BNE/BL/BGE/BLU/BGEU) Sel br ist Ist. WrE Brach Imm Br Logic 21 RISC-V Ucoditioal JAL Sel brjmp ist Ist. imm[2] UB WrE Brach Imm Jump Imm Imm[11] imm[1:1] imm[19:12] Br Logic oset[2:1] dest JAL jump to + j_imm; rd ß JALR I oset[11:] base dest JALR Sel imm[11:] f3 brjmp jmpreg ist Ist. oset WrE Sig Br Logic jump to imm + (); rd ß +4 Hardwired is pure Combiatioal Logic op code combiavoal logic Aluuc WriteE Sel Decodig istructio determies the settig of various muxes ad fuctio Simple decodig helps to make faster hardre 23 24
7 Hardwired able (Excerpt) Istructio Aluuc WriteE Sel SUB I SLL LW SW BEQ JAL JALR RS2 RS2 IMI RS2 IMI IMS IMB IMJ IMI SUB SLL MEM :, {I,B,J}-type immediate IM{I, B, J} Aluuc:, Sub, Shift, OR, etc : what values to write to rd N N N /BA JA JRA Sigle-Cycle Hardwired We will assume clock period is suicietly log for all of the followig steps to be completed : 1. Istructio fetch 2. Decode ad register fetch 3. operatio 4. fetch if required 5. ister write-back setup time t C > t Ietch + t Retch + t + t DMem + t RWB At the risig edge of the followig clock, the, register file ad memory are updated ull RISCV1Stage path (HW1) br/jmp jalr pc_sel val +4 Istructio Mem +4 Ist ir[31], ir[7], ir[3:25], ir[11:8]] ir[31:2] ir[24:2] ir[19:15] Jump argge BrJmp argge Bype Sig ed Iype Sig ed ile Decoder Sigals Brach CodGe Op1Sel br_eq? br_lt? Aluu br_ltu? mem_rw mem_val cotrol status registers wb_sel ir[11:7] ile Mem cpr_e tohost rf_ e testrig_tohost Ackowledgemets hese slides cotai material developed ad copyright by: Arvid (MI) Krste Asaovic (MI/UCB) Joel Emer (Itel/MI) James Hoe (CMU) Joh Kubiatowicz (UCB) David Patterso (UCB) MI material derived from course UCB material derived from course CS152, CS252 Execute Stage 27 28
Computer Architecture ELEC2401 & ELEC3441
Computer Architecture ELEC241 & ELEC3441 Lecture 4 Sigle Cycle Processor Dr. Hayde Kwok-Hay So Departmet of Electrical ad Electroic Egieerig Overview irst implemetatio the RISC-V ISA i this course More
More informationLecture 4 - Pipelining
CS 152 Computer Architecture and Engineering Lecture 4 - Pipelining John Wawrzynek Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~johnw
More informationComputer Architecture ELEC3441
Computer Architecture ELEC3441 RISC vs CISC Iron Law CPUTime = # of instruction program # of cycle instruction cycle Lecture 5 Pipelining Dr. Hayden Kwok-Hay So Department of Electrical and Electronic
More informationLecture 08: RISC-V Single-Cycle Implementa9on CSE 564 Computer Architecture Summer 2017
Lecture 08: RISC-V Single-Cycle Implementa9on CSE 564 Computer Architecture Summer 2017 Department of Computer Science and Engineering Yonghong Yan yan@oakland.edu www.secs.oakland.edu/~yan 1 Acknowledgements
More informationReview: ISA. Review: Compiling Applications. Computer Architecture ELEC3441. Instruction Set Architecture (1) Computer Architecture: HW/SW Interface
Computer Architecture ELEC3441 Instruction Set Architecture (1) 2 nd Semester, 2017-18 Dr. Hayden Kwok-Hay So Review: ISA n Instruction set architecture defines the user observable behavior a processor
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter The Processor Part A path Desig Itroductio CPU performace factors Istructio cout Determied by ISA ad compiler. CPI ad
More informationECE 552 / CPS 550 Advanced Computer Architecture I. Lecture 4 Reduced Instruction Set Computers
ECE 552 / CPS 550 Advanced Computer Architecture I Lecture 4 Reduced Instruction Set Computers Benjamin Lee Electrical and Computer Engineering Duke University www.duke.edu/~bcl15 www.duke.edu/~bcl15/class/class_ece252fall11.html
More informationSimple Instruction Pipelining
Simple Instruction Pipelining Krste Asanovic Laboratory for Computer Science Massachusetts Institute of Technology Processor Performance Equation Time = Instructions * Cycles * Time Program Program Instruction
More informationEC 513 Computer Architecture
EC 513 Computer Architecture Single-cycle ISA Implementation Prof. Michel A. Kinsy Computer System View Processor Applications Compiler Firmware ISA Memory organization Digital Design Circuit Design Operating
More informationLecture 3: Single Cycle Microarchitecture. James C. Hoe Department of ECE Carnegie Mellon University
8 447 Lecture 3: Single Cycle Microarchitecture James C. Hoe Department of ECE Carnegie Mellon University 8 447 S8 L03 S, James C. Hoe, CMU/ECE/CALCM, 208 Your goal today Housekeeping first try at implementing
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationComputer Architecture ELEC3441
CPU-Memory Bottleeck Computer Architecture ELEC44 CPU Memory Lecture 8 Cache Dr. Hayde Kwok-Hay So Departmet of Electrical ad Electroic Egieerig Performace of high-speed computers is usually limited by
More informationChapter 4 The Datapath
The Ageda Chapter 4 The Datapath Based o slides McGraw-Hill Additioal material 24/25/26 Lewis/Marti Additioal material 28 Roth Additioal material 2 Taylor Additioal material 2 Farmer Tae the elemets that
More informationLecture 2: RISC V Instruction Set Architecture. Housekeeping
S 17 L2 1 18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University Housekeeping S 17 L2 2 Your goal today get bootstrapped on RISC V RV32I to start
More informationLecture 2: RISC V Instruction Set Architecture. James C. Hoe Department of ECE Carnegie Mellon University
18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L02 S1, James C. Hoe, CMU/ECE/CALCM, 2018 Your goal today Housekeeping get bootstrapped
More informationLecture 3 - From CISC to RISC
CS 152 Computer Architecture and Engineering Lecture 3 - From CISC to RISC Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory http://inst.eecs.berkeley.edu/~cs152
More informationELEC3441: Computer Architecture Second Semester, Feb 23, Quiz 2
ELEC3441: Computer Architecture Second Semester, 2016 17 Feb 23, 2017 Quiz 2 Name: University Number: Instructions: Time Allowed: 30 mins. Answer ALL questions. This is a close book quiz. No notes, books,
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationCS252 Spring 2017 Graduate Computer Architecture. Lecture 6: Out-of-Order Processors
CS252 Sprig 2017 Graduate Computer Architecture Lecture 6: Out-of-Order Processors Lisa Wu, Krste Asaovic http://ist.eecs.berkeley.edu/~cs252/sp17 WU UCB CS252 SP17 2 WU UCB CS252 SP17 Last Time i Lecture
More informationAnne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B
Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,
More informationRISC-V Assembly and Binary Notation
RISC-V Assembly and Binary Notation L02-1 Course Mechanics Reminders Course website: http://6004.mit.edu All lectures, videos, tutorials, and exam material can be found under Information/Resources tab.
More informationImplementing RISC-V Interpreter in Hardware
Implementing RISC-V Interpreter in Hardware Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology October 16, 2018 MIT 6.004 Fall 2018 L11-1 Instruction interpreter
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Single-Cycle Disadvantages & Advantages
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 4 The Processor Pipeliig Sigle-Cycle Disadvatages & Advatages Clk Uses the clock cycle iefficietly the clock cycle must
More informationISA and RISCV. CASS 2018 Lavanya Ramapantulu
ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program
More informationC 1. Last Time. CSE 490/590 Computer Architecture. ISAs and MIPS. Instruction Set Architecture (ISA) ISA to Microarchitecture Mapping
CSE 49/59 Computer Architecture ISAs and MIPS Last Time Computer Architecture >> ISAs and RTL Comp. Arch. shaped by technology and applications Computer Architecture brings a quantitative approach to the
More informationChapter 5: Processor Design Advanced Topics. Microprogramming: Basic Idea
5-1 Chapter 5 Processor Desig Advaced Topics Chapter 5: Processor Desig Advaced Topics Topics 5.3 Microprogrammig Cotrol store ad microbrachig Horizotal ad vertical microprogrammig 5- Chapter 5 Processor
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationCMSC Computer Architecture Lecture 3: ISA and Introduction to Microarchitecture. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 3: ISA ad Itroductio to Microarchitecture Prof. Yajig Li Uiversity of Chicago Lecture Outlie ISA uarch (hardware implemetatio of a ISA) Logic desig basics Sigle-cycle
More informationAgenda. Recap: Adding branches to datapath. Adding jalr to datapath. CS 61C: Great Ideas in Computer Architecture
/5/7 CS 6C: Great Ideas in Computer Architecture Lecture : Control & Operating Speed Krste Asanović & Randy Katz http://insteecsberkeleyedu/~cs6c/fa7 CS 6c Lecture : Control & Performance Recap: Adding
More informationECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something
More informationA Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationCSC 220: Computer Organization Unit 11 Basic Computer Organization and Design
College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture:
More informationRTL Model of a Two-Stage MIPS Processor
RTL Model of a Two-Stage MIPS Processor 6.884 Laboratory February 4, 5 - Version 45 Introduction For the first lab assignment, you are to write an RTL model of a two-stage pipelined MIPS processor using
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationCh 5: Designing a Single Cycle Datapath
Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic:
More informationThe Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath
The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationCS 61C: Great Ideas in Computer Architecture. Lecture 13: Pipelining. Krste Asanović & Randy Katz
CS 61C: Great Ideas in Computer Architecture Lecture 13: Pipelining Krste Asanović & Randy Katz http://inst.eecs.berkeley.edu/~cs61c/fa17 RISC-V Pipeline Pipeline Control Hazards Structural Data R-type
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationMidterm. Sticker winners: if you got >= 50 / 67
CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.
More informationLecture 10: Simple Data Path
Lecture 10: Simple Data Path Course so far Performance comparisons Amdahl s law ISA function & principles What do bits mean? Computer math Today Take QUIZ 6 over P&H.1-, before 11:59pm today How do computers
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationReview: Abstract Implementation View
Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationCS 152 Computer Architecture and Engineering. Lecture 3 - From CISC to RISC
CS 152 Computer Architecture and Engineering Lecture 3 - From CISC to RISC Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationLaboratory Exercise 6 Pipelined Processors 0.0
Laboratory Exercise 6 Pipelined Processors 0.0 Goals After this laboratory exercise, you should understand the basic principles of how pipelining works, including the problems of data and branch hazards
More informationece4750-tinyrv-isa.txt
========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :
More informationComputer Architecture (TT 2011)
Computer Architecture (TT 2011) The MIPS/DLX/RISC Architecture Daniel Kroening Oxford University, Computer Science Department Version 1.0, 2011 Outline ISAs Overview MIPS/DLX Instruction Formats D. Kroening:
More informationCS61C : Machine Structures
CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn
More informationAnne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]
Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Understanding the basics of a processor We now have the technology to build a CPU! Putting it all
More informationLecture 7 Pipelining. Peng Liu.
Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More informationRecap: A Single Cycle Datapath. CS 152 Computer Architecture and Engineering Lecture 8. Single-Cycle (Con t) Designing a Multicycle Processor
CS 52 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con t) Designing a Multicycle Processor February 23, 24 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs52/
More informationCS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats
CS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats Instructors: Krste Asanović and Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/fa17 9/14/17 Fall 2017 - Lecture #7 1 Levels of
More information9/14/17. Levels of Representation/Interpretation. Big Idea: Stored-Program Computer
CS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats Instructors: Krste Asanović and Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/fa17 Fall 2017 - Lecture #7 1 Levels of Representation/Interpretation
More informationElementary Educational Computer
Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified
More informationPipelined CPUs. Study Chapter 4 of Text. Where are the registers?
Pipelined CPUs Where are the registers? Study Chapter 4 of Text Second Quiz on Friday. Covers lectures 8-14. Open book, open note, no computers or calculators. L17 Pipelined CPU I 1 Review of CPU Performance
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More informationCS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)
CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,
More informationCS250 Section 4. 9/21/10 Yunsup Lee. Image Courtesy: Tilera
CS250 Section 4 9/21/10 Yunsup Lee Image Courtesy: Tilera Any questions on lab 2 & lab 3? Doing okay with gate-level simulations? Announcements I m still working to get physical libraries for lab 3 work
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationL19 Pipelined CPU I 1. Where are the registers? Study Chapter 6 of Text. Pipelined CPUs. Comp 411 Fall /07/07
Pipelined CPUs Where are the registers? Study Chapter 6 of Text L19 Pipelined CPU I 1 Review of CPU Performance MIPS = Millions of Instructions/Second MIPS = Freq CPI Freq = Clock Frequency, MHz CPI =
More informationLecture 3 - From CISC to RISC
CS 152 Computer Architecture and Engineering Lecture 3 - From CISC to RISC John Wawrzynek Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~johnw
More informationEEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC
More informationCS 110 Computer Architecture Single-Cycle CPU Datapath & Control
CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides
More informationDesign for a simplified DLX (SDLX) processor Rajat Moona
Design for a simplified DLX (SDLX) processor Rajat Moona moona@iitk.ac.in In this handout we shall see the design of a simplified DLX (SDLX) processor. We shall assume that the readers are familiar with
More informationR-type Instructions. Experiment Introduction. 4.2 Instruction Set Architecture Types of Instructions
Experiment 4 R-type Instructions 4.1 Introduction This part is dedicated to the design of a processor based on a simplified version of the DLX architecture. The DLX is a RISC processor architecture designed
More informationA Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Announcements! HW2 available later today HW2 due in one week and a half Work alone
More informationEECS 151/251A: SPRING 17 MIDTERM 2 SOLUTIONS
University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey G. Alexandrov, N. Narevsky, V. Iyer MoWe 4-5:30pm Mo, Oct. 2, 6:00-7:30pm EECS 151/251A:
More informationEE108B Lecture 3. MIPS Assembly Language II
EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework
More informationECE 2300 Digital Logic & Computer Organization. More Single Cycle Microprocessor
ECE 23 Digital Logic & Computer Organization Spring 28 More Single Cycle Microprocessor Lecture 6: HW6 due tomorrow Announcements Prelim 2: Tues April 7, 7:3pm, Phillips Hall Coverage: Lectures 8~6 Inform
More informationLecture 6 Datapath and Controller
Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex
More informationRiSC-16 Sequential Implementation
RiSC-16 Sequential Implementation ENEE 446: Digital Computer Design, Fall 2000 Prof. Bruce Jacob This paper describes a sequential implementation of the 16-bit Ridiculously Simple Computer (RiSC-16), a
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationCharacter Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21
2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...
More informationECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath
ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath
More informationMore CPU Pipelining Issues
More CPU Pipelining Issues What have you been beating your head against? This pipe stuff makes my head hurt! Important Stuff: Study Session for Problem Set 5 tomorrow night (11/11) 5:30-9:00pm Study Session
More informationHomework 1 (r1.0) Due: Part (A) Feb, 2018, 11:55pm Part (B) Feb, 2018, 11:55pm
Second Semester, 2017 18 Homework 1 (r1.0) Due: Part (A) -- 28 Feb, 2018, 11:55pm Part (B) -- 28 Feb, 2018, 11:55pm Instruction: Submit your answers electronically through Moodle. There are 3 major parts
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationare Softw Instruction Set Architecture Microarchitecture are rdw
Program, Application Software Programming Language Compiler/Interpreter Operating System Instruction Set Architecture Hardware Microarchitecture Digital Logic Devices (transistors, etc.) Solid-State Physics
More informationNon-Pipelined Processors
Constructive Computer Architecture: Non-Pipelined Processors Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology L10-1 Single-Cycle RISC Processor As an illustrative
More informationDescription of Single Cycle Computer (SCC)
Descriptio of Sigle Cycle Computer (SCC) Refereces: Chapter 9 of M. Morris Mao ad Charles Kime, Logic ad Computer Desig Fudametals, Pearso Pretice Hall, 4 th Editio, 28. Overview Part Datapaths Itroductio
More informationVerilog RTL for a Two-Stage SMIPSv2 Processor
Verilog RTL for a Two-Stage SMIPSv2 Processor 6.375 Laboratory 1 February 23, 2006 For the first lab assignment, you are to write an RTL model of a two-stage pipelined SMIPSv2 processor using Verilog.
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local
More informationCS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationAppendix D. Controller Implementation
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Appedix D Cotroller Implemetatio Cotroller Implemetatios Combiatioal logic (sigle-cycle); Fiite state machie (multi-cycle, pipelied);
More information