Compilation of Parametric Dataflow Applications for Software-Defined-Radio-Dedicated MPSoCs

Transcription

1 Compilation of Parametric Dataflow Applications for Software-Defined-Radio-Dedicated MPSoCs PhD work of Mickael Dardaillon Mickaël Dardaillon, Kevin Marquet (Citi), Tanguy Risset (Citi), Jérôme Martin (Cea Leti), Henri-Pierre Charles (CEA List) June 24th, 2016

2 2 / 39 Evolution of telecommunication protocols data rate (kbps) G 3G 4G 2G 3G Wi-Fi Bluetooth Wi-Fi Bluetooth year

3 2 / 39 Evolution of telecommunication protocols data rate (kbps) G 3G 4G SDR Wi-Fi Bluetooth year

4 3 / 39 4G LTE-Advanced: Downlink 1 frame (10 ms) 1 sub-frame (1 ms)

5 3 / 39 4G LTE-Advanced: Downlink 1 frame (10 ms) 1 sub-frame (1 ms) subcarriers (20 MHz) OFDM Symbols Control Data User 1 User 2 User 3

6 3 / 39 4G LTE-Advanced: Downlink 1 frame (10 ms) 1 sub-frame (1 ms) MIMO: 4 2 antennas 2048 subcarriers (20 MHz)... Control Data User 1 LTE throughput: 1.4 Gbps LTE-Advanced: 7 Gbps Latency: 2 ms Power budget: 500 mw User 2 User 3 14 OFDM Symbols

7 4 / 39 Context What is an SDR software?

8 Context What is an SDR software? Baseband processing in software ZigBee... LTE Advanced Constraints Computing power GFLOPS Reconfiguration time < 100µs Consumption < 500mW RF Frontend 1 FFT CFO correction AGC + synchronization CFO estimation channel estimation MIMO decoding Demodulation RF Frontend 2 FFT CFO correction Architecture independent SDR Deinterleaving 4 / 39

9 5 / 39 Context What is an SDR software? What is an SDR hardware platform?

10 Context What is an SDR software? What is an SDR hardware platform? oftware-defined Radio 2619 P words wide Vector memory 1wordwide EVP16? VLIW Vector Processor ector register file Scalar RF Vector FU Scalar FU ric vector-processor architecture. Program memory VLIW controller ACU 16 words wide 1wordwide Vector memory 16 vector registers 32 scalar regs. Load/store unit Load/store U ALU ALU MAC/shift unit MAC U Shuffleunit 8wordswide 1wordwide Intravector unit ector memory Code generation unit AXU vectorregisters 4scalarregs. Figure 8: The EVP architecture. 5 / 39

11 ed i Context Programming Model for SDR Micro-Scheduling Experimentations FU FU FUon Magali FU RF RF RF RF wit Conclusion the vid Context mo FU FU FU FU RF RF RF RF of f acc FU FU FU FU the RF RF RF RF blo CGA View What is an SDR software? What is an SDR hardware platform? EVP16? VLIW Vector Processor SB3500? DSP Control Processor Configuration Memor [FIG4] IMEC s ADRES processor in the BEAR platform. icache SBX Memory IO and Other Interfaces SBX Complex HSN Memory Subsystem IO Subsystem Buses Core 3 SHB HSN 4 AMBA ARM DMA Device Controller [FIG5] Sandbridge SB3500 platform architecture. Core 2 SHB SHB Core 1 Each of the three Sandblaster cores has support for icache SBX Memory IO and Other Interfaces IO and Other Interfaces SBX Memory icache VL CGA Section plat allo diff the ST- PRO The con five ope on bot ism mu the how por AR MIC ARM plat sor bas con turbo coprocessor for 5 / 39

12 5 / 39 Context What is an SDR software? What is an SDR hardware platform? EVP16? MOD mod DMA dma4 DSP dsp4 OFDM ofdm3 OFDM ofdm4 VLIW Vector Processor SB3500? DSP Control Processor Magali? Configurable Units NoC DMA dma1 DSP dsp1 OFDM ofdm1 OFDM ofdm2 ARM arm DMA dma2 DSP dsp DSP dsp3 DMA dma3 DMA dma5 DSP dsp5 DEMOD demod LDPC ldpc TURBO turbo WIFLEX wiflex

13 5 / 39 Context What is an SDR software? What is an SDR hardware platform? EVP16? VLIW Vector Processor SB3500? DSP Control Processor Magali? Configurable Units NoC... No unified hardware platform model for SDR. Problem Statement: how to program and compile a telecommunication protocol to an heterogeneous MPSoC?

14 Magali SDR LTE demonstrator [Clermidy et al., 09] Power consumption: 231mW 6 / 39

15 Magali SDR DSP dsp4 DSP dsp1 DSP dsp3 DSP dsp5 DSP dsp2 LTE demonstrator [Clermidy et al., 09] Power consumption: 231mW 6 / 39

16 Magali SDR MOD mod DSP dsp4 OFDM ofdm3 OFDM ofdm4 DSP dsp1 LDPC ldpc OFDM ofdm1 DSP dsp3 DSP dsp5 TURBO turbo OFDM ofdm2 DSP dsp2 DEMOD demod WIFLEX wiflex LTE demonstrator [Clermidy et al., 09] Power consumption: 231mW 6 / 39

17 Magali SDR MOD mod DMA dma4 DSP dsp4 OFDM ofdm3 OFDM ofdm4 DSP dsp1 DMA dma5 LDPC ldpc DMA dma1 OFDM ofdm1 DMA dma2 DSP dsp3 DSP dsp5 TURBO turbo OFDM ofdm2 DSP dsp2 DMA dma3 DEMOD demod WIFLEX wiflex LTE demonstrator [Clermidy et al., 09] Power consumption: 231mW 6 / 39

18 7 / 39 Outline Context SDR software? Programming Model for SDR Dataflow Model of Computation Input Format Dataflow Refinement and Buffer Verification Mapping and Scheduling Micro-Scheduling Experimentations on Magali Code Generation Experimental Results Conclusion

19 8 / 39 State of the Art in SDR Programming Imperative Concurrent Platform ExoCHI [Wang et al., 07] BEAR [Derudder et al., 09] Language OpenMP + C Matlab + C Dataflow Platform Simulink LabView GNU Radio RVC-CAL [Lucarz et al., 08] DiplodocusDF [Gonzalez-Pina et al., 12] MAPS [Castrillon et al., 13] Language Python + C XML + C UML C like

20 9 / 39 Static Dataflow (SDF) [Lee et al., 87] Src Decod 1 Ctrl

21 10 / 39 Phase Approach with Static Dataflow Src Decod 1 Ctrl Src Decod Sink... Src Decod Sink Src Decod Sink

22 11 / 39 Dynamic Dataflow (DDF) [Buck, 93] SDF Analysable KPN DDF Expressive Kahn Process Network (KPN) [Kahn, 74]

23 11 / 39 Dynamic Dataflow (DDF) [Buck, 93] SDF MCDF SADF PiMM SPDF BPDF KPN DDF Analysable Expressive Scenario Aware DataFlow (SADF) [Theelen et al., 06] Mode Controlled DataFlow (MCDF) [Moreira et al., 12] Schedulable Parametric DataFlow (SPDF) [Fradet et al., 12] Parameterized and Interfaced dataflow Meta-Model (PiMM) [Desnos et al., 13] Boolean Parametric DataFlow (BPDF) [Bebelis et al., 13] Kahn Process Network (KPN) [Kahn, 74]

24 12 / 39 Schedulable Parametric DataFlow (SPDF) Src Ctrl Decod 1 [Fradet et al., 12] Model of Computation Analysis Quasi-Static Scheduling

25 12 / 39 Schedulable Parametric DataFlow (SPDF) Src Ctrl Decod 1 set p[1] p 10 p 10 Decod 2 Sink [Fradet et al., 12] Model of Computation Analysis Quasi-Static Scheduling...

26 Parametric DataFlow Format (PaDaF) Src Ctrl Decod 1 10 set p[1] p p 10 Decod 2 Sink Actor specification class Decod: public Actor{ PortIn<int> in; PortOut<int> out; ParamIn p; void compute() { [...] out.push(res, p); Graph specification Src src; Decod decod[2]; [...] for(int i=0; i<2; i++) { decod[i].in <= src.out[i]; 13 / 39

27 Front End Implementation Front End PaDaF (C++) C++ Front End (CLang) LLVM IR Graph Construction Graph + LLVM IR SDR Programming Model Propose SPDF for SDR C++ input format [IWCMC 12, IGI 14] Front End Based on LLVM framework Derived from SystemC analysis [Marquet et al., 10] Static graph structure [CASES 14] 14 / 39

28 15 / 39 Outline Context SDR software? Programming Model for SDR Dataflow Model of Computation Input Format Dataflow Refinement and Buffer Verification Mapping and Scheduling Micro-Scheduling Experimentations on Magali Code Generation Experimental Results Conclusion

29 16 / 39 SDF Scheduling Decod 1 Ctrl Src Decod Sink Iteration vector: (Src; Decod 1 ; Ctrl; (Decod 2 ) 10 ; (Sink) 5)

30 17 / 39 SPDF Scheduling [Fradet et al., 12] Src Ctrl Decod 1 10 set p[1] p p 10 Decod 2 Sink Iteration vector: (Src; Decod 1 ; Ctrl; (Decod 2 ) 10 ; (Sink) p)

31 18 / 39 SPDF Mapping Src Decod Decod 2 p p 1 10 Ctrl set p[1] Sink DEMOD demod ARM arm DMA dma1 DMA dma2

32 18 / 39 SPDF Mapping Src dma Decod 1 10 Decod 2 p p 1 10 arm Ctrl set p[1] Sink demod dma2 DEMOD demod ARM arm DMA dma1 DMA dma2

33 19 / 39 SPDF Quasi-Static Scheduling Src dma Decod 1 10 Decod 2 p p 1 10 arm Ctrl set p[1] Sink demod dma2 S(dma1) = (Src) S(arm) = (Ctrl; set(p)) S(demod) = ( Decod 1 ; get(p); (Decod 2 ) 10) S(dma2) = (get(p); (Sink) p )

34 20 / 39 SPDF Symbolic Execution dma1 Src demod arm D1 (D2) 10 Ctrl dma2 (Sink) p Time S(dma1) = (Src) S(arm) = (Ctrl; set(p)) S(demod) = ( Decod 1 ; get(p); (Decod 2 ) 10) S(dma2) = (get(p); (Sink) p )

35 21 / 39 SPDF Buffer Sizing arm Src dma1 [10] [100] 10 1 [1] Decod 1 1 p 10 Decod 2 p[10*p max ] 10 Ctrl set p[1] Sink demod dma2 Problem: overestimates buffer size e.g. Magali FFT size: 2048 Buffer size: 16

36 22 / 39 SPDF Model Refinement arm Src dma [10] [10] 10 Decod Decod 2 p [1] 1 p [p max ] 10 Ctrl set p[1] Sink demod dma2 Src::compute() { [...] out[1].push(ctrl, 10); for(int i=0; i<10; i++) out[2].push(data[i],10); } Idea: model each individual data communication Micro-Scheduling

37 23 / 39 Micro-Scheduling: an Example dma1 demod arm Src D1 (D2) 10 Ctrl dma2 µs(src) = µs(d 2 ) = µs(sink) = (Sink) p Time ) (push Src,D1 (10); push Src,D2 (10) 10 ) (pop Src,D2 (10); push D2,Sink ) (pop (p) D2,Sink (1)10

38 24 / 39 Buffer Sizing Verification How to verify buffer sizes using micro-schedules?

39 Buffer Sizing Verification How to verify buffer sizes using micro-schedules? Proposed Verification Method Based on Model Checking Derived from buffer minimization [Geilen et al., 05] Model Schedule Buffer sizes + Micro-Schedule + Parameter values Model Checker SPIN Check for deadlocks 24 / 39

40 Micro-Scheduling Implementation Front End PaDaF (C++) C++ Front End (CLang) LLVM IR Graph Construction Back End Mapping Scheduling Buffer Verification (SPIN) Micro-Scheduling SPDF model refinement Sequential communications Buffer Verification Model checking Model generation [CASES 14] Graph + LLVM IR 25 / 39

41 26 / 39 Outline Context SDR software? Programming Model for SDR Dataflow Model of Computation Input Format Dataflow Refinement and Buffer Verification Mapping and Scheduling Micro-Scheduling Experimentations on Magali Code Generation Experimental Results Conclusion

42 Code Generation Graph + LLVM IR OFDM DEMOD TURBO DSP DMA ARM code generation communication code generation control code generation Control code (C) ARM code generation MOD DMA DSP OFDM OFDM mod DSP dsp1 dma4 ARM arm dsp ofdm3 DMA dma5 ofdm4 LDPC ldpc Magali code (ASM) DMA OFDM DMA DSP DSP TURBO dma1 ofdm1 dma2 dsp3 dsp5 turbo OFDM DSP DMA DEMOD WIFLEX ofdm2 dsp2 dma3 demod wiflex 27 / 39

43 28 / 39 Benchmarks using LTE OFDM: compilation Src FFT Defram Sink dma1 ofdm1 dma3 Demodulation: communications Src Word 1200 Demap Deinter 900 dma2 dma3 57 Sink dma4 Src Bit Deinter Depunct Turbo Decod 57 dma1 demod turbo

44 29 / 39 Benchmarks using LTE Parametric Demodulation: parameter Src Bit Turbo 4 Deinter Depunct Decod dma Split Split Demap p Demap Word 60 Deinter 300p 300p Word 300p Deinter 8 57 arm Control set p[1] p Sink dma3 dma4 Src p Bit Deinter 300p Depunct Turbo Decod 57 dma1 demod turbo

45 30 / 39 Results: Estimated Development Time Compiler Development Front-End : 4 man-months Back-End : 8 man-months Native PaDaF Application C / ASM (#lines) (hours) C++ (#lines) (hours) OFDM 150 / Demodulation 300 / Param. Demod. 500 / Takeaway Message: Reduces development time

46 Results: Buffer Verification Time Evaluation framework 2.4 GHz Intel Core i5, 8 GB RAM, OS X SPIN Model Checker Application States Transitions Exec. Time (s) OFDM Demodulation Param. Demod Takeaway Message: Reduces development time, improves verification 31 / 39

47 Results: Execution Time Evaluation framework SystemC TLM based on 65 nm CMOS implementation ARM code run on QEMU Virtual Machine Application Native Generated (µs) (µs) OFDM (+13%) Demodulation (+57%) Param. Demod (+33%) Takeaway Message: Reduces development time, improves verification 32 / 39

48 Execution Model Src FFT Defram Sink dma1 ofdm1 dma3 Phase Approach arm dma1 ofdm1 dma3 Time Distributed arm dma1 ofdm1 dma3 Time 33 / 39

49 33 / 39 Execution Model Phase Approach arm dma1 ofdm1 dma3 25 µs 37 µs 16 µs 21 µs Time Distributed arm dma1 ofdm1 dma3 25 µs 74 µs 23 µs 25 µs Time

50 Results: Execution Time Evaluation framework SystemC TLM based on 65 nm CMOS implementation ARM code run on QEMU Virtual Machine Application Native Generated Optimized (µs) (µs) (µs) OFDM (+13%) 149 (+0%) Demodulation (+57%) 180 (+0%) Param. Demod (+33%) 288 (-31%) Takeaway Message: Reduces development time, improves verification, maintains performances 34 / 39

51 35 / 39 Back End Implementation Front End PaDaF (C++) C++ Front End (CLang) LLVM IR Graph Construction Graph + LLVM IR Back End Mapping Scheduling Buffer Verification (SPIN) Code Generation MPSoC Code (ASM) Magali Support Computation Communication Control LTE Experimentation Performance close to native Buffer verification Central controller [ComPAS 14, CASES 14]

52 36 / 39 Outline Context SDR software? Programming Model for SDR Dataflow Model of Computation Input Format Dataflow Refinement and Buffer Verification Mapping and Scheduling Micro-Scheduling Experimentations on Magali Code Generation Experimental Results Conclusion

53 37 / 39 Conclusion A complete research experience between Telecommunication, SoC programming sqand Compilation. Mickael Dardaillon is currently working at National Instruments (Austin) on the compilation Parametric Dataflow in LabView-FPGA (mickael.dardaillon@gmail.com) CEA has stopped the activities on Magali (and is, in general, less involved in telecommunication chips because of ST-microelectronics strategy). There are many open questions: How to program FPGA-based SDR machines? How to handle fast dynamic reconfiguration in heterogenous MP-SoC?

54 38 / 39 Question? Front End PaDaF (C++) C++ Front End (CLang) LLVM IR Back End Mapping Scheduling Buffer Verification (SPIN) Programming Model PaDaF Front End Micro-Scheduling Buffer verification Model checking Graph Construction Graph + LLVM IR Code Generation MPSoC Code (ASM) Experimentations Magali Back End LTE experiments

55 Perspectives On dataflow programming Compiler Runtime Front End PaDaF (C++) C++ Front End (CLang) Back End Mapping Scheduling LLVM IR Buffer Verification (SPIN) Graph Construction Code Generation Graph + LLVM IR MPSoC Code (ASM) 39 / 39

56 39 / 39 Perspectives On dataflow programming On heterogeneous MPSoC Future of dedicated platforms Development on such platforms data rate (kbps) G 3G 4G Wi-Fi Bluetooth year

57 Perspectives On dataflow programming On heterogeneous MPSoC On data manipulation 50% of telecom. protocol Complexity abstraction... Control Data User 1 User 2 User 3 39 / 39

58 39 / 39 Perspectives On dataflow programming On heterogeneous MPSoC On data manipulation