Chapter 3 working with combinational logic

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1 hapter 3 working with combinational logic ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz

2 Working with combinational logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs multi-level logic, converting between Ns and ORs Time behavior Hardware description languages We are going to cover these topics in this chapter The first important topic here is formalizing the process of boolean minimization. In the last chapter, we illustrated how logic functions (or its expressions) can be simplified by boolean cubes or K-maps. Here we will look at a systematic or algorithmic approach. Then we will cover how logic design is realized by logic gates such as NN and NOR. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 2

3 esign example: two-bit comparator N N2 LT EQ GT block diagram and truth table < = > LT EQ GT we'll need a 4-variable Karnaugh map for each of the 3 output functions efore going into the formal minimization process, let s look at some examples. The first example compares two numbers, each of which is two bits long, N is and N2 is. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 3

4 esign example: two-bit comparator (cont d) K-map for LT K-map for EQ K-map for GT LT = EQ = GT = ' ' + ' + ' ' ' ' ' + ' ' + + ' ' ' + ' + ' = ( xnor ) ( xnor ) LT and GT are similar (flip / and /) EQ = ( + ) + (+ ) =(+ )(+ ) ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 4

5 esign example: two-bit comparator (cont d) two alternative implementations of EQ with and without XOR EQ EQ XNOR is implemented with at least 3 simple gates Note that an XNOR gate is complicated and requires at least 3 simpler gates ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 5

6 esign example: 2x2-bit multiplier 2 2 block diagram and truth table P P2 P4 P8 2 2 P8 P4 P2 P 4-variable K-map for each of the 4 output functions This is a 2bit by 2bit multiplier that generates 4 bit output (whose MS is P8 and LS is P). Note that 2 and 2 are higher order bits. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 6

7 esign example: 2x2-bit multiplier (cont d) 2 2 K-map for P8 P8 = 22 K-map for P4 P4 = 22' + 2' K-map for P2 K-map for P P = 2 2 P2 = 2'2 + 2' + 22' + 2' 2 ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 7

8 esign example: increment by I I2 I4 I8 block diagram and truth table This example shows how we can utilize don t care terms O O2 O4 O8 I8 I4 I2 I O8 O4 O2 O X X X X X X X X X X X X X X X X X X X X X X X X 4-variable K-map for each of the 4 output functions ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 8

9 esign example: increment by (cont d) I8 X O8 O4 I8 X I2 X X X X X I4 I8 X I O2 O8 = I4 I2 I + I8 I' O4 = I4 I2' + I4 I' + I4 I2 I O2 = I8 I2 I + I2 I' O = I' I2 O X X X X X I4 I8 X I I2 I4 X X X X X I X In O8, we will interpret a term as if it helps to minimize the number of literals for the elements of the ON-set. The other terms will be treated as. To minimize the number of literals, we have to find out the maximum size subcube. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 9 I2 I4 X X X X I

10 efinition of terms for two-level simplification Implicant single element of ON-set or -set or any group of these elements that can be combined to form a subcube (or an adjacent group) Prime implicant implicant that can't be combined with another to form a larger subcube Essential prime implicant prime implicant is essential if it alone covers an element of ON-set will participate in LL possible covers of the ON-set -set used to form prime implicants but not to make implicant essential Objective: grow implicant into prime implicants (to minimize literals per term) cover the ON-set with as few prime implicants as possible (to minimize number of product terms) So far we have examined a few examples of logic design simplification From now on, we will try to perform simplification in a systematic or algorithmic way. To do so, we first have to define some terminologies. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz

11 Examples to illustrate terms X 6 prime implicants: '', ',, '',, ' essential minimum cover: + ' + '' 5 prime implicants: essential, ',, ', '' minimum cover: 4 essential implicants ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz First of all, we have to find out all the possible prime implicants. Then we first transform the essential prime implicants to boolean expressions. Then we will try to find the minimum set of prime implicants to cover the entire on-set, called minimum cover.

12 lgorithm for two-level simplification lgorithm: minimum sum-of-products expression from a Karnaugh map Step : choose an element of the ON-set Step 2: find "maximal" groupings of s and Xs adjacent to that element consider top/bottom row, left/right column, and corner adjacencies this forms prime implicants (number of elements always a power of 2) Repeat Steps and 2 to find all prime implicants Step 3: revisit the s in the K-map if covered by single prime implicant, it is essential, and participates in final cover s covered by essential prime implicant do not need to be revisited Step 4: if there remain s not covered by essential prime implicants select the smallest number of prime implicants that cover the remaining s This is the formalized algorithm of the two-level simplification algorithm. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 2

13 lgorithm for two-level simplification (example) X X X X X X X 2 primes around ''' X X 2 primes around ' X X X X X X X X X 3 primes around ''' 2 essential primes minimum cover (3 primes) First pick any and check the prime implicants (PIs) that include the. The PIs should be considered for all the s. Then we first choose essential PIs and then find out the minimum cover, the minimum number of PIs that cover the remaining s ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 3

14 ctivity List all prime implicants for the following K-map: X X X X X X Which are essential prime implicants? What is the minimum cover? Let s start with prime implicants. mong PIs, check which are essential. Finally, we should find out the minimum cover, which is the minimum number of PIs that cover all the elements of the ON-set (including essential PIs) ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 4

15 Implementations of two-level logic Sum-of-products N gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) N gates to form product In this section, we will focus on how to implement logic networks with NN or NOR gates. gain there are two kinds of canonical forms: S-O-P and P-O-S. small circle is an inverter. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 5

16 Two-level logic using NN gates Replace minterm N gates with NN gates Place compensating inversion at inputs of OR gate s I mentioned in chapter, MOS transistors (TRs) are widely used and NN and NOR gates are easily implemented by MOS TRs. So we want to change N and OR gates into NN gates only (or NOR gates only) The simplest way is to insert double inverters between N and OR gates. Then what happens is that N becomes NN just by placing bubbles. How about the OR gate? ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 6

17 Two-level logic using NN gates (cont d) OR gate with inverted inputs is a NN gate de Morgan s: + = ( ) Two-level NN-NN network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed Recall de Morgan s Law. When inverters are passing through a gate, the gate should be changed from OR to N and vice versa. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 7

18 Two-level logic using NOR gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of N gate In the case of P-O-S forms, the same technique is used; however, this time, the NOR gate is the target of conversion. gain, we insert two bubbles between OR and N gates and push those bubbles in the opposite directions. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 8

19 Two-level logic using NOR gates (cont d) N gate with inverted inputs is a NOR gate de Morgan s: = ( + ) Two-level NOR-NOR network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed Using de Morgan s theorem again, the N gate with inverted inputs is transformed into the NOR gate as shown in the above. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 9

20 Two-level logic using NN and NOR gates NN-NN and NOR-NOR networks de Morgan s law: ( + ) = ( ) = + written differently: + = ( ) ( ) = ( + ) In other words OR is the same as NN with complemented inputs N is the same as NOR with complemented inputs NN is the same as OR with complemented inputs NOR is the same as N with complemented inputs This slide summarizes what I explained about conversion from N-OR combination to either NN or NOR gates. ll the conversions are just variations of de morgan s theorem. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 2

21 onversion between forms onvert from networks of Ns and ORs to networks of NNs and NORs introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" conservation of inversions do not alter logic function Example: N/OR to NN/NN Z NN NN NN gain, inverters inserted between gates are called bubbles. In order to make no changes in the logic function, the bubbles are always paired. Z ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 2

22 onversion between forms (cont d) Example: verify equivalence of two forms Z NN NN NN Z Z = [ ( ) ( ) ] = [ ( + ) ( + ) ] = [ ( + ) + ( + ) ] = ( ) + ( ) Let s verify the conversion rule by boolean expressions and boolean theorems ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 22

23 onversion between forms (cont d) Example: map N/OR network to NOR/NOR network Z NOR NOR Z \ \ \ \ NOR NOR NOR Z conserve "bubbles" Step Step 2 When an input variable, say, is complemented, it is denoted by \ conserve "bubbles" When a S-o-P canonical form is converted to NOR networks, we have to insert two bubbles at the input stage. nd the same thing happens at the output stage. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 23

24 onversion between forms (cont d) Example: verify equivalence of two forms Z \ \ NOR NOR Z \ \ NOR Z = { [ ( + ) + ( + ) ] } = { ( + ) ( + ) } = ( + ) + ( + ) = ( ) + ( ) This is the boolean logic proof of the conversion in the previous slide. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 24

25 Multi-level logic x = F + E F + F + E F + F + E F + G reduced sum-of-products form already simplified 6 x 3-input N gates + x 7-input OR gate (that may not even exist!) 25 wires (9 literals plus 6 internal wires) x = ( + + ) ( + E) F + G factored form not written as two-level S-o-P x 3-input OR gate, 2 x 2-input OR gates, x 3-input N gate wires (7 literals plus 3 internal wires) E F G If there are common parts in a canonical form, it may be better to use multi-level logic to reduce the number of literals and gates at the cost of delay. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 25 X

26 onversion of multi-level logic to NN gates F = ( + ) + original N-OR network \ Level Level 2 Level 3 Level 4 F introduction and conservation of bubbles \ F redrawn in terms of conventional NN gates \ \ F Normally when we add two bubbles in a wire, two levels are converted to NN gates. Here we add two bubbles between N and OR gates. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 26

27 onversion of multi-level logic to NORs F = ( + ) + introduction and conservation of bubbles original N-OR network \ \ Level Level 2 Level 3 Level 4 F F redrawn in terms of conventional NOR gates \ \ \. F \ Here we add bubbles in different position to use NOR gates. Note that the final inverter is implemented by NOR! ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 27

28 onversion between forms Example X F X F original circuit add double bubbles to invert all inputs of OR gate \ X F \ X \ X F add double bubbles to invert output of N gate insert inverters to eliminate double bubbles on a wire This slide illustrates how we can convert a combination of N and OR gates into NN and NOT gates. s mentioned before, NOT gates can be replaced by NN gates by splitting the input. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 28

29 N-OR-Invert (OI) gates OI function: three stages of logic N, OR, Invert multiple gates "packaged" as a single circuit block logical concept possible implementation Z Z N OR Invert NN NN Invert 2x2 OI gate symbol & & + 3x2 OI gate symbol & & + Here is a special case of N-OR-Inverter gates, which is a popular combination in a logic package. The reason it becomes a popular combination is that it can be implemented compactly with MOS TRs. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 29

30 OI example Why OI is more compact than NN or NOR? out = [ab+c] : invert symbol circuit or and ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 3

31 onversion to OI forms General procedure to place in OI form compute the complement of the function in sum-of-products form by grouping the s in the Karnaugh map Example: XOR implementation xor = + OI form: F = ( + ) Let s take an example to use OI to implement a logic function. Suppose we have to implement a XOR function. F = +. first of all, we consider F (note that there is an inverter at the end). F = +. So we implement F in the SOP form. & & + F ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 3

32 Summary for multi-level logic dvantages circuits may be smaller gates have smaller fan-in circuits may be faster isadvantages more difficult to design tools for optimization are not as good as for two-level analysis is more complex Multi-level logic design can reduce the number of gates or at least the number of fan-ins of gates. However, optimization is more complex. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 32

33 Time behavior of combinational networks Waveforms visualization of values carried on signal wires over time useful in explaining sequences of events (changes in value) Simulation tools are used to create these waveforms input to the simulator includes gates and their connections input stimulus, that is, input signal waveforms Some terms gate delay time for change at input to cause change at output min delay typical/nominal delay max delay careful designers design for the worst case rise time time for output to transition from low to high voltage fall time time for output to transition from high to low voltage pulse width time that an output stays high or stays low between changes The next topic of this chapter is the behavior of combinational logic as time goes by. The waveform of a system can be simulated by a tool considering gates and their connections. The output of the system is triggered by the input stimulus. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 33

34 Momentary changes in outputs an be useful pulse shaping circuits an be a problem incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit = delays matter F remains high for three gate delays after changes from low to high F is not always pulse 3 gate-delays wide Let s see how a waveform changes over time in this case. Here, each gate incurs time unit delay. This time-varying behavior is utilized to make a periodic pulse. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 34

35 Oscillatory behavior nother pulse shaping circuit resistor + close switch open switch initially undefined open switch ssume that each gate delay is time units. Here, the output of NN is feedback to its input with a couple of inverters. Let s look at the waveform of. what does it look like? ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 35

36 Hardware description languages (HLs) escribe hardware at varying levels of abstraction Structural description textual replacement for schematic hierarchical composition of modules from primitives ehavioral/functional description describe what module does, not how synthesis generates circuit for module Simulation semantics This is the last topic of chapter 3. So far, we rely on boolean expressions and schematic drawings to describe logic functions. However, as a logic function gets complicated, it will become extremely hard to write and understand the logic system. Hierarchy can help to mitigate this problem; but it is not enough. HLs are proposed to deal with this problem. Using HLs, we can describe any complicated logic system. Moreover, the languages can be executed, they run like s/w. program emulates the behavior of the designed system as faithfully as possible. It radically reduces the time to design a system ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 36

37 HLs bel (circa 983) - developed by ata-i/o targeted to programmable logic devices not good for much more than state machines ISP (circa 977) - research project at MU simulation, but no synthesis Verilog (circa 985) - developed by Gateway (absorbed by adence) similar to Pascal and delay is only interaction with simulator fairly efficient and easy to write IEEE standard VHL (circa 987) - o sponsored standard similar to da (emphasis on re-use and maintainability) simulation semantics visible very general but verbose IEEE standard Verilog and VHL are the most popular HLs. This course does not aim to cover HLs in-depth. V: very high speed I ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 37

38 Verilog Supports structural and behavioral descriptions Structural explicit structure of the circuit e.g., each logic gate instantiated and connected to others ehavioral program describes input/output behavior of circuit many structural implementations could have same behavior e.g., different implementation of one oolean function We ll mostly be using behavioral Verilog rely on schematic when we want structural descriptions We will just have a quick look at Verilog. There are two approaches in describing the system (or its modules). structural description specifies the system textually in terms of logic gates behavioral description can handle more dynamic properties of the system, which is the focus in the textbook. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 38

39 Structural model module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t, t2; a and inverter inv (abar, a); inverter inv (bbar, b); and_gate and (t, a, bbar); and_gate and2 (t2, b, abar); or_gate or (out, t, t2); b inv inv bbar t abar t2 and2 or out endmodule Here is one example of a structural model description. Wire is used to declare internal variables, which correspond to internal wires. Three types of gates are already included in the Verilog language, just like a library function. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 39

40 Simple behavioral model ontinuous assignment module xor_gate (out, a, b); input a, b; output out; reg out; assign #6 out = a ^ b; simulation register - keeps track of value of signal endmodule delay from input change to output change Here is one example of a behavioral model description. reg is used to declare out, which should be kept track of by a register whenever there is a change. ssign means that out should be evaluated again whenever there is a change in a or b. ^ is x-or in Verilog. #6 means it takes 6 time units while the input change is propagated to the output value ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 4

41 Simple behavioral model always block module xor_gate (out, a, b); input a, b; output out; reg out; or b) begin #6 out = a ^ b; end endmodule specifies when block is executed ie. triggered by which signals The always block is another expression which is equivalent to the assign sentence in the previous sign indicates that this block should be evaluated whenever there is a change in a or b. The list is called the sensitivity list. Is there anything missing? ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 4

42 riving a simulation through a testbench module testbench (x, y); output x, y; reg [:] cnt; initial begin cnt = ; repeat (4) begin # cnt = cnt + ; $display ("@ time=%d, x=%b, y=%b, cnt=%b", $time, x, y, cnt); end # $finish; end 2-bit vector initial block executed only once at start of simulation print to a console assign x = cnt[]; assign y = cnt[]; endmodule directive to stop simulation testbench is the module that drives the designed system by triggering input stimuli. The repeat block will be iterated 4 times. This means x, y are the input variables of the system. The role of the initial block is to schedule the change of input variables. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 42

43 omplete simulation Instantiate stimulus component and device to test in a schematic p.44 test-bench x y a b z If we combine the testbench module with the X-or module, the Verilog progrma will do the function as shown here. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 43

44 HLs vs. programming languages (PLs) Program structure instantiation of multiple components of the same type specify interconnections between modules via schematic hierarchy of modules ssignment continuous assignment (logic always computes) propagation delay (computation takes time) timing of signals is important (when does computation have its effect) ata structures size explicitly spelled out - no dynamic structures no pointers Parallelism hardware is naturally parallel (must support multiple threads) assignments can occur in parallel (not just sequentially) Even though a hierarchical structure is common on HLs and PLs, there are some fundamental differences between HLs and PLs. For example, continuous assignment and propagation delay are not typically supported in PLs. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 44

45 HLs and combinational logic Modules - specification of inputs, outputs, bidirectional, and internal signals ontinuous assignment - a gate s output is a function of its inputs at all times (doesn t need to wait to be "called") Propagation delay- concept of time and delay in input affecting gate output omposition - connecting modules together with wires Hierarchy - modules encapsulate functional blocks HLs can describe every aspect of combinational logic systems. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 45

46 Working with combinational logic summary esign problems filling in truth tables incompletely specified functions simplifying two-level logic Realizing two-level logic NN and NOR networks networks of oolean functions and their time behavior Time behavior Hardware description languages Later combinational logic technologies more design case studies In this chapter, we talked about the formal process of logic simplification, based on the K-map technique. ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 46

47 Oct. 3 and Oct. 5: national holidays, no class ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz 47

Simplification of two-level combinational logic

Simplification of two-level combinational logic ombinational logic optimization! lternate representations of oolean functions " cubes " karnaugh maps! Simplification " two-level simplification " exploiting don t cares " algorithm for simplification