CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN

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Eugene Floyd
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1 HPTER II- HPTER II HPTER II ND R.M. Dansereau; v..

2 HPTER II-2 SI IDEL SWITH Simplest structure in a computing system is a switch IDEL SWITH INPUT OUTPUT Path exists between INPUT and OUTPUT if Switch is LOSED or Path does not exist between INPUT and OUTPUT if SWITH is OPEN or R.M. Dansereau; v..

3 HPTER II-3 SWITHES IN SERIES -SI SWITH SWITHES IN SERIES INPUT Truth Table S S2 PTH? S NO NO NO YES S2 ND configuration OUTPUT R.M. Dansereau; v..

4 HPTER II-4 SWITHES IN PRLLEL -SI SWITH -SWITHES IN SERIES SWITHES IN PRLLEL INPUT S S2 S Truth Table S2 PTH? NO YES YES YES OUTPUT OR configuration R.M. Dansereau; v..

5 HPTER II-5 INPUT SELETOR -SI SWITH -SWITHES IN SERIES -SWITHES IN PRLLEL INPUT Truth Table S S S2 OUTPUT S2 OUTPUT NE INPUT 2 INPUT UNKNOWN INPUT 2 rowbarred level where logic level is indeterminate. Likely avoid this case. R.M. Dansereau; v..

6 HPTER II-6 MOS MOS SWITHES -SWITHES IN SERIES -SWITHES IN PRLLEL -INPUT SELETOR The idea is to use the series and parallel switch configurations to route signals in a desired fashion. Unfortunately, it is difficult to implement an ideal switch as given. omplementary Metal Oxide Semiconductor (MOS) devices give us some interesting components. IDEL SWITH INPUT nmos transistor DRIN pmos transistor SOURE SWITH GTE GTE OUTPUT SOURE DRIN R.M. Dansereau; v..

7 HPTER II-7 MOS TRNSFER HRTERISTIS MOS -MOS SWITHES nmos S SWITH nmos when LOSED S OPEN LOSED Transmits logic level well Transmits logic level poorly pmos S S SWITH LOSED OPEN pmos when LOSED Transmits logic level well Transmits logic level poorly R.M. Dansereau; v..

8 HPTER II-8 MOS TRNSMISSI GTE () MOS -MOS SWITHES -TRNSFER HR. S IDEL SWITH INPUT OUTPUT S MOS TRNSMISSI GTE (SWITH) INPUT OUTPUT S S nmos pmos OUTPUT S INPUT INPUT S OUTPUT R.M. Dansereau; v..

9 HPTER II-9 MOS TRNSMISSI GTE (2) MOS -MOS SWITHES -TRNSFER HR. -TRNSMISSI GTE SPLIT OF URRENT ROSS TRNSMISSI GTE FOR LOGI- ND LOGI- INPUT LOGI- T INPUT S = LOGI- T INPUT S = S = S = R.M. Dansereau; v..

10 HPTER II- HIGH IMPEDNE () MOS -MOS SWITHES -TRNSFER HR. -TRNSMISSI GTE With switches, we can consider three states for an output: Logic- Logic- High Impedance Path exists for Logic- and Logic- when the switch is LOSED. S / OUTPUT = / High impedance is a state where the switch is OPEN. S / OUTPUT = R.M. Dansereau; v..

11 HPTER II- HIGH IMPEDNE (2) MOS -HIGH IMPEDNE nother way of thinking of switches is as follows Path exists for Logic- and Logic- when the switch is LOSED, meaning that the impedance/resistance is small enough to allow amply flow of current. = LOSED «KΩ SOURE DRIN SOURE DRIN High impedance is a state where the switch is OPEN, meaning that the impedance/resistance is very large allowing nearly no current flow. = OPEN» MΩ SOURE DRIN SOURE DRIN R.M. Dansereau; v..

12 HPTER II-2 INVERTER (NOT) MOS -HIGH IMPEDNE = PULL-DOWN PULL-UP This network inverts the binary input value. N R.M. Dansereau; v..

13 HPTER II-3 NND NETWORK MOS -HIGH IMPEDNE -INVERTER = PULL-DOWN PULL-UP R.M. Dansereau; v..

14 HPTER II-4 NOR NETWORK -HIGH IMPEDNE -INVERTER -NND NETWORK = + PULL-DOWN PULL-UP R.M. Dansereau; v..

15 HPTER II-5 ND NETWORK -INVERTER -NND NETWORK -NOR NETWORK NND INVERTER = R.M. Dansereau; v..

16 HPTER II-6 OR NETWORK -NND NETWORK -NOR NETWORK -ND NETWORK NOR INVERTER = + R.M. Dansereau; v..

17 HPTER II-7 XOR NETWORK -NOR NETWORK -ND NETWORK -OR NETWORK = + R.M. Dansereau; v..

18 omplementary ircuits _ -- _ -- oolean Equality + = (+ )( +) ecause = =

19 HPTER II-8 XNOR NETWORK -ND NETWORK -OR NETWORK -XOR NETWORK = + an this be implemented without the extra inverter at the output? nswer: Yes! R.M. Dansereau; v..

20 R.M. Dansereau; v.. HPTER II-9 PULL-UP/PULL-DOWN -OR NETWORK -XOR NETWORK -XNOR NETWORK D + = D D D PULL-UP PULL-DOWN

21 HPTER II-2 FUNTI IMPLEMENTTI -XOR NETWORK -XNOR NETWORK -PULL-UP/PULL-DOWN Most oolean functions can be easily implemented using switches. The basic rules are as follows Pull-up section of switch network Use complements for all literals in expression Use only pmos devices Form series network for an ND operation Form parallel network for an OR operation Pull-down section of switch network Use complements for all literals in expression Use only nmos devices Form parallel network for an ND operation Form series network for an OR operation R.M. Dansereau; v..

22 HPTER II-2 EXMPLE PULL-UP -XNOR NETWORK -PULL-UP/PULL-DOWN -FUN. IMPLEMENTTI To implement the oolean function given below, the following pull-up network could be designed. F = E( D + ( + ) ) D E F R.M. Dansereau; v..

23 HPTER II-22 EXMPLE PULL-DOWN -PULL-UP/PULL-DOWN -FUN. IMPLEMENTTI -EXMPLE PULL-UP To complete the switch design, the pull-down section for the oolean function must also be designed. F = E( D + ( + ) ) F E D Notice how ND and OR become OR and ND circuits, respectively. R.M. Dansereau; v..

24 HPTER II-23 OMPLETED EXMPLE -FUN. IMPLEMENTTI -EXMPLE PULL-UP -EXMPLE PULL-DOWN Putting the pull-up and pull-down pieces together gives the following MOS switch implementation of the oolean function. PULL-UP D PULL-DOWN E E F = E( D + ( + ) ) D R.M. Dansereau; v..

There are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly.

There are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly. ll the Gates There are only 6 possible 2-input gates Let s examine all of them. Some we already know, others are just silly. Do we really need all of these gates? How many of these gates can be implemented