Generation of RTL-code and test facilities for on-chip TDM-network
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1 Generation of RTL-code and test facilities for on-chip TDM-network CNoCCing on Heaven's Door? Geir Åge Noven ESTEC Round-Table on SoC September 2009
2 Background Master thesis conducted by Steffen Forså Oslo, spring 2006 Moore's law still applies Transistor size is shrinking faster than interconnect area Routing consumes relatively more area than gates Can we avoid the «Scyscraper limitation»? Can we throw out a relatively large number of wires for the cost of only a few gates?
3 Routing congestion, signal integrity Studies show that «long wires» on chips toggles at 10% of the clock rate of the chip, on average Can we, by combining some of the «long wires» reduce the effort needed by the routing algorithms? Long, adjacent wires create crosstalk problems, and suffer from capacitive delays. This problem is moved into a «communication» and, thus isolated, is better solved there. (divide & conq) Routing congestion is a major concern in the design of large ASICs A separate communication network will make overall planning of the layout easier
4 Examples of NoC Communication as a separate on large chips DAC 2001: Communication is the next «level of abstraction» Several architectures and protocols have been suggested Packet-/lineswitch, regular og irregular Network on Chip is a well-established area of research in the academic community Commercial solutions available since 2000 Communication Behavioural RTL Gate Transistor This thesis describes a TDM-switched network Route packets Make a ring (Sonics inc.) Most echonomical network
5 What is a NoC? An on-chip network is a porting of a LAN to the chip level (CAN?) The s communicates via Protocol HW infrastructure, topology The General NoC Handles These has to be designed under the new prerequisites the chip poses compared to a traditional LAN Complexity Resources Designspeed, re-usability, testability, routability Advantages of TDM: Disadvantages of TDM Predictable delays Static Connections (predetermined) Simple hardware Not optimal for connections with bandwidth variation in time (But: A TDM network can solve some physical problems and function as a customizable Network layer for packet switching.)
6 Custom Network on Chip Creator Comunication Constraints CNoCC RTL for switches and network Behavioural synthesis
7 CNoCC in the tool flow spec Partitioning into s Communication assessment spec CTG Communication Trace Graph Module design RTL seeds GraphPart network fs, N CNoCC network RTL constraints not met Logic synthesis Place and Route chip
8 CTG Communication Trace Graph CTG is the input to CnoCC List of Modules List of commnication channels with Bandwith and Latency requirements Some kind of Graph Partitioning Algorithm must be adapted og and run (not within the scope of the thesis) This type of algorithm is also used by «Floorplanning» tools The GPA is also required to suggest positions of TDM switching nodes If the TDM network is viewed as a Network Layer, the Packet switches are to be considered as Modules at this stage, belonging to the Transport Layer. GPA CTG Floorplan w/switches
9 CNoCC in the tool flow spec Partitioning into s Communication assessment spec CTG Communication Trace Graph seeds Module design RTL GraphPart network fs, N CNoCC network RTL constraints not met Logic synthesis Place and Route chip
10 Operation of CNoCC 1 Assume that the s has an adapted interface towards the network A Assume that the s produce/consume a constant-bitrate stream of data, where the frequency is derived from the clock frequency of the network (fs) N o C B C ZZZ Choose a number N as the repitition rate of the sequensing (N clock cycles of fs) This gives (rounded to integers) the bus width and packing scheme produced/consumed by the s GenF2 GenF1 s0 s1 s2 s3 RecF1 RecF2 t=1/fs N = GenF1 1 3 GenF2 s s0
11 Operation of CNoCC 2 1 ) B u ild s h a p e s b e tw e e n s w itc h e s 2) Sequence the bits within the shape 3) Map the inputshape to the outputshape with least possible delay W i r e s Timeslots
12 Planning of the network 6*fs GenF * fs * N s1 7*fs GenF * fs * N s * fs * N = 16 * fs *fs GenF3 0 1 fs * N s s RecF1 RecF RecF2
13 Architecture of the switch Zero or more times N or less inputs Always register outputs One stage per input wire static interconnect network One stage per output wire
14 Test generators/receivers GenFn RecFn Using a perl script, fairly large test networks was built (1000's of generators/consumers with different random bandwidths) They were automatically tested by Pseudorandom generators/analysers in a VHDL testbench (also automatically generated) N o C A B C The networks were synthisized to get the component resource usage ZZZ
15 Empirical tests of the system Many test cases with different variations of parameters were tested The results show the expected trends, but the Packing algorithm and the HW architecture has to be tuned to achieve better results The consumption of HW resources is too high Latency, HW resources Latency, HW resources Wires Low average B/W Wires n n High average B/W
16 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion
17 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger
18 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers)
19 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers) Global routing is transferred to an «echonomical network» (i.e. using only the neccesary amount of routing) with deterministic behaviour and using top metal layers.
20 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers) Global routing is transferred to an «echonomical network» (i.e. using only the neccesary amount of routing) with deterministic behaviour and using top metal layers. The global network (e.g. using static TDM switching) may be customized to have channels used by
21 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers) Global routing is transferred to an «echonomical network» (i.e. using only the neccesary amount of routing) with deterministic behaviour and using top metal layers. The global network (e.g. using static TDM switching) may be customized to have channels used by Low bandwith control/data signals with controlled latency CTG
22 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers) Global routing is transferred to an «echonomical network» (i.e. using only the neccesary amount of routing) with deterministic behaviour and using top metal layers. The global network (e.g. using static TDM switching) may be customized to have channels used by Low bandwith control/data signals with controlled latency CTG A packet-switched system for random-access communication between s. Some of the Modules in the CTG becomes the Routers. R R R
23 Can this be used in a NoC? The area of ASICs and FPGAs are becoming increasingly dominated by routing resources, causing routing congestion «The skyscraper problem» may stop devices from becoming increasingly larger Traditional routing can be used for local connections (using lower metal layers) Global routing is transferred to an «echonomical network» (i.e. using only the neccesary amount of routing) with deterministic behaviour and using top metal layers. S OL V E D? A The global network (e.g. using static TDM switching) may be customized to have channels used by Low bandwith control/data signals with controlled latency A packet-switched system for random-access communication between s. Some of the Modules in the CTG becomes the Routers. Based on the CTG (Communication Trace Graph), specifying all s and their interconnection needs, this global network may be synthesized by a system as shown with CNoCC CTG R R R N o C GPA +cnocc B C ZZZ
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