CMP 305: VLSI Very Large Scale Integration Design

Transcription

1 CMP 305: VLSI Very Large Scale Integration Design Amr Wassal Computer Engineering Cairo University Spring 2013 Adapted from 1.Digital Integrated Circuits, Second Edition, 2003, J. Rabaey, A. Chandrakasan, B. Nikolic 2.Mary Jane Irwin, Vijay Narayanan s slides 3.Synopsys University Courseware, Copyright 2010 Synopsys, Inc. Developed By:Vazgen Melikyan Credits & Acknowledgments Slides are adapted from: 1.Digital Integrated Circuits, Second Edition, 2003, J. Rabaey, A. Chandrakasan, B. Nikolic 2.Mary Jane Irwin, Vijay Narayanan s slides 3.Synopsys University Courseware, Copyright 2010 Synopsys, Inc. Developed By:Vazgen Melikyan Course is partially sponsored by: VLSI Design, Spring 2013 Amr Wassal 2

2 Intended Learning Outcomes 1. Develop an understanding of the VLSI-related industries and their dynamics and economics. 2. Learn about the different technologies for digital design. 3. Acquire the design skills and learn the flow for digital VLSI design. 4. Understand the design metrics and the interplay among design trade-offs, and technology issues. 5. Get introduced to the concept of IP reuse and using it as a means to close the productivity gap. VLSI Design, Spring 2013 Amr Wassal 3 Suggested References No Specific Textbook References 1. Modern VLSI Design: IP-Based Design, Wayne Wolf, Prentice Hall, 4 th Edition, Digital Integrated Circuits, J. Rabaey, A. Chandrakasan and B. Nikolic, Prentice Hall, 3 rd Edition, Application-Specific Integrated Circuits, M. Smith, Addison-Wesley Professional, VLSI Design, Spring 2013 Amr Wassal 4

3 Course Requirements & Grading Subject to change: Tutorials: 5 % - individual effort Midterm: 10 % - individual effort Final: 60 % - individual effort Project: 20 % - group effort Lab: 5 % - individual effort Office hours: by appointment a_wassal at yahoo.com subject must start with [CMP305] TAs: Engs. Omar El-Seddeek and others VLSI Design, Spring 2013 Amr Wassal 5 Course Outline Semiconductor Industry and Technology Overview MOS Transistor, IC Design Flows Logic Families, Standard Cells Timing in Digital Systems Front-end Design Flow Back-end Design Flow Design-for-Testability (DFT) Packaging, Interconnection and Signal Integrity Low-Power Design VLSI Design, Spring 2013 Amr Wassal 6

4 Industry & Technology Overview Introduction to the semiconductor industry Functional Structure of a Fabless Company Manufacturing Process Design Rules VLSI Design, Spring 2013 Amr Wassal 7 Industry & Technology Overview Introduction to the semiconductor industry Functional Structure of a Fabless Company Manufacturing Process Design Rules VLSI Design, Spring 2013 Amr Wassal 8

5 Semiconductors TAM World GDP US$62T Applications: Goods embedding electronics and ICT services US$10 s Trillions Per annum size of Semiconductor market is US$300B in 2010 Electronic Goods US$1,000B Electronic Components Drives the whole world economy Semiconductor Components US$300B EDA US$4B The locomotive that powered the economy of many tigers VLSI Design, Spring 2013 Amr Wassal 9 Semiconductors Industry Segments: By End-User Market Computing Telecom/Wireless Consumer Automotive Military and Aerospace Medical Industrial/Process Control/Measurement and more Total available market of ~$300 Billions in VLSI Design, Spring 2013 Amr Wassal 10

6 Semiconductors Industry Segments: By Business Model Integrated Device Manufacturer (IDM) Intel, AMD, IBM, LSI Login, Sony, TI, Infineon, Toshiba, Samsung, NEC, Mitsubishi, Philips, Motorola,... etc. Has in-house manufacturing using its own Fabs besides its own design capabilities (vertical integration). Fabless Marvell, Broadcom, Xilinx, PMC-Sierra, nvidia, ATI, Qualcomm, etc. Outsources manufacturing to (usually) a foundry. Focuses on products, IP, patents and licensing. Merchant Foundry TSMC, UMC, SMIC, etc. Finds work from the pool of fabless companies. Requires careful scheduling, pricing and contracting to remain at full utilization. VLSI Design, Spring 2013 Amr Wassal 11 Semiconductors Industry Segments: By Role in the Supply-Chain Design house (IDM, Fabless): Intel, IBM, LSI Login, Sony, TI, Infineon, Toshiba, Samsung, NEC, Mitsubishi, Philips, Motorola,... vs. Marvell, Broadcom, Xilinx, PMC- Sierra, nvidia, ATI, Qualcomm, etc. Manufacturing (IDM, Foundries): Intel, IBM, vs. TSMC, SMIC, Global Foundries, etc. Assembly/Testing: Amkor, Siliconware Precision, Advanced Semi Engineering, etc. EDA Vendor: Synopsys, Cadence, Mentor Graphics, Magma (Synopsys), etc. IP Vendor: ARM, Virage, Artisan, Denali, MIPS, Rambus, Synopsys, Cadence, etc. Design Services: Wipro, TATA Elxsi, HCL Technologies, etc. Fab Equipment Vendor: Applied Material, ASML, KLM-Tencor, Novellus, Hitachi, etc. VLSI Design, Spring 2013 Amr Wassal 12

7 Semiconductors Industry Segments: By Product Discretes Logic DRAM Memory Flash Memory Other Memories Analog Optoelectronics Sensors/MEMS DSP Microcontrollers Microprocessors CPLDs/FPGAs ASICs/ASSPs VLSI Design, Spring 2013 Amr Wassal 13 Tour the Fab Videos 1, 2 & 3 VLSI Design, Spring 2013 Amr Wassal 14

8 Semiconductor Industry - Revisited Which role in the semiconductors industry can be readily adopted in the Egyptian industry? Which business model to use? Why do that? What careers to expect? Is there any risk? Is there any reward? VLSI Design, Spring 2013 Amr Wassal 15 Semiconductor Industry in Egypt Mentor Graphics (EDA Multi-national) SysDSoft (Now Intel Siemens Acquisition) Si-Ware Systems (Fully Egyptian) Newport Media Inc. Si-Vision and MEMS-Vision Swiftronix (Synopsys affiliated) Hittite (US) Varkon Semiconductors SilMinds Mipex Did I miss anyone? VLSI Design, Spring 2013 Amr Wassal 16

9 Other Related Companies PCB Manufacturing and Assembly AOI BURAQ Electronic systems manufacturing Al-Kharafy Bio-Business Valeo Morroco Sizable operation for ST-Microelectronics Kingdom of Saudi Arabia Sizable research activities VLSI Design, Spring 2013 Amr Wassal 17 Industry & Technology Overview Introduction to the semiconductor industry Functional Structure of a Fabless Company Manufacturing Process Design Rules VLSI Design, Spring 2013 Amr Wassal 18

10 Functional Structure of a Fabless Company Pros and cons of not owning the Fab Focus on product development rather than technology development. Limited by available commercial technologies and foundry capacities. Often a matrix organization Rows are business units Columns are pooled functions VLSI Design, Spring 2013 Amr Wassal 19 Functional Structure of a Fabless Company (cont.) Business Units own Design System Digital Mixed Signal/Analog. Verification System Digital Mixed Signal/Analog. Marketing Applications Engr g Functional pools support CAD/EDA tools and IT PCB/Hardware Testing or Validation Layout (Physical Design) Technology / IP Acquisition Assembly/Packaging Product Engineering/ Production VLSI Design, Spring 2013 Amr Wassal 20

11 What about MEMS? Videos 4 & 5 VLSI Design, Spring 2013 Amr Wassal 21 Industry & Technology Overview Introduction to the semiconductor industry Functional Structure of a Fabless Company Manufacturing Process Design Rules VLSI Design, Spring 2013 Amr Wassal 22

12 Technology Trends: Basic Active Electronic Devices Audion (Triode), 1906 Lee De Forest First point contact transistor (germanium), 1947 John Bardeen and Walter Brattain Bell Laboratories VLSI Design, Spring 2013 Amr Wassal 23 Computing Devices Then EDSAC, University of Cambridge, UK, 1949 VLSI Design, Spring 2013 Amr Wassal 24

13 Technology Trends (cont.) First integrated circuit (germanium), 1958 Jack S. Kilby, Texas Instruments Contained five components, three types: transistors resistors and capacitors Intel Pentium II, 1997 Clock: 233MHz Number of transistors: 7.5 M Gate Length: 0.35 VLSI Design, Spring 2013 Amr Wassal 25 Advances in Integration Intel 4004 (1971) 1.5 GHz 42 million transitors Intel Pentium 4 (2000) 108 KHz 2,300 transistors If automobile speed had increased similarly over the same period, we could now drive from Cairo to Shanghai in seconds. VLSI Design, Spring 2013 Amr Wassal 26

14 Moore s Law Cramming More Components onto Integrated Circuits Gordon Moore, Electronics, 1965 Intel Computing Net Corporate Power Worth will double will double every every 18 months 18 months # of transistors on cost-effective integrated circuit doubles every months. VLSI Design, Spring 2013 Amr Wassal 27 Technology Generations (or Nodes) We refer to the smallest feature size or Critical Dimension (CD). 10um 5um 2um 1um 0.8um 0.5um 0.35um 0.25um 0.18um 0.13um 90nm 65nm 45nm 32nm 22nm Possible through the magic of device scaling Desirable due to manufacturing economics (wafer and batch processing) Usually limited by lithography, implies new patterning technology, equipment for each node. $$$$$$ VLSI Design, Spring 2013 Amr Wassal 28

15 Critical Dimension CD = P min / 2 = k1. λ / NA CD is the critical dimension Pmin/2 is the minimum half pitch k1 is a process factor λ is the wavelength of the exposure light NA is the numerical aperture of the projection optics. VLSI Design, Spring 2013 Amr Wassal 29 Basic Structure of Computers: Technology Trends (cont.) VLSI Design, Spring 2013 Amr Wassal 30

16 Advances in Integration Intel Teraflop Chip 2007 An 80-core ManyCore processor. ch.intel.com/artic les/terascale/1449.htm VLSI Design, Spring 2013 Amr Wassal 31 Technology is constantly on the move! Num. of transistors is not limiting factor Currently ~ 1 billion transistors/chip Problems: Too much Power, Heat, Latency Not enough Parallelism 3-dimensional chip technology? Sandwiches of silicon Through-Vias for communication On-chip optical connections? Power savings for large packets The Intel Core i7 microprocessor ( Nehalem ) 4 cores/chip 45 nm, Hafnium hi-k dielectric 731M Transistors Shared L3 Cache - 8MB L2 Cache - 1MB (256K x 4) VLSI Design, Spring 2013 Amr Wassal Nehalem 32

17 Moore s Law over 10 years 2 10/ Design Element Granularity Methodology Architecture X Sub-system Platform Based Design System Level Synthesis Networks on a Chip CGRA X IPs IP Based Design High Level Synthesis. System on a Chip X Arithmetic Register RTL / Logic Synthesis Algorithm on a Chip X Std. Cells Physical Synthesis Controller on a Chip 1970 X Polygons Manual Design SSI / MSI The granularity of reusable objects increases by 100 X every decade -- Moore s EDA Law VLSI Design, Spring 2013 Amr Wassal 33 Review: CMOS Inverter V DD Full rail-to-rail swing high noise margins Low output impedance High input impedance V in C L V out No direct path steady-state between power and ground no static power dissipation Propagation delay a function of load capacitance and on resistance of transistors VLSI Design, Spring 2013 Amr Wassal 34

18 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors. VLSI Design, Spring 2013 Amr Wassal 35 Inverter in CMOS Process VLSI Design, Spring 2013 Amr Wassal 36

19 A Modern CMOS Process gate oxide field oxide Al (Cu) TiSi 2 SiO 2 tungsten n+ p well p-epi p- n well p+ SiO 2 Dual-Well Trench-Isolated CMOS VLSI Design, Spring 2013 Amr Wassal 37 Review: CMOS Buffer V DD V DD M2 M4 V in V out V out2 M1 M3 VLSI Design, Spring 2013 Amr Wassal 38

20 Its Layout View VLSI Design, Spring 2013 Amr Wassal 39