Shaping Solutions in Advanced Semiconductor Assembly and Test. Pranab Sarma, Product Engineering Manager

Transcription

1 Shaping Solutions in Advanced Semiconductor Assembly and Test Pranab Sarma, Product Engineering Manager

2 STATS ChipPAC Overview 2

3 What we do total turnkey solutions Wafer design Outsourced Semiconductor Assembly and Test Services ( OSAT ) Wafer probe & bump Package design & simulation Package assembly z Bonding die on a substrate Wafer fabrication z (Bump) (Sort) Wire bonding to form electrical connection Die singulation/ wafer singulation z Encapsulation of integrated circuits into packages Multiple applications 3 QA and final chip testing

4 Semiconductor growth by market segment (US$B) $150 Computing/Data storage ($140.1) $125 Market Size by 2011 $100 $75 $50 $25 Consumer 24.6% Computing 18.7% Communications 56.7% STATS STATS ChipPAC market mix mix in in Mil/Civil Areo ($4.8) Growth and and scale scale in in 3C s 3C s Consumer ($60.4) Communications ($107.8) Industrial ($33.1) By 2011, total semi market $373.5B Automotive ($27.3) total OSAT market $30.4B $ Storage 7.0 ($13.3) CAGR ( ) % We are well aligned to high growth market segments 4

5 Our positioning and strategy Excellence in backend turnkey SATS solutions (Bump, Sort, Assembly, Final Test) Maintain capital discipline (Strong balance sheet & cash flow) Invest in technology and focus on long term growth products (3D wafer level interconnect, CSMP and etc) Positioning and Strategy Global strategic footprint that best serves our customers (Singapore, China, Korea, Malaysia, Taiwan, US) Technology differentiation in integration (3D, SiP, FC, WLCSP, RF & mixed signal testing) 5

6 Established presence in the world s most strategic semiconductor markets Icheon, Korea: 587,000 ft 2 high-end facility specializes in advanced array packaging such as Flip- Chip, Stacked Die, Chip Scale Packaging and BGA. Second 199,000 ft2 facility expected to be ready in second half Milpitas and San Diego, CA: 34,000 ft 2 and 20,000 ft 2 respectively, pre-production test houses, provide complete semiconductor test services. Offers new product integration support, final test and other high volume preparatory services Sales R&D Manufacturing Shanghai, China: 422,000 ft 2 facility provides wafer sort, packaging and test services. Second 500,000 ft 2 facility expected to be completed in 2Q ,000 ft 2 operation in Song Jiang District will be focused on 200mm gold bumping and wafer sort services for LCD driver ICs. Kuala Lumpur, Malaysia: 488,000 ft 2 facility provides high volume packaging and test services for a full range of Mixed-Signal / RF test and Power Discrete devices Hsin-Chu Hsien, Taiwan: Winstek, subsidiary with 220,000 ft 2 facility, provides wafer probe services and final test. Hsin-Chu Hsien, Taiwan: 7,000 ft 2 facility specializes in 300mm wafer electroplated solder bump Singapore: Corporate Headquarters 594,000 ft 2 facility with state-ofthe-art equipment, class 10K clean room. Provides full turnkey services including wafer probe, packaging, final testing and drop shipment Global scale, unrivalled positioning 6

7 STATS ChipPAC is the leader in 3D packaging Feature rich end products required more silicon in less space 3D packaging takes advantage of the vertical axis to dramatically increase silicon density 3D packaging is enabling the digital revolution in communication and consumer products MEMS MIC Audio PU FLASH FLASH FM Radio Digital Baseband SRAM Power Mgmt Image Sensor Analog Baseband BT Slim profile handset in the market RF TX PA FEM Package-on-Package (PoP) 6 die stack capability 7 Handset layout block diagram Trend towards customized packaging continues as integration of silicon becomes more complex

8 STATS ChipPAC s flip chip, gold bump and wafer sort complementing the turnkey services 300mm solder bumping and gold bump lines co-located with TSMC foundries 12 Solder bump TSMC Fab 7 Hsin-chu 8 Gold bump TSMC Songjiang Broad technology offering Wafer processes (bumping, RDL, IPD, WLCSP) fccsp (single die and stacked dies) fcbga (bare die, lidded, multi-die, SiP) Well engaged with leading customers GPU graphics & ASIC IDM/fabless companies LCD Driver IC fabless companies Leveraging 3D technology for emerging portable and consumer product applications Game consoles, portable PC, LCD HDTV WLCSP fcqfn fclfbga-sd2 fcbga fcbga-mp RDL Solder bump Gold (Au) bump Resistor Capacitor Inductor Integrated passive devices 8

9 Deliver the broadest and most comprehensive test capability Type of Test Mixed signal High-end digital Radio frequency 3D/Memory Position test solution to enable turnkey strategy Yes Yes Yes Yes Leverage expertise and scale SCS & SCM SCK & SCS SCS & SCM SCK & SCC Utilize test R&D as key differentiator for turnkey Yes Yes Yes Yes Breadth of application types Breadth of package types MCU, Mixer, CODEC, Tunner & Switches QFN, QFP, BGA & CSP CPU, GPU, DSP, PHY, MAC, ASIC & ASSP FCBGA, FBGA, FBGA-SD, BGA, CSP & WLCSP Transceiver, Receiver, Transmitter, RF FEM & RFIC QFN, CSMP, SiP & WLCSP Memory Card, NOR & NAND Flash FCBGA, FBGA- SD, PoP, PiP & MCC Lowest cost of test Multi-site setup Multi-site setup Multi-site setup High parallel>320 Alignment with high growth market segment PC, Communication & Consumer 3-D memory testing in traction to support next generation 3-D packages PoP PiPm PiPs 9

10 Technology differentiation in integration IP Alignment to Market Process Patents Published Wafer process, wafer thinning, die attach, molding, packaging technique Laminate Package 3D Stack Package Flip Chip, SIP Packages Others Leadframe Package 3D Leadership 3-D wafer interconnect Energy saving, small form factor Flip chip enabling technologies PoP PiPS Flip-chip LFBGAm USPTO* IP Filing 117 filed 37 issued Smaller footprint, high integration 235 filed 43 issued High performance, high density 2005 *United States Patent and Trademark Office

11 Our leadership in shaping solutions to achieve product customization for our customers Leading enabling technologies Advanced packaging Broad test offering Substrate Solder bump Gold bump VFBGA-T LFBGA-SD LFLGA ROOS CATALYST VERIGY Wire bond Stacked dies IPD TFLGA TBGA LFBGA-SiP LTX FUSION FLEX ADVANTEST Shielding RDL + + QFN/BCC PoP/PiP Seamless integration UFLEX HP93K/PS800 PoP/PiP for BB/MAC + Flash FCBGA for GPU LFBGA for CPU Memory card packaging TBGA for MPU QFN/BCC for TXVR Customized solutions for our customers 11

12 Our market focus High growth markets Wireless 31% CAGR Consumer -22% CAGR PC/Storage 18% CAGR Wireline 14% CAGR Automotive 15% CAGR Note: CAGR period is five years ( ) Source: Gartner DQ Dec 06 12

13 Pb Free Conversion Status 13

14 Pb Free Roadmap 70% of laminate volume is Pb free. - All new products are Pb free. Of the remaining non Pb free products 80% are PBGA. - The BOM is Pb free except the solder ball that is Sn-Pb. -These are legacy products and will be supported based on demand. - New designs will generally move to Pb free. Requirement for being ROHS compliant and customer demand driving the push for higher conversion rate to Pb free. - STATS ChipPAC s product focus is more focused towards high growth markets that is driving the conversion to Pb free and green solutions. - Current business demands encourage investments in infrastructure for Pb free solution and discourages long term investments for supporting leaded solutions. STATS ChipPAC has done extensive studies comparing eutectic and Pb free solution indicating that Pb free solutions are at par or better than eutectic. 14

15 Pb Free Program Better For Business Better For Environment Reliability Overview Qualified major package families internally and at customers. Completed and passed the following tests: - MRT 260C, 260C and specific customer conditions. - PCT (336 Hrs) - TC Condition C (1000 cycles) - HTS (1000 Hrs) - 85C/85% RH without Bias Passed BLR Tests with different Pb-free alloys. Passed Aging (Intermetallic) and Bend Tests. 15

16 Overview: Package Level Reliability Reliability Target 16

17 Board Level Reliability 17

18 Board Level Reliability 18

19 Board Level Reliability 19

20 Board Level Reliability 20

21 Board Level Reliability 21

22 Pb Free Reliability Study Conclusion Lead-free Solder Joint Reliability is Superior. No Difference in the Reliability Among the Various Lead-free Solder Joints Tested So Far. In General, Area Array Packages and Leadframe Packages Exhibit Acceptable Thermal Fatigue Resistance. Based on Internal Study, Customer Feedbacks, and Market Conditions, Conversion to Lead-free Offers Better Advantages Compared to Sn-Pb. 22

23 The Road Ahead STATS ChipPAC is Committed to Continuous Conversion to Lead-free Solutions. - Existing customers will be supported during the life of the legacy products, however new designs will be continuously converted to Lead-free solutions. STATS ChipPAC is Ready for ROHS Implementation. Lead-free Solution is Better for Business and Better for Environment. 23

24 Thank You 24