Fine Line Panel Level Fan-Out

Transcription

1 Fine Line Panel Level Fan-Out David Fang CTO, Vice President of Powertech Technology Inc. P - 1

2 Outline 1. Brief Introduction of PTI 2. Moore s Law Challenges & Solutions Moore s Law Challenges Highly Integration SiP Solutions 3. Fine Line Panel Level Fan Out Technology Wafer Level v.s. Panel Level Panel Level Fan Out Challenges and Solutions Panel Level Fan Out Diversification 4. Summary P - 2

3 PTI Company Overview Founded in 1997 Major Services: Chip Probing, Bumping, WLP, Panel FO, Packaging, Final Test, & Module Assembly Revenue: $1.5B USD (2016) Employees: ~16, plants worldwide Taiwan Headquarters (3D) Hukou (3A) Hukou (2A & 2B) Hukou (3C) HSP (P8 & P11) WenHua (P9) Hsinpu (P1) Greatek P - 3

4 PTI Package Technology In Brief 32D Stacking NAND 50um Pitch CPB FC SiP WLCSP CIS CSP 25um chip Debut in D/3DIC 3DIC Memory Cube 3DIC Memory on Logic 2.5D IC 4D memory logic chip2 chip3 chip1 Chip Bump Interposer TSV Fan Out CHIEFS CLIP PiFO BF 2 O P - 4

5 Outline 1. Brief Introduction of PTI 2. Moore s Law Challenges & Solutions Moore s Law Challenges Highly Integration SiP Solutions 3. Fine Line Panel Level Fan Out Technology Wafer Level v.s. Panel Level Panel Level Fan Out Challenges and Solutions Panel Level Fan Out Diversification 4. Summary P - 5

6 Electronics Industry Evolution Vacuum tube John Ambrose Fleming, 1904 Transistor John Bardeen, Walter Brattain, and William Shockley, 1947 Integrated circuit Jack Kilby, 1958 LSI~VLSI 18,000 vacuum tubes Pennsylvania State U. U. of Manchester IBM s 1950s 1960s 1970s ~ Today s accomplishments were yesterday s impossibilities! P - 6

7 Moore s Law Challenges Source: The Economist P - 7

8 SoC Challenges SoC in FCBGA Chip Split & Re-constitution in SiP P - 8

9 Challenges of Conventional SiP SoC in FCBGA Conventional SiP Challenges for conventional SiP 1. Performance degradation (long interconnection). 2. Power consuming (high transmission resistance). 3. Large form factor (substrate routing constraint). Need solutions to allocate chips as close as possible. P - 9

10 3DIC and 2.5DIC for SiP 3DIC SiP Difficult TSV connection design (different chip size). Heat dissipation & data retention issue. Thicker package than conventional SiP. Take time to coordinate different chip suppliers and TSV designs. High chips cost (same size chips). 2.5DIC SiP Chips Interposer Substrate Additional interposer design and manufacturing. Interposer cost. Extra tests to ensure known good interposer. P - 10

11 Fan Out SiP FC SiP L/S>10/10um FO SiP L/S 2/2~10/10um Wide L/S fan out (> 10/10um) doesn t have better performance than FC SiP because long interconnection. We need fine L/S fan out to place chips closer for better performance, lower power consumption, and higher I/O density. P - 11

12 Highly Integration SiP Solutions Items Solution Flip Chip 3DIC 2.5DIC Fine line Fan Out I/O density (#/mm 2 ) 1x10 2 ~ 6x10 2 1x10 3 ~ 1x10 4 1x10 3 ~ 1x10 4 1x10 2 ~ 1x10 3 L/S (um) 9/12 < 2/2 < 2/2 2/2 Chip partition Bandwidth Total power Thickness M M+ M L Cost $$ $$$ $$$ $$- Fine line Fan Out for highly integration has reasonable cost with good performance. P - 12

13 FO : Advantages & Applications Thin RDL & PI Low Z-height Mobile AP Fine pitch pillar High I/Os Side-by-side Short transmission & High I/O interconnection <5/5um L/S Low insertion loss, Coplanar waveguide Short path Low J PMIC, Power High BW PoP Logic + Memory >3 GHz CPU, GPU P - 13

14 Fan-Out for Heterogeneous Integration SoC AP 14nm BB 14nm AP 14nm BB 28nm AP 14nm BB 28nm PMIC RF IPD SoC on FCCSP High wafer cost Low wafer gross die High NRE (mask) FO (side-by-side) Low wafer cost Low NRE (mask) Flexible to dynamic product mix Quick time-to-market FO SiP Low COO Easy to use / design-in Small form factor P - 14

15 Fan-Out for Homo/Heterogeneous Integration (Chip Partition) FCCSP Fan-Out 7 nm Wafer Yield : ~30% Wafer Yield : ~70% + < N-lane SerDes N-lane SerDes 2N-lane SerDes Chip Combo 1X dollars 1X dollars >2X dollars Chip Combo Performance boosted Value added by FO P - 15

16 Outline 1. Brief Introduction of PTI 2. Moore s Law Challenges & Solutions Moore s Law Challenges Highly Integration SiP Solutions 3. Fine Line Panel Level Fan Out Technology Wafer Level v.s. Panel Level Panel Level Fan Out Challenges and Solutions Panel Level Fan Out Diversification 4. Summary P - 16

17 Wafer Level or Panel Level Suitable Player for Panel Level Fan Out Setup 300mm wafer 3~5X Package quantity ratio (per panel) Package size (mm 2 ) Wafer level Panel level 15 x x x x Package for More than Moore is usually larger than 10x10mm. Panel level provides 3~5X efficiency than wafer level. Industry Expertise Wafer foundry LCD PCB OSAT IC package N N Large panel - Fine line Warpage control 1. OSAT is in a good position to setup panel level Fan Out. 2. Initial investment per module is 30~40% higher than Fan In WLP. P - 17

18 Panel Level Fan Out Challenges 1. No worldwide standards mm wafer has SEMI standards - LCD and IC substrate has different panel size. What standard should panel level follow? 2. Tool and accessory readiness - Lack of whole set of fine pitch panel tools - Process cassette, loader / unloader, transportation 3. Product & Process Difficulty Gen. LCD panel Size (mm) 1 300x x x x x x Panel warpage, chip shift, fine line patterning PCB (IC substrate) panel Type A B C D Size (mm) 400x x x x600 P - 18

19 Tool Readiness for Panel Level Fan Out Process Industry Wafer foundry (WLP, bumping) LCD PCB Picked Coating A B C B Exposure A B C B Tool Development A B C B Deposition A B C PVD: B ECD: A (E ) Back-end A - - Expanded version Cassette FOUP Cassette Tray Accessory Transportation OHT AGV/MGV Trolly New design Load Port Load Lock Open Env. Open Env. Panel Level Fan Out leverages a mixed infrastructure. We referred accessory of different industries to design suitable ones for panel level Fan Out. P - 19

20 Major Panel Level Fan Out Process Flow (Chip First) Chip Preparation Die Embedding Patterning Backend Cu post Chip mount Dielectric litho Marking BSG Molding PVD Ball mount Chip singulation Mold grinding RDL litho Debond RDL ECD Singulation Strip & etch P - 20

21 Panel warpage Warpage Challenge for Panel Level Fan Out Acceptable warpage Before Big warpage Panel After Process steps A B C D E F G H I J K L M Small warpage Conveyor with guide rollers Robot clamps with vacuum chuck 1. Structure, materials, and process optimization helps reducing warpage. 2. Special chuck, conveyor, and cassette designs also help to tolerate panel warpage. P - 21

22 Panel Chip Shift Challenge for Panel Level Fan Out PI open Pad Chip Not aligned PI open to pad mis-alignment Original chip mount location Chip shift after mold cure Aligned Good alignment Chip mount shift intentionally Chip mount accuracy Mold parameters optimization Lithography compensation Add chip shift design tolerance CTE matched design Chip mount offset compensation Chip move to correct position after mold cure Offset chip mount position intentionally to compensate chip shift after mold cure. P - 22

23 Chip Shift Compensation Mask-to-Chip alignment Laser Direct Imaging (LDI) Mask Θ CCD CCD read die shift X Y LDI CCD CCD detect chip shift location AOI feedback chip shift to stepper. Chuck will move to fit chip shift LDI creates patterns aligned with shifted chip locations. P - 23

24 PTI Panel Level Fan Out Solutions eplp (embedded Panel Level Package) eplb (embedded Panel Level BGA) CHIEFS (Chip First) CLIP (Chip Last) PiFO (Chip Middle) BF 2 O (Bump Free) - Cheaper than CLIP - AP, BB, ASIC, Memory - Known Good RDL - Passive available - CPU, GPU, FPGA, Thermal sensitive devices - Pillars connect top and bottom RDLs - Passive available - RF module, Sensor, AP (PoPb), SiP, 3D stacking - PMIC, Audio, RF transceiver CHIEFS :Chips Integration Embedded Fanout Solution CLIP : Chip Last Integration Package PiFO : Pillars In FanOut BF 2 O : Bump Free FanOut RDL L/S : 8/8um qualified, 5/5um developed, 2/2um capability P - 24

25 Homogeneous Integration Fan Out Chip A Chip A 8/8 um M2 M1 3P2M+UBM P - 25

26 Heterogeneous Integration Fan Out Chip A Chip B 5/5 um M2 M3 M1 4P3M+UBM P - 26

27 PiFO (Pillar in FO) controller Underfill EMC Cu Pillar Top RDL 3P2M 55um 33um 100um 200um M1 M3 M2 Bottom RDL 3P3M+UBM Bottom RDL first P - 27

28 Panel Level Fan Out Diversification CHIEFS (Chip First) CLIP (Chip Last) PiFO (Chip Middle) BF 2 O (Bump Free) Homo/Heterogeneous Integration Specific Function FO stack FO in package FO compartment EMI shield FO_PoP w/ stacked chips FO_PoP w/ FI FO SiP embedded SBT FO AoP FO Sensor P - 28

29 Outline 1. Brief Introduction of PTI 2. Moore s Law Challenges & Solutions Moore s Law Challenges Highly Integration SiP Solutions 3. Fine Line Panel Level Fan Out Technology Wafer Level v.s. Panel Level Panel Level Fan Out Challenges and Solutions Panel Level Fan Out Diversification 4. Summary P - 29

30 Summary 1. Panel level Fan-Out has advantages of small form factor, high bandwidth, and good production efficiency for highly integrated packages. 2. PTI setup the first fine line panel level Fan Out in 2H/2016 to extend Moore s Law with homo / heterogeneous integration. 3. We expect fine line Fan-Out would be adopted in a wide range of applications. It is encouraged that more players to join and make it prosperous. P - 30

31 Powertech Technology Inc. No. 10, Datong Rd., Hsinchu Industrial Park, Hukou, Hsinchu, Taiwan. TEL: (886) Powertech Technology (Suzhou) Ltd. No. 33, Xinghai Street, Suzhou Industrial Park, Suzhou, China. TEL: (86) Powertech Technology (Singapore) Pte.Ltd. 12 Ang Mo Kio Street 65 Singapore TEL: (65) Powertech Semiconductor (Xian) Co., Ltd. Part B, Shaanxi Xi'an Export Processing Zone, No. 28, Xinxi Avenue, Xi'an, Shaanxi China. TEL: (86) Greatek Electronics Inc. No. 136, Gung-Yi Rd., Chunan Town, Miaoli, Taiwan. TEL: (886) Tera Probe Inc. KAKiYA Bldg., Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa. TEL: (81) P - 31