Programmable Logic. Module: EE2C2 Digital Design. Lecturer: James Grimbleby. j.b.grimbleby reading.ac.uk. Number of Lectures: 6

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1 Programmable Logic Module: EE2C2 Digital Design Lecturer: URL: personal rdg ac stsgrimb/ j.b.grimbleby reading.ac.uk Number of Lectures: 6 Recommended course text: J. F. Wakerley Digital Design: Principles and Practices (4th ed) Prentice-Hall 2005 ISBN: School of Systems Engineering - Electronic Engineering Slide 1

2 Programmable Logic Course text: J. F. Wakerley Digital Design: Principles and Practices (4th ed) Prentice-Hall 2005 ISBN: Price: 45 (approx) School of Systems Engineering - Electronic Engineering Slide 2

3 Programmable Logic Syllabus This course of lectures deals with the technology and programming of programmable logic devices The topics that will be covered include: Technologies: fuse, anti-fuse, MOSFET, RAM Programmable ROM, EPROM Combinational and sequential logic using PROMs Programmable array logic (PAL) Programming PALs - hardware definition language Versatile PALs Generic Array Logic (GAL) Combinational and sequential logic using PALs/GALs Field-programmable gate arrays (FPGA) School of Systems Engineering - Electronic Engineering Slide 3

4 Programmable Logic Prerequities You should be familiar with the following topics: SE1EB5: Computer and Internet Technologies Boolean algebra Karnaugh maps and Boolean simplification Logic gates Implementation of combinational systems Hazards Flip-flops Implementation of sequential systems SE1EC5: Engineering g Mathematics EE2C2: Digital Design Finite-state machines School of Systems Engineering - Electronic Engineering Slide 4

5 Programmable Logic Reference text books: Digital Systems Design with Programmable Logic, Martin Bolton, Addison-Wesley, ISBN Programmable logic PLDs and FPGAs R.C. Seals and G.F. Whapshott Macmillan 1997 ISBN School of Systems Engineering - Electronic Engineering Slide 5

6 Programmable Logic Programmable logic devices (PLDs) are increasingly being used instead of standard TTL or CMOS gates Types of PLD include: PROMs, PLAs, PALs, GALs and FPGAs The logic function of PLDs is determined by the state of a number of internal links A hardware definition language (HDL) such as VHDL is used to specify the function of PLDs The HDL is compiled on a computer and downloaded to the device by a special-purpose programmer. School of Systems Engineering - Electronic Engineering Slide 6

7 Programmable Logic A single PLD can replace a number of standard logic gates with the following advantages: reduced area on circuit board higher h speed lower power consumption reduced cost increased reliability design changes without PCB modification Typically re-programmable devices are used during the development phase One-time-programmable devices are used during production School of Systems Engineering - Electronic Engineering Slide 7

8 Programmable AND A A B B +V s A A B B +V s X = A. B School of Systems Engineering - Electronic Engineering Slide 8

9 Programmable OR P Q R S 0V P Q R S 0V X = Q + S School of Systems Engineering - Electronic Engineering Slide 9

10 Programmable Logic Devices are programmed by making, or breaking, connections within the device. There are 6 main technologies: 1. Mask programmed 2. Fuse 3. Anti-fuse 4. Floating-gate: UV erasable 5. Floating-gate: gate: electrically erasable 6. RAM-based School of Systems Engineering - Electronic Engineering Slide 10

11 Mask Programmed Logic Mask-programming must be performed by the manufacturer The process is identical for all devices except for the final metallisation The final metallisation is controlled by a mask specified by the user Turn-round time is long Cost of mask is very high making this method only suitable for very large number of identical devices Mask-programmed logic is non-volatile and radiation-hard School of Systems Engineering - Electronic Engineering Slide 11

12 Fuse Programmed Logic Fuse logic is one-time-programmable Fuse is a two-terminalterminal device that is normally a low resistive element and may be blown resulting in an open circuit Typical materials are nichrome and polysilicon There may be reliability problems - the evaporated fuse material settles elsewhere on the surface of the device Fuse element is non-volatile and radiation-hard School of Systems Engineering - Electronic Engineering Slide 12

13 Anti-Fuse Programmed Logic Anti-fuse logic is one-time-programmable Anti-fuse is a two-terminal device that is normally an open circuit and may be programmed to a low resistance This is done by destructively breaking down an insulating layer Typical programmed resistances range from 25 to 500 Ω Anti-fuse is non-volatile and radiation-tolerant; tolerant; certain versions can be made radiation-hard. School of Systems Engineering - Electronic Engineering Slide 13

14 Metal-Metal Anti-Fuse Metal layers (tungsten, titanium) are separated by SiO 2 insulator and amorphous silicon Link m 1 m 2 SiO 2 m 1 m 2 SiO 2 Amorphous Si School of Systems Engineering - Electronic Engineering Slide 14

15 Floating-Gate MOSFET: UV Erasable Floating-gate MOSFET devices which can be reprogrammed UV erasable, electrically programmable Data retention > 20 years at 125 C Ceramic package incorporates a quartz window (to allow uv exposure) which is expensive Not radiation-hard School of Systems Engineering - Electronic Engineering Slide 15

16 Floating-Gate MOSFET Control gate Floating gate Drain Gate Source Insulator Si0 2 Substrate Erase using short-wavelength th ultra-violet l t light: photoelectric t emission gives floating gate a +ve charge Program by breaking down the drain-substrate diode: hot electrons cross insulator giving g floating gate a -ve charge School of Systems Engineering - Electronic Engineering Slide 16

17 Floating-Gate MOSFET Erased : gate has positive charge which lowers threshold voltage Transistor operates normally Programmed : gate has negative charge which raises threshold voltage Transistor is always OFF School of Systems Engineering - Electronic Engineering Slide 17

18 Floating-Gate MOSFET: Electrically Erasable Floating-gate MOSFET devices which can be reprogrammed Electrically erasable, electrically programmable Data retention > 20 years at 125 C Inexpensive plastic packaging Not radiation-hard School of Systems Engineering - Electronic Engineering Slide 18

19 Floating-Gate MOSFET: Electrically Erasable Control gate Floating gate Drain Gate Source Insulator Si0 2 Substrate Erase is by Fowler-Nordheim tunnelling which establishes a positive charge on the floating gate Program by breaking down the drain-substrate diode: hot electrons cross insulator giving floating gate a -ve charge School of Systems Engineering - Electronic Engineering Slide 19

20 RAM-Based PLDs A flip-flop stores the state of each link RAM-based PLDs are re-programmable and volatile RAM-based PLDs allow fast in-circuit reconfiguration The link map must be downloaded from an external source on power-up Several transistors per link leads to large chip size RAM-based PLDs are radiation-hard, but device storing the link map may be radiation-sensitive School of Systems Engineering - Electronic Engineering Slide 20

21 RAM-Based PLDs Each link consists of a flip-flop together with a transistor switch: +Vcc Flip-flop p Link School of Systems Engineering - Electronic Engineering Slide 21

22 Programmable ROM The most familiar programmable logic device is the programmable read-only memory (PROM, EPROM, EEPROM or FlashRAM) PROM typically has 10 to 19 inputs (address lines) and 8 outputs (data lines) n address lines specify 2 n locations; each location contains an 8-bit data word Each of the 8 outputs t is therefore a completely l general combinational function of the inputs School of Systems Engineering - Electronic Engineering Slide 22

23 Programmable ROM Inputs: Fixed AND matrix A B C Programmable OR matrix A. BC. A. BC. A. B. C A. BC. A. BC. A. BC. A. BC. A. BC. Outputs: W X Y Z School of Systems Engineering - Electronic Engineering Slide 23

24 EPROM: ST M27C Outputs 17 Inputs 1Mbit EPROM Organised as 128 Kwords of 8 bits (bytes) Access time: 35 ns Cost: 4 School of Systems Engineering - Electronic Engineering Slide 24

25 EPROM: ST M27C1001 Quartz window Ceramic package School of Systems Engineering - Electronic Engineering Slide 25

26 Combinational Logic Using PROMs Consider the completely-specified function F of the 4 variables A, B, C and D: F = A.( B + C + BC. ) + A. B.( C + D ) "Multiplying out" the brackets gives: F = A. B + AC. + A. BC. + A. BC.. D There is no point in simplifying the function any further since the PROM generates all the minterms A truth table is used to generate the PROM data School of Systems Engineering - Electronic Engineering Slide 26

27 Combinational Logic Using PROMs F = A. B + AC. + A. BC. + A. BC.. D A B C D F A B C D F School of Systems Engineering - Electronic Engineering Slide 27

28 Combinational Logic Using PROMs Assign: A A 3, B A 2, C A 1, D A 0 F D 0 A B C D F A B C D F 3 A 2 A 1 A 0 D 0 Addr Data A 3 A 2 A 1 A 0 D 0 Addr Data x00 0x x08 0x x01 0x x09 0x x02 0x x0A 0x x03 0x x0B 0x x04 0x x0C 0x x05 0x x0D 0x x06 0x x0E 0x x07 0x x0F 0x00 A 3 School of Systems Engineering - Electronic Engineering Slide 28

29 Combinational Logic Using PROMs Data to be programmed into a PROM is normally specified in data file which h is uploaded d to a PROM programmer A common format for specifying PROM data is Motorola S- records Unfortunately software is not available for automatically generating PROM data files from logic functions In most cases the data must be entered manually into the PROM programmer This can be time-consuming and error-prone School of Systems Engineering - Electronic Engineering Slide 29

30 Combinational Logic Using PROMs The process of defining the PROM data can be automated by writing a computer program Example: the 8-bit square root of a 16-bit integer number: #include <iostream.h> #include <math.h> h> const unsigned int address_lines = 16; const unsigned int rom_size = 1 << address_lines; unsigned int data(unsigned int address) { return (unsigned int) sqrt((double) address); } School of Systems Engineering - Electronic Engineering Slide 30

31 Combinational Logic Using PROMs Function dump_rom() will call data() with all possible address values, and print out the result: void dump_rom() { unsigned int a; cout.setf(ios::hex); } cout.fill('0'); ') for (a = 0; a < rom_size; ++a) { cout << "rom["; cout.width(4); } cout << a << "] = "; cout.width(2); cout << data(a) << "\n"; School of Systems Engineering - Electronic Engineering Slide 31

32 Combinational Logic Using PROMs In practice the program would need to be modified to output the data in S-record (or similar) form PROM A 0 D 0 A 1 D 1 Inputp : Q A 2 D 2 Output : A 14 D 6 A 15 D 7 Q School of Systems Engineering - Electronic Engineering Slide 32

33 Combinational Logic Using PROMs PROMs tend to be large and expensive compared with other types of PLD They are also slow and generate both static and dynamic hazards at the outputs PROMs can generate completely general logic functions In practice required logic functions contain a limited number of "product terms": F = A + BC.. D 2 product terms School of Systems Engineering - Electronic Engineering Slide 33

34 Sequential logic systems are usually formalised as finite- state machines (FSMs) Sequential Logic Using PROMs The elements of synchronous FSMs are: 1. A state memory consisting of D-type flip-flops 2. Combinational logic to generate the next state variables from the present state variables and the inputs 3. Combinational logic to generate the outputs from the present state variables and the inputs The combinational logic can be implemented using PROMs School of Systems Engineering - Electronic Engineering Slide 34

35 Sequential Logic Using PROMs Inputs State memory Synchronised inputs Outputs D 0 Q 0 A 0 D 0 D 1 Q 1 A 1... PROM D 3 D 2 Q 2 A 2 D 4 D 3 Q 3 A 3 D 5 D 4 Q 4 A 4 D 6 Present Next Clock state state School of Systems Engineering - Electronic Engineering Slide 35

36 Sequential Logic Using PROMs Sequence detector: X FSM Z Clock A string of 0s and 1s is assumed to be applied to the input X synchronously with the clock The output Z should become 1 for a single clock period if the sequence 1001 appears on the input School of Systems Engineering - Electronic Engineering Slide 36

37 Sequential Logic Using PROMs State diagram of sequence detector: 1/0 X/Z 0/0 1/0 0/0 0/0 S0 S1 S2 S3 1/0 0/0 1/1 4 states 2 state variables School of Systems Engineering - Electronic Engineering Slide 37

38 Sequential Logic Using PROMs 4 states 2 state variables X X s D 0 Q 0 A 0 D 0 Z Y 1 y 1 D 1 Q 1 D 2 Q 2 Y 2 y 2 PROM Y A 1 D 1 1 A 2 D 2 Y 2 Clock School of Systems Engineering - Electronic Engineering Slide 38

39 Sequential Logic Using PROMs Y-map y 1 y 2 X s =0 X s =1 00 S S S S Y 1 Y 2 Output y 1 y 2 X s =0 X s =1 00 S S S S3 0 1 Z School of Systems Engineering - Electronic Engineering Slide 39

40 Sequential Logic Using PROMs Assign: X s A 0, y 1 A 1, y 2 A 2, Z D 0, Y 1 D 1, Y 2 D 2 y 2 y 1 X s Y 2 Y 1 Z A 2 A 1 A 0 D 2 D 1 D 0 Addr Data x00 0x x01 0x x02 0x x03 0x x04 0x x05 0x x06 0x x07 0x04 School of Systems Engineering - Electronic Engineering Slide 40

41 Sequential Logic Using PROMs There are some drawbacks to PROM-based FSMs: 1. The clock frequency is limited by the response time of the PROM 2. Following a clock transition the outputs will exhibit static and dynamic hazards 3. PROMs are larger, more expensive and power hungry than alternative PLDs 4. Software is not available for programming PROM-based FSMs School of Systems Engineering - Electronic Engineering Slide 41

42 Programmable Array Logic Programmable Array Logic devices (PALs) typically generate 8 output logic functions of 10 inputs and 6 of the outputs themselves The logic functions are not completely general as in PROMs but typically allow 8 product terms The feedback means that PALs can be programmed to act as asynchronous FSMs Some PALs contain D-type flip-flops flops on their outputs and so can be used as synchronous counters and FSMs. School of Systems Engineering - Electronic Engineering Slide 42

43 Programmable Array Logic Inputs: A B C Fixed OR matrix Program- mable AND matrix Outputs: W X Y Z School of Systems Engineering - Electronic Engineering Slide 43

44 Programmable Array Logic: MMI PAL16L8 Technology: bipolar, one-time programmable Outputs: 8, inputs: 10, feedback: 6 Number of product terms: 7 Package: 20-pin DIL or surface mount Delay time input change to output: 25 ns Power supply: 120 ma at 5 V Cost: N/A (replaced by V series PALs and GALs) School of Systems Engineering - Electronic Engineering Slide 44

45 Programmable Logic: PAL16L8 School of Systems Engineering - Electronic Engineering Slide 45

46 Programmable Logic: PAL16L8 1 product term 7 product terms Tri-state control Output Feedback School of Systems Engineering - Electronic Engineering Slide 46

47 Combinational Logic Using PALs The logic function of a PAL is defined by making/breaking appropriate links in the AND matrix The link data could in principle be entered into the PAL programmer manually In practice the logic function is specified either by schematic entry or by hardware description language (HDL) The most popular HDLs for small programmable logic devices are ABEL, CUPL, OPAL and PALASM School of Systems Engineering - Electronic Engineering Slide 47

48 Combinational Logic Using PALs The specification written in a HDL is compiled on a PC to produce a JEDEC fuse map file Most HDL compilers incorporate a simulator which allows the design to be tested before programming a device The JEDEC file is uploaded to the PAL programmer This device is then programmed A security link on the device can be set to prevent the link data from being read (to prevent reverse engineering) School of Systems Engineering - Electronic Engineering Slide 48

49 Combinational Logic Using PALs Design Write HDL spec Create JEDEC Compile Upload Yes Errors? No Simulate Program PAL In-circuit test Yes No Yes Errors? Errors? No School of Systems Engineering - Electronic Engineering Slide 49

50 CUPL Definition File: Boolean Expression Name EX1; Partno EX0000; Date 6/10/98; Rev 01; Designer J.B.Grimbleby; Company University of Reading; Assembly None; Location None; Device p16l8; /* input pins */ PIN 1 = A; PIN 2 = B; PIN 3 = C; PIN 4 = D; /* output t pins */ PIN 19 = F; F = A.( B + C + BC. ) + A. B.( C + D) Boolean Operator Symbols:! NOT & AND # OR /* equations */ F =!A & (B # C #!B &!C) # A & B &!(C # D); School of Systems Engineering - Electronic Engineering Slide 50

51 CUPL Documentation File Expanded Product Terms:!F => A &!B # A & C # A & D F.oe => 1 Symbol Table: Pin Variable Pterms Max Min Pol Name Ext Pin Type Used Pterms Level A 1 V B 2 V C 3 V D 4 V F 19 V F oe 19 D School of Systems Engineering - Electronic Engineering Slide 51

52 CUPL Documentation File Fuse Plot: xx x-x x-----x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Chip Diagram: EX1 A x x Vcc B x x F C x x D x x x x x x x x x x x x GND x x School of Systems Engineering - Electronic Engineering Slide 52

53 JEDEC Output File CUPL(WM) 4.9a Serial# MW Device p16l8 Library DLIB-h-39-8 Created Mon Oct 05 19:23: Name EX1 Partno EX0000 Revision 01 Date 6/10/98 Designer J.B.Grimbleby Company University of Reading Assembly None Location None *QP20 *QF2048 *G0 *F0 *L *L *L *L *C0FD1 *76D1 School of Systems Engineering - Electronic Engineering Slide 53

54 PAL16L8 Implementation B B A A A. B A. A. B. BC.. C... = 0 A.C A.D F B A C D School of Systems Engineering - Electronic Engineering Slide 54

55 CUPL Definition File: Truth Table /* input pins */ PIN 1 = p; PIN 2 = q; PIN 3 = r; /* output pins */ PIN 19 = aa; PIN 18 = a; PIN 17 = bb; PIN 16 = b; /* truth table */ table p, q, r => a, b, aa, bb { 'b'000 => 'b'1000; 'b'001 => 'b'1100; 'b'010 => 'b'0100; 'b'011 => 'b'0110; 'b'100 => 'b'0010; 'b'101 => 'b'0011; 'b'110 => 'b'0001; 'b'111 => 'b'1001; } School of Systems Engineering - Electronic Engineering Slide 55

56 CUPL Documentation File Expanded Product Terms: a =>!p &!q # p & q & r aa => p &!q #!p & q & r b =>!p & q #!p & r bb => p & q # p & r School of Systems Engineering - Electronic Engineering Slide 56

57 CUPL Simulation ORDER: p, q, r, %2, a, aa, b, bb; VECTORS: 000**** 001**** 010**** 011**** 100**** 101**** 110**** 111**** 000**** 001**** 010**** 011**** 100**** 101**** 110**** 111**** Input file ================== a b pqr aabb ================== 0001: 000 HLLL 0002: 001 HLHL 0003: 010 LLHL 0004: 011 LHHL 0005: 100 LHLL 0006: 101 LHLH 0007: 110 LLLH 0008: 111 HLLH 0009: 000 HLLL 0010: 001 HLHL 0011: 010 LLHL 0012: 011 LHHL 0013: 100 LHLL 0014: 101 LHLH 0015: 110 LLLH 0016: 111 HLLH Output File School of Systems Engineering - Electronic Engineering Slide 57

58 CUPL Simulation School of Systems Engineering - Electronic Engineering Slide 58

59 CUPL Definition File: From Schematic A B C D s t F p q r p = BC. s = C + D q = B + C + p t = A. B. s r = A. q F = r + t School of Systems Engineering - Electronic Engineering Slide 59

60 CUPL Definition File: From Schematic /* input pins */ PIN 1 = A; PIN 2 = B; PIN 3 = C; PIN 4 = D; p = BC. ; q = B + C + p r = A. q s = C + D t = A. B. s F = r + t /* output pins */ PIN 19 = F; /* intermediate variables */ p =!B &!C; q = B # C # p; r =!A & q; s =!(C # D); t = A & B & s; /* equations */ F = r # t; School of Systems Engineering - Electronic Engineering Slide 60

61 CUPL Definition File: From Schematic F =>!A!A # B &!C &!D p =>!B &!C q => B # C #!B &!C r =>!A & B #!A &!B &!C #!A & C s =>!C &!D t => A & B &!C &!D School of Systems Engineering - Electronic Engineering Slide 61

62 CUPL Definition File: From Schematic Pin Variable Pterms Max Min Pol Name Ext Pin Type Used Pterms Level A 1 V B 2 V C 3 V D 4 V F 19 V p 0 I q 0 I r 0 I s 0 I t 0 I School of Systems Engineering - Electronic Engineering Slide 62

63 CUPL Definition File: From Schematic Fuse Plot: x x----x---x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Chip Diagram: Schematic A x x Vcc B x x F C x x D x x x x x x x x x x x x GND x x School of Systems Engineering - Electronic Engineering Slide 63

64 Registered PALs: PAL16R8 School of Systems Engineering - Electronic Engineering Slide 64

65 Registered PALs: PAL16R8 Clock 8 product terms Output Feedback Tri-state control School of Systems Engineering - Electronic Engineering Slide 65

66 Versatile PALs Versatile PALs have a macrocell on each output Each macrocell can be programmed to be combinational or registered, and active-low or active-high The macrocell on each output allows a versatile PAL to emulate a range of simple PALs For example a PAL16V8 can replace any 20-pin PAL such as: PAL16L8, PAL18R8, PAL16R4, PAL16R6, PAL16H8 Consequently simple PALs are now effectively obsolete School of Systems Engineering - Electronic Engineering Slide 66

67 Versatile PALs: PAL16V AR D Q 00 Q SP 01 MPX 0 MPX 1 S 1 S 0 Versatile PAL macrocell School of Systems Engineering - Electronic Engineering Slide 67

68 Versatile PALs: PAL16V8 AR Q D SP Q S 1 =0, S 0 =0: Registered active-low School of Systems Engineering - Electronic Engineering Slide 68

69 Versatile PALs: PAL16V8 AR Q D SP Q S 1 =0, S 0 =1: Registered active-high School of Systems Engineering - Electronic Engineering Slide 69

70 Versatile PALs: PAL16V8 S 1 =1, S 0 =0: Combinational active-low School of Systems Engineering - Electronic Engineering Slide 70

71 Versatile PALs: PAL16V8 S 1 =1, S 0 =1: Combinational active-high School of Systems Engineering - Electronic Engineering Slide 71

72 Generic Array Logic GALs are similar to versatile PALs except that they use floating-gate/electrical erase technology GALs can therefore be reprogrammed GALs use CMOS technology resulting in a lower power consumption than bipolar technology PALs GALs are as fast, or faster, than bipolar technology PALs Being reprogrammable GALs can be fully tested t by the manufacturer School of Systems Engineering - Electronic Engineering Slide 72

73 Generic Array Logic: Lattice GAL16V8 Technology: cmos, re-programmable Outputs: 8, inputs: 10, feedback: 6 Number of product terms: 8 Package: 20-pin DIL or surface mount Delay time input change to output: 3.5 ns Power supply: 75 ma at 5 V Cost: 2 School of Systems Engineering - Electronic Engineering Slide 73

74 Sequential Logic Using PALs Three-stage Johnson-code counter C B A D Q D Q D Q Input Q Q Q /* input pins */ /* output pins */ /* equations */ PIN 1 = clock; PIN 19 = A; PIN 18 = B; PIN 17 = C; A.d = B; B.d = C; C.d =!A; School of Systems Engineering - Electronic Engineering Slide 74

75 Sequential Logic Using PALs ORDER: clock, %2, A, B, C; VECTORS: P000 C*** C*** C*** C*** C*** C*** C*** C*** C*** C*** C*** Simulation input =============== c k ABC =============== 0001: P : C LLH 0003: C LHH 0004: C HHH 0005: C HHL 0006: C HLL 0007: C LLL 0008: C LLH 0009: C LHH 0010: C HHH 0011: C HHL 0012: C HLL 0013: C LLL Simulation output School of Systems Engineering - Electronic Engineering Slide 75

76 Sequential Logic Using PALs School of Systems Engineering - Electronic Engineering Slide 76

77 Sequential Logic Using PALs School of Systems Engineering - Electronic Engineering Slide 77

78 Sequential Logic Using PALs Johnson-code counter works correctly provided that it starts in one of the states of the counting sequence However, the unused states (010, 101) cycle To prevent this the equations must be changed to force one of the unused states back to the correct sequence Force state 101 to go to state 011: /* equations */ A.d = B; B.d = C; C.d =!A #!B & C; School of Systems Engineering - Electronic Engineering Slide 78

79 Sequential Logic Using PALs School of Systems Engineering - Electronic Engineering Slide 79

80 Finite State Machines Using PALs C1 0/0 0/0 x/z 1/1 1/0 C0 1/0 0/1 C2 Modulo-3 up/down counter (Moore machine) School of Systems Engineering - Electronic Engineering Slide 80

81 FSM (Moore) Definition File /* input pins */ PIN 1 = clock; PIN 2 = x; 3 states t 2 state t variables /* output pins */ PIN 16 = z; /* feedback pins */ PIN 15 = xs; /* state variables */ PIN 17 = u; PIN 18 = v; $DEFINE C0 'b'00 $DEFINE C1 'b'01 $DEFINE C2 'b'10 $DEFINE C3 'b'11 Synchronised input x State variables must be assigned to output pins States must be assigned representations (including unused states) School of Systems Engineering - Electronic Engineering Slide 81

82 FSM (Moore) Definition File xs.d = x; sequence u,v { present C0 if xs next C1; default next C2; Synchronised input x Output z set for this state (independent of input) } out z; present C1 if xs next C2; default next C0; present C2 if xs next C0; default next C1; present C3 default next C0; Output z not set for these states School of Systems Engineering - Electronic Engineering Slide 82

83 FSM (Moore) Documentation Expanded Product Terms: u.d =>!u & v & xs #!u &!v &!xs v.d =>!u &!v & xs # u &!v &!xs xs.d => x 2 product terms 2 product terms 1 product term z =>!u &!v School of Systems Engineering - Electronic Engineering Slide 83

84 FSM (Moore) Simulation ORDER: clock, x, %2, =================== xs, u, v, %2, z; c x kx suv z =================== VECTORS: 0001: P P : C0 LHL L C0**** 0003: C0 LLH L C0**** 0004: C0 LLL H C0**** C0**** C0**** C0**** C1**** C1**** C1**** C1**** C1**** C1**** Input file 0005: C0 LHL L 0006: C0 LLH L 0007: C0 LLL H 0008: C1 HHL L 0009: C1 HLL H 0010: C1 HLH L 0011: C1 HHL L 0012: C1 HLL H 0013: C1 HLH L Output file School of Systems Engineering - Electronic Engineering Slide 84

85 FSM (Moore) Simulation School of Systems Engineering - Electronic Engineering Slide 85

86 FSM (Mealy) State Diagram x/z 1/0 0/0 0/0 0/0 S0 1/0 S1 S2 S3 0/0 1/0 1/1 Sequence detector: Detects sequence 1001 on input x School of Systems Engineering - Electronic Engineering Slide 86

87 FSM (Mealy) State Definition File /* input pins */ PIN 1 = clock; PIN 2 = x; /* output pins */ PIN 16 = z; /* feedback pins */ PIN 15 = xs; /* state variables */ PIN 17 = u; PIN 18 = v; $DEFINE s0 'b'00 $DEFINE s1 'b'01 $DEFINE s2 'b'11 $DEFINE s3 'b'10 xs.d = x; sequence u,v { present s0 if xs next s1; default next s0; present s1 if xs next s1; default next s2; present s2 if xs next s1; default next s3; present s3 next s0; if xs out z; } School of Systems Engineering - Electronic Engineering Slide 87

88 FSM (Mealy) Documentation Expanded d Product Terms: u.d => v &!xs v.d =>!u & v #!u & xs # v & xs xs.d => x z => u &!v & xs z.oe => 1 School of Systems Engineering - Electronic Engineering Slide 88

89 FSM (Mealy) Simulation ORDER: clock, x, %2, xs, u, v, %2, z; =================== c x kx suv z VECTORS: =================== P : P C0**** 0002: C0 LLL L C1**** 0003: C1 HLL L C0**** 0004: C0 LLH L C0**** 0005: C0 LHH L C0**** C1**** C0**** C1**** C0**** C0**** C1**** C0**** C0**** Input file 0006: C0 LHL L 0007: C1 HLL L 0008: C0 LLH L 0009: C1 HHH L 0010: C0 LLH L 0011: C0 LHH L 0012: C1 HHL H 0013: C0 LLL L 0014: C0 LLL L Output file School of Systems Engineering - Electronic Engineering Slide 89

90 FSM (Mealy) Simulation S2 S1 S2 S1 S2 S1 S2 S3 S0 S1 S2 School of Systems Engineering - Electronic Engineering Slide 90

91 Bus Systems A common requirement in digital electronics is to connect a number of devices to a common data path This arrangement is used in microprocessor systems Such a common data path is called a bus Device Device Device Device #1 #2 #3 #4 A bus consists of a number of wires, each wire carrying one bit of a complete word School of Systems Engineering - Electronic Engineering Slide 91

92 Bus Systems Such a data bus cannot be implemented with normal logic gates This is because each of the devices connected to the bus would independently try to establish a binary value on the lines Connecting gate outputs in parallel lead to contention This can be avoided by using tri-state or open-collector logic School of Systems Engineering - Electronic Engineering Slide 92

93 Tri-State Logic This is also sometimes called "three-state logic Tri-state logic devices have three possible output states: logic 0 logic 1 undefined (high impedance) X Such devices have, in addition to the normal inputs, a tri-state control input This is usually called "output enable or OE School of Systems Engineering - Electronic Engineering Slide 93

94 Tri-State Logic A tri-state inverting buffer has a symbol: A B OE Truth table for this inverting buffer: A OE B 0 0 X 1 0 X School of Systems Engineering - Electronic Engineering Slide 94

95 Tri-State Logic The outputs of tri-state devices can be connected together One, and only one, device connected to the bus can have OE=1, all other devices must have OE=0 A combinational logic circuit should prevent more than one device having OE=1 Each of the outputs on a GAL has tri-state capability The tri-state t t control is a logic function of the inputs, but is limited to one product term School of Systems Engineering - Electronic Engineering Slide 95

96 Open-Collector Logic Open-collector logic devices have output circuits that can pull down to logical 0, but cannot pull up to logical 1 Such devices can be represented by a logic block followed by a bipolar junction transistor: Output t Inputs logic In other words, the output can be considered to be a switch to zero volts School of Systems Engineering - Electronic Engineering Slide 96

97 Open-Collector Logic Any number of open-collector outputs can be connected, together with a single "pull-up" up resistor to give a bus system: R +5V Connection of open-collector devices in this way gives "wired AND" School of Systems Engineering - Electronic Engineering Slide 97

98 Open-Collector Logic Some bus systems employing open-collector logic use an active-low representation When active-low logic is used the connection of open-collector gates gives "wired-or" The speed at which open-collector bus systems can operate is determined by the bus capacitance and the value of the pull-up resistor If the total bus capacitance is 200 pf and the pull-up up resistor is 500 Ω then the time constant is 100 ns School of Systems Engineering - Electronic Engineering Slide 98

99 Open-Collector Logic Active-low, open-collector logic can be emulated using a tri- state inverting logic gate: 1 Output B Input A A B 0 X 1 0 This can be used to allows GALs (which have tri-state outputs) to interface to wired-or systems School of Systems Engineering - Electronic Engineering Slide 99

100 Address Decoding using GALs School of Systems Engineering - Electronic Engineering Slide 100

101 Address Decoding using GALs This address decoder can be implemented entirely in a single GAL: The advantages of using a GAL are PCB space, power consumption, o reliability and re-programmability poga ab School of Systems Engineering - Electronic Engineering Slide 101

102 Address Decoding using GALs CUPL definition file: /* input pins */ /* feedback pins */ PIN 1 = clock; PIN 13 = u0; PIN 2 = a20; PIN 14 = u1; PIN 3 = a21; PIN 4 = a22; /* equations */ PIN 5 = a23;!cs.d =!dav & a23 & a22 &!a21 &!a20; PIN 6 = dav; u0.d =!cs; /* output pins */ u1.d = u0; PIN 19 = cs; PIN 18 = dta; dta = 'b'0; dta.oe = u1; School of Systems Engineering - Electronic Engineering Slide 102

103 Address Decoding using GALs ORDER: clock, a23, a22, a21, a20, dav, %2, cs, u0, u1, dta; VECTORS: CXXXX1**** CXXXX1**** CXXXX1**** C11001**** C11000**** C11000**** C11000**** C11001**** CXXXX1**** CXXXX1**** CXXXX1**** CXXXX1**** ===================== caaaad d l2222a cuut k3210v s01a ===================== 0001: CXXXX1 HLHL 0002: CXXXX1 HLLZ 0003: CXXXX1 HLLZ 0004: C11001 HLLZ 0005: C11000 LLLZ 0006: C11000 LHLZ 0007: C11000 LHHL 0008: C11001 HHHL 0009: CXXXX1 HLHL 0010: CXXXX1 HLLZ 0011: CXXXX1 HLLZ 0012: CXXXX1 HLLZ School of Systems Engineering - Electronic Engineering Slide 103

104 Address Decoding using GALs School of Systems Engineering - Electronic Engineering Slide 104

105 Asynchronous FSM using PALs Pulse gate state diagram Pulses on input p are gated by q pq 0X 1X B A D 1X 0X 0X School of Systems Engineering - Electronic Engineering Slide 105

106 Asynchronous FSM using PALs Pulse gate state table Next state Present Output state p=0 p=0 p=1 p=1 z q=0 q=1 q=1 q=0 A (A) (A) D B 0 B A A (B) (B) 0 D A A (D) (D) 1 4 state 2 state variables Assignments for A and D, and A and B must be unit distant School of Systems Engineering - Electronic Engineering Slide 106

107 Asynchronous FSM using PALs /* input pins */ PIN 1 = p; table p, q, u, v => u, v { PIN 2 = q; 'b'00a => 'b'a; 'b'01a => 'b'a; /* output pins */ 'b'11a => 'b'd; PIN 19 = z; 'b'10a => 'b'b; PIN 18 = u; 'b'00b => 'b'a; PIN 17 = v; 'b'01b => 'b'a; 'b'11b => 'b'b; $DEFINE A 00 $DEFINE B 01 $DEFINE D 10 $DEFINE X 11 table u, v => z { 'b'a => 'b'0; 'b'b => 'b'0; 'b'd => 'b'1; 'b'x => 'b'0; } } 'b'10b => 'b'b; 'b'00d => 'b'a; 'b'01d => 'b'a; 'b'11d => 'b'd; 'b'10d => 'b'd; 'b'00x => 'b'a; 'b'01x => 'b'a; 'b'11x => 'b'a; 'b'10x => 'b'a; School of Systems Engineering - Electronic Engineering Slide 107

108 Asynchronous FSM using PALs Expanded Product Terms: u => p & q &!v # p & u &!v v => p &!q &!u # p &!u & v z => u &!v u.oe => 1 v.oe => 1 z.oe => 1 School of Systems Engineering - Electronic Engineering Slide 108

109 Asynchronous FSM using PALs ORDER: p, q, %2, u, v, %2, z; ================== pq uv z VECTORS: ================== 00*** 0001: 00 LL L 00*** 0002: 00 LL L 10*** 0003: 10 LH L 10*** 0004: 10 LH L 00*** 0005: 00 LL L 01*** 0006: 01 LL L 11*** 0007: 11 HL H 11*** 0008: 11 HL H 01*** 0009: 01 LL L 00*** 0010: 00 LL L 10*** 0011: 10 LH L 11*** 0012: 11 LH L 01*** 0013: 01 LL L 01*** 0014: 01 LL L 11*** 0015: 11 HL H 10*** 0016: 10 HL H 00*** 0017: 00 LL L 00*** 0018: 00 LL L 00*** 0019: 00 LL L School of Systems Engineering - Electronic Engineering Slide 109

110 Asynchronous FSM using PALs S2 S1 S2 S1 S2 S1 S2 S3 S0 S1 S2 School of Systems Engineering - Electronic Engineering Slide 110

111 Complex PLDs and FPGAs The devices discussed so far (PALs and GALs) are simple PLDs (SPLDs) These are suitable for implementing simple combinational and sequential logic functions For more complex functions it is necessary to use: Programmable Logic Arrays (PLAs), or Field-Programmable Gate ARRAYs (FPGAs) School of Systems Engineering - Electronic Engineering Slide 111

112 Programmable Logic Array Inputs: A B C Programmable OR matrix Program- mable AND matrix Outputs: W X Y Z School of Systems Engineering - Electronic Engineering Slide 112

113 Field-Programmable Gate Array Logic blocks Programmable links Input/output blocks School of Systems Engineering - Electronic Engineering Slide 113

114 Field-Programmable Gate Array Logic blocks Programmable links School of Systems Engineering - Electronic Engineering Slide 114

115 Field-Programmable Gate Array Typical FPGA: QuickLogic pasic3 Technology: CMOS 4-layer metal Programming: Antifuse Usable logic gates: Logic cells: Flip-flops (max): I/O (max) Cell speed: 2 ns Routability: 100% Operating voltage: 3.33 V (5 V tolerant) Packages: PLCC, TQFP, PQFP, PBGA School of Systems Engineering - Electronic Engineering Slide 115

116 pasic3 Logic Cell Mux Inputs Outputs t D-type flip-flop flop School of Systems Engineering - Electronic Engineering Slide 116

117 pasic3 Logic Cell A pasic3 logic cell can be configured to be: one 16-input AND gate two 6-input AND gates + two 4-input AND gates two 6-input AND gates + two 2:1 multiplexers two 6-input AND gates + one 4:1 multiplexer one 5-input XOR gate one 3-input XOR gate + one 2-input XOR gate one D-type flip-flop with async preset and clear one RS-type flip-flop with async preset and clear one JK-type flip-flopflop with async preset and clear one T-type flip-flop with async preset and clear etc... School of Systems Engineering - Electronic Engineering Slide 117

118 FPGA Development Tools There are two approaches to FPGA design: Schematic entry: The design is entered as a hierarchical schematic using gates and flip-flopsflops This is typically used for small to medium size systems Schematics are easy to understand and modify HDL entry: The design is specified using a HDL (VHDL or Verilog) Large systems are almost always specified using a HDL Difficult to get an overview of a design specified using a HDL School of Systems Engineering - Electronic Engineering Slide 118

119 Hardware Definition Languages g VHDL: Very High speed integrated circuit Description Language Initiated by American DoD as a specification language Standardised by IEEE Verilog First real commercial HDL language Industry standard for many years Standardised by IEEE School of Systems Engineering - Electronic Engineering Slide 119

120 Functional Simulation Functional simulation can be done after the schematic has been entered or a HDL file has been created Functional simulation gives information about the logical operation of the system It does not provide any information about timing delays The functional simulation uses a stimulus file which h defines the input signals to predict the outputs The simulation examples given for the PAL/GAL designs are functional simulations School of Systems Engineering - Electronic Engineering Slide 120

121 Place and Route If the results of functional simulation are satisfactory then the design is compiled to produce an EDIF netlist EDIF files can be exchanged between different design tools A place and route tool is used to fit the design to a specific FPGA device This process can be very time-consuming, particularly if the device usage approaches 100% The result is a fuse map file that can be used to program the FPGA School of Systems Engineering - Electronic Engineering Slide 121

122 Post-Layout Simulation Once the place and route operation is complete the circuit delays can be back-annotated to the netlist These delays are estimated from the track resistance and parasitic capacitance This allows a timing simulation to be performed which incorporates realistic delays It is at this stage that hazards and races may become apparent (that would not appear in the functional simulation) If the post-layout simulation is satisfactory then the device can be programmed School of Systems Engineering - Electronic Engineering Slide 122

123 Programmable Logic J. B. Grimbleby, 20 October 2008 School of Systems Engineering - Electronic Engineering Slide 123