# Chapter 4. Combinational Logic. Dr. Abu-Arqoub

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1 Chapter 4 Combinational Logic

2 Introduction N Input Variables Combinational Logic Circuit M Output Variables 2

3 Design Procedure The problem is stated 2 The number of available input variables & required output variables are determined 3 The input & output variables are assigned letter symbols 4 The truth table that defines the required relationships between the inputs & outputs is derived 5 The simplified Boolean function for each output is obtained 6 The logic diagram is drawn 3

4 Example Design a system with three switches and two lamps, where The first lamp on only if any two sequence switches are on The second lamp on only if the first and the last switches on The three switches are on doesn't occur On -> Off -> 4

5 Example Number of inputs 3 Number of outputs 2 Let the three inputs be a, b, & c Let the two outputs be L, & L2 Truth Table: L2 L c b a X X 5

6 Example Boolean Function for the outputs: L= bc + ab L2= ac 6

8 Adders Number of inputs 2 Number of outputs 2 (2 bits to be added) (the sum & carry of two bits) Let two input bits be X, Y & the sum (S) & the carry (C) Truth Table: X Y S C 8

9 Adders X Y Combinational Logic Circuit For HA S C Boolean Function for the outputs: S = X Y + XY = X Y C = XY 9

10 Adders S = X Y = (X Y) = (XY + X Y ) = (C + X Y ) HA

11 Full Adder It s the arithmetic sum of three input bits (the sum of two significant bits & the carry from the previous lower significant position) Design a combinational logic circuit to perform the addition of 3 bits (sum of 2 bits & the carry) Number of Inputs 3 Number of outputs 2 (2 bits & carry) (sum & carry) Let the inputs be X, Y, C in Let the outputs be S, C out C out + X Y S C in

12 Full Adder Truth Table: C out S C in Y X 2

13 Full Adder Boolean functions for the outputs: No Simplification S = XY C in + X YC in + XYC in + X Y C in 3

14 Full Adder C out = YC in + XC in + XY S = XY C in + X YC in + XYC in + X Y C in = C in (XY + X Y) + C in (XY + X Y ) = C in (X Y) + C in (X Y) = C in Z + C in Z = C in Z = C in (X Y) 4

15 Full Adder C out = XY C in + X YC in + XYC in + XYC in = C in (XY + X Y) + XY (C in + C in ) = C in (X Y) + XY FA 5

16 Subtractors Problem: Using a combinational logic circuit, Design a Half Subtractor (HS) 2 a Full Subtractor (FS) Half Subtractor: Inputs X, Y Outputs D, B (Borrow) b X - Y d 6

17 Subtractors Truth Table: X Y B D B = X Y D = X Y + XY = X Y 7

18 Subtractors 2 Full Subtractor: Inputs X, Y, Bp (Bp is the previous borrow) Outputs Bn, D (Bn is the next borrow) Truth Table: X Y Bp Bn D Bn x - y Bp Bn D 8

19 Full Subtractor: 9

20 Subtractors D = X Y Bp + X YBp + XY Bp + XYBp Bn = X Y + X Bp + YBp 2

21 Code Conversion Ex: Design a combinational logic circuit to perform a conversion from the BCD to the Excess-3 code Inputs 4 (A, B, C, D) Outputs 4 (W, X, Y, Z) 2

22 Code Conversion Truth Table: Output Excess-3 Input BCD Z Y X W D C B A x x x x x x x x 22

23 Code Conversion W = m 5 + m 6 + m 7 + m 8 + m 9 X = m + m 2 + m 3 + m 4 + m 9 Y = m + m 3 + m 4 + m 7 + m 8 Z = m + m 2 + m 4 + m 6 + m 8 W = A + BC + BD 23

24 Code Conversion X = B C + B D + BC D 24

25 Code Conversion Y = CD + C D 25

26 Code Conversion Z = D 26

27 Code Conversion W = A + BC + BD = A + B (C + D) X = B C + B D + BC D = B (C + D) + BC D = B (C + D) + B ( C + D) Y = CD + C D = CD + (C + D) Z = D 27

28 Analysis Procedure The analysis of a combinational circuit is the reverse process of the design of a combinational logic circuit It starts with a given logic diagram & ends with a set of Boolean functions, a truth table, or a verbal explanation of the circuit operation 28

29 Analysis Procedure Ex: Given the following logic circuit, analyze it: 29

30 Analysis Procedure R=XY R2=XZ R3=YZ F (X, Y, Z) = R + R 2 + R 3 = XY + XZ + YZ F 2 (X, Y, Z) = F(X,Y,Z) = (XY + XZ + YZ) = (X + Y ) (X + Z ) (Y + Z ) Truth Table: 3 F 2 = (F ) F = R + R 2 + R 3 R 3 = YZ R 2 = XZ R = XY Z Y X 3

31 Analysis Procedure Ex2: Given the following logic circuit, analyze it: R = (XY) R 2 = (R Z) F (X, Y, Z) = (R 2 X) R 2 = (RZ)=((XY) Z) = XY + Z F (X, Y, Z) = ((XY + Z ) X) = (XY + Z ) + X = Z (X + Y ) + X = ZX + ZY + X = X + ZY 3

32 Analysis Procedure Truth Table: 32 F = X + Y Z Y Z X Z Y X F = (R 2 X) R 2 = (R Z) R = (XY) OR 32

33 Analysis Procedure Ex3: Analyze the following logic circuit: F = (R 2 + Y), R 2 = (R + Z) R = (X + Y) R 2 = ((X + Y) + Z) F = (((X + Y) + Z) + Y) F = Y (X + Z) 33

34 Truth Table: Analysis Procedure X Y Z F (X, Y, Z) 34

35 Homework design a binary multiplier that multiplies two numbers each of them a two bit numer 2 design a circuit (incrementer) that adds one to a 4- bit binary number (use 4 half adders) 3 obtain the simplified Boolean expressions for output F and G in terms of the input variables in the circuit 35

36 Homework 4 Design a combinational circuit with 3 inputs and output the output is when the binary value of the inputs is less than 3, otherwise the output is 5 A majority circuit is a combinational circuit whose output is equal to if the input variables have more s than s, otherwise the output is design a 3-input majority circuit 36

37 Homework Q4 A parity generator circuit is a circuit that generates parity bit that is used for the purpose of detecting errors during transmission of binary information A parity bit is an extra bit included with a binary message to make the number of 's either odd or even Design a 3-bit combinational even parity generator circuit The circuit has three inputs: x, y, and z, which are constituted the message, and one output: p, which is constituted the parity bit The circuit functions as the following: The output (p) has the value only and only if the number of 's on the input lines (x, y, z) is odd, otherwise the output (p) has the value Note: in designing of the above circuit, please use only XOR gates 37

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