Coping with Variability in Semiconductor Manufacturing

Transcription

1 1 Coping with Variability in Semiconductor Manufacturing Costas J. Spanos Berkeley Computer Aided Manufacturing Department of EECS University of California, Berkeley 12/6/04

2 2 The Traditional Semiconductor Manufacturing Environment IC Design Mead & Conway design rules Manufacturing Process Development

3 3 Introduction Error budgets cannot keep up with shrinking dimensions. In the sub-100nm generations, Critical Dimensions (CDs) are hard to control. Typical problem: manufacture 65nm features, and try to keep error at +/- ~5nm. Most of the time, one can only measure those features with +/- 2nm precision!

4 4 The objective is to maintain both Wafer to Wafer and Across Wafer CD Uniformity Bad Good

5 5 Outline Measuring Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process

6 Spin/Coat: Across-Wafer 6 Sources of CD Variation Exposure: Across-Field PEB: Across-Wafer Deposition: Across-Wafer Across-Lot Total CD Variation Etch: Across-Wafer Develop: Across-Wafer Systematic CD variation components with different frequencies are combined.

7 7 Processing Sequence wafers to be processed processing equipment finished wafer What was the state of the wafer during processing?

8 8 Smart Sensor Wafers In situ sensor array, with integrated power and telemetry Applications: process control, calibration, diagnostics & monitoring, process design

9 9 The Approach processing equipment SensorWafer feedback process control data wafers to be processed base station

10 : Off-the-shelf Components, Ni on Al, Solder Paste Mount LED batteries PIC voltage regulator thermistor resistor capacitor s 100mm

11 11 Today: The Sensor Wafer SiO 2 polyimid module Courtesy OnWafer Technologies

12 12 Much more than you ever wanted to know about Post Exposure Bake Overshoot Steady Heating Cooling 200mm ArF 90nm 130 o C 60sec Courtesy OnWafer Technologies Chill

13 13 On-Wafer Plasma Monitoring 200mm Poly Etching Routine He Reduced He main etch pre-etch over etch de-chuck

14 14 Cool chuck - 200mm Poly Etching main etch Temperature fluctuations during main etch

15 15 Can see rotating magnetic field! phase delay in temp fluctuation Can calculate B-field period Can see rotation is clockwise

16 16 Next Step: Zero-Footprint Metrology Wafer Data Transmission Dielectric Layer 500µm Si Photo-/RF Transmitter Data Processing, Storage Unit Battery Data Acquisition Unit Prototyping a zero-footprint metrology wafer with optical detection unit and encapsulated power source.

17 17 Proposed Architecture Power Management & RF Transmission Unit Self-contained wireless transmitter Power Measurement Units Integrated excitation/detection Unit Power Unit Thin film Battery

18 18 3 x 3 Pixels Optical Metrology Prototype Bottom Wafer with LED Photodetector integrated Top Wafer

19 Feasibility Test: Thickness Measurement 19 Green LED Blue LED 5mm Test Coating Glass Slide LED Filter PD Si Packaging Substrate Reflection Intensity (a.u.) Shipley S1818 PR on Glass Slide Excitation λ=525nm PR Thickness (nm) Theoretical Curve

20 20 Wireless Aerial Image Metrology light Mask Image system Mask image NA Partial coherence Illumination aberrations Defocus magnification Aerial image Latent image Resist image Wafer

21 21 An Integrated Aerial Image Sensor Dark contact mask forms a moving aperture to capture incident electromagnetic field. Mask aperture Poly-silicon mask Photodetector Substr ate Φ 1 Φ 2 Φ 3 Φ 1 Φ 2 Φ 3 p-si How can a µm detector retrieve nanometerscale resolution of of the aerial image?

22 22 Moiré Patterns for Spatial Frequency Shift Patterns Overlap Pattern rotates 4 o Pattern rotates 8 o Pattern rotates 16 o Wide CD Narrow CD

23 Aperture pattern shift testing Detector mask layout design Image pattern Detect pattern d image pattern intensity Mask layout x(pixel) Measurement result

24 24 Near-Field Optical Simulation mask Intensity at the center of the simulation domain

25 25 Outline Measuring Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process

26 26 Manufacturing Evolution Model & Controller RT equipment model Diagnostic Engine

27 27 Advanced Process Control (from Previous tool) Post-Process Measurements For Feedforward Control Run to Run Controller Process Model Automatic Fault Detection Summarized In-Situ Measurements Updated Recipe Real Time Equipment Controller Equipment Model Modified Recipe Equipment State In-Situ Sensors Proce ss State Post-Process Measurements Wafer State Metrology (to next tool) Courtesy AMD Drift Noise

28 Courtesy AMD 28 Factory Wide Control with Real-Time Optimization Demand Profile Factory Wide Control Manufacturing Constraints Supervisory Control Predictive Yield Modeling Dynamic Scheduling Transistor/Isolation Island of Control BEOL Island of Control Transistor Island of Control Supervisory Control Dynamic Scheduling CD Target CD Target Thickness Target Thickness Target RtR RtR RtR RtR FDC CD FDC CD FDC Thk FDC Thk Masking Etch Deposition Polish E-Test

29 29 A Completed APC Apps by Technology (Cum) P854 P856 P858 PX60 P1262 APC Applications B Completed APC Apps by Area (18) Polish 2 Etch 2 TF/Diff 4 Implant 1 Litho 9 # of Apps D Control Points Completed Proposed CD Reg Thickness Control Points Courtesy Intel C Polish 6 APC Proposed Apps (28) C4 3 Etch 2 TF/Diff 7 Litho 10

30 30 Post Exposure Bake Track Equipment Complexity is Increasing 10 Years of Product Evolution Single Zone Control Multi-Zone Control PEB Evolved from a Single Zone to Multi-Zone Control System Why?

31 31 PEB Hotplate Thermal Profile Optimization System Plate Type Specific Thermal Profile Modeling Engine AutoCal Baseline Thermal Profile Condition Input Input BakeTemp & OnView Offset Generator Engine Output OnWafer Technologies Offset Values Optimized for Both Within-Plate and Plate-to-Plate Thermal Profile Uniformities

32 32 PEB Temp Control Before After Target = 120 o C o C o C 16 plates, 120 ºC Target OnWafer Technologies

33 33 Spatial PEB/CD Distribution Correlation Plotting both the bake plate temperature trajectory and R 2 from temperature-cd correlation against bake time: Max R 2 during the transient heating period Continued high R 2 during steady state due to poor temperature control in single-zone plate design

34 Plate Type Specific Thermal Profile Modeling Engine 34 PEB Hotplate Critical Dimension Optimization System AutoCal Resist & Litho Cell Specific CD Modeling Engine AutoCD Input Input Offset Generator Engine Input Input Output Offset Values Optimized for Both Within-Plate and Plate-to-Plate Critical Dimensions Uniformities Baseline Thermal Profile Condition BakeTemp & OnView Baseline CD Profiles per Plate Customer Provided OnWafer Technologies

35 35 CDU Improvement AutoCD AutoCal POR Across Plate Plate to Plate AutoCal AutoCD POR OnWafer Technologies

36 36 The New Problem Wafer Litho Etch Processing Tool Poor Across-Wafer CD Uniformity How can we improve the across-wafer CDU? How much can we improve CDU?

37 37 Supervisory Control with Wireless Metrology Compensate for systematic spatial non-uniformities across the litho-etch sequence using all available control authority: Exposure step: die to die dose PEB step: temperature of multi-zone bake plate Etch: backside pressure of dual-zone He chuck Exposure PEB / Develop dose temperature He pressure Etch Optimizer Wafer-level CD Metrology Scatterometry/CDSEM

38 38 Present Status of Active CD Control Exposure Etch PA Bake PEB Etch Poly Etch System Etch Photoresist Removal Spin Develop HMDS PD Bake ADI ADI AEI AEI ELM ELM

39 39 On-wafer and in-line metrology in pattern transfer PA Bake Spin Exposure HMDS PEB Thin Thin Film Film Develop PD Bake I I (x, (x, y) y) T (t, (t, x, x, y) y) Etch Etch Poly Etch System OCD T (t, (t, x, x, y) y) V (t, (t, x, x, y) y) E (t, (t, x, x, y) y) Etch Photoresist Removal OCD OCD ELM ELM

40 40 CDU control has to incorporate many strategies PA Bake Spin Exposure HMDS PEB Thin Thin Film Film FB/FF FB/FF Control Control Develop PD Bake I I (x, (x, y) y) Optimal Pattern Pattern Design Design T (t, (t, x, x, y) y) FF FF control control Etch Etch Poly Etch System T (t, (t, x, x, y) y) V (t, (t, x, x, y) y) E (t, (t, x, x, y) y) FF/FB FF/FB Control, Control, chuck chuck diagnostics diagnostics Etch OCD FB FB Control Photoresist Removal OCD FB/FF Control OCD Profile Inversion FB FB Control ELM ELM

41 41 Outline Measuring Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with an emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process

42 42 Spatial Correlation Analysis Exhaustive poly-cd measurements (280/field):

43 43 Origin of Spatial Correlation Dependence - - Average Wafer Scaled Mask Errors Across-Field Systematic Variation = Across-Wafer Systematic Variation Polynomial Model

44 44 Origin of Spatial Correlation Dependence Within-die variation: - = Slit Scan Average Field Scaled Mask Errors Non-mask related across-field systematic variation Polynomial model of across-field systematic variation The shape of this model will be very similar to the shape of spatial correlation dependence.

45 45 Origin of Spatial Correlation Dependence By slicing the within-die variation, we can see where the origin of the spatial correlation plots ρ ( ) z * z n jk = ij ik /

46 46 Spatial Correlation Model Fit rudimentary linear model to spatial correlation curve extracted from empirical data: Ignore this part - distances to large for typical IC sub-circuit Characteristic correlation baseline r B X L, characteristic correlation length

47 47 Origin of Spatial Correlation Dependence The across-wafer variation impacts ρ B : Relative weights of field & wafer variation determine overall shape of spatial correlation curve

48 48 Calculation of Expected Effect Assuming n independent random variables with equal mean and variance, the variance of the sum of the n variables is: σ 2 tot = nσ 2 indv ( C ) σ = [ n + ρ( n)( n 1) ] σ 2ρ n 2 indv indv For ρ = 1, σ tot = nσ indv For ρ = 0, σ tot = n 1/2 σ indv Total potential improvement is factor of n 1/2 (i.e., for a 16-stage path, maximum total delay variation reduction is ~4x )

49 49 Monte Carlo Simulations Use canonical circuit of FO2 NAND-chain w/ stages separated by 100µm local interconnect, ST 90nm model: 100µm 100 µm Input Stage i Output Perform Monte Carlo simulations for various combinations of X L, ρ B, and σ/µ (gate length variation) Measure resulting circuit delays, extract normalized delay variation (3σ/µ )

50 50 Statistical Theory vs. Circuit Simulation Prediction of potential impact of spatial correlation using SPICE simulations on simple inverter chain: 1 Delay Variation, normalizedtocorr=1 case Theory SPICE simulations SPICE-based model Correlation Factor

51 51 Delay Variability vs. X L, ρ B, σ/µ 25 Normalized delay variability (3σ/µ) (%) X L scaling σ L scaling ρ B = 0.4 ρ B = % 20% 40% 60% 80% 100% ρ B = 0.0 Scaling factor Scaling gate length variation directly has most impact Reducing spatial correlation also reduces variability

52 52 Outline Measuring Variability Sensors and (wireless) metrology Controlling Variability Advanced Process Control (with en emphasis on wireless metrology) Evaluating the Impact of Variability on ICs Modeling a noisy manufacturing process

53 53 Coping with Variability in Semiconductor Manufacturing IC IC Design Robust Designs Novel Metrology / APC Manufacturing Process Development Error Budget Engineering Design for Controllability