High Speed Digital Design With ADS 2012 and SystemVue 2012

Transcription

1 High Speed Digital Design With ADS 2012 and SystemVue 2012 Colin Warwick Product Manager for High- Speed Digital Design at Agilent EEsof EDA

2 Proposed Agenda Help us to help you What is your present workflow and tool set? What are your most time-consuming steps? What are your most error-prone steps e.g. ones that cause rework? What insights are lacking that you need to guardband around? Design space exploration using ADS Pre-layout channel is Multi-Layer Model library of traces and vias. Gives you Tx, Rx settings, and inputs to constraint manager in third-party enterprise PCB tool (stackup, controlled impedance line, and via design parameters). Post-layout: Swap out pre-layout models with an EM-based model of the candidate, pre-manufacture artwork. Reuse the pre-layout Tx/Rx models and simulator set up. Verification and adjust. 2

3 Success Story: Why Did Cisco Choose ADS For Signal Integrity? Our systems include multi-gigabit per second chip-to-chip serial links across PCBs and backplanes. We selected ADS because it lets us couple simulations at the channel-, circuit-, and physical-levels with measured data from the instruments. The resulting workflow requires fewer respins of the physical prototypes. We get fewer unwanted surprises, and get to market quicker. -- Straty Argyrakis, CPP Integrity Engineer, Cisco Systems 3

4 HSD Strategic Intent Provide the industry s premier HSD EDA software. Integration of premier simulation technologies for microwave effects (which are inherent in the multigigabit/s regime), tuned to the needs of high speed digital designers. Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS/EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 4

5 Channel Simulator versus Traditional SPICE-like Transient Simulator 5

6 Why You Can t Use SPICE or Traditional IBIS Flow For Multigigabit/s SERDES Circuitry is too complex 10 s k transistors in the logic block Design space is too big Tx settings Channel design Rx setting = Thousands of simulations to find the optimum eye height/width Altera s Adaptive Equalizer Sub-gigabit/s yesterday Multigigabit/s today RGEN Reference edge generator. LPF HPF. RECT Rectifiers and integrators Comparators Digital controls and filter Go to and search for ADCE to see video D2A Digital to analog converter Source: Altera/Agilent joint webcast 6

7 Solution: Channel Simulator with IBIS AMI flow IBIS is Input/output Buffer Information Specification AMI is Algorithmic Modeling Interface IBIS Open Forum added the AMI flow an alternate to the traditional (SPICE-based) flow in IBIS version Agilent supports IBIS 5.1: Two Agilent experts serve on IBIS Open Forum SystemVue for AMI model builders (typically IC vendors) ADS for model users (both IC vendors and OEMs) 7

8 Traditional flow IBIS Compliant Transient Simulator (SPICE) versus AMI flow IBIS Compliant Channel Simulator Traditional *.ibs text file Traditional *.ibs text file plus ref. to Altera s Adaptive Equalizer Signal processing logic block Examples: Tx pre-emphasis Rx adaptive Eq Rx CDR RGEN Reference edge generator. LPF HPF. RECT Rectifiers and integrators Comparators Digital controls and filter Go to and search for ADCE to see video D2A Digital to analog converter *.ami header file (text) *.dll or *.so executable 8

9 What Does IBIS AMI Flow Offer? Portability & IP Protection: One IC model runs in many EDA tools, without the need for non-portable, proprietary encryption keys Interoperability: IC Vendor A IC Vendor B Performance: Ultralow BER contour in seconds not days Flexibility: Simulator has statistical and bit-by-bit ( time domain ) modes Models can have LTI and/or NLTV algorithms IC vendor can expose arbitrary model-parameters Optimization: Simulator can sweep modelspecific parameter quickly 9

10 SystemVue for IC Model Builders Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS, EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 10

11 For Model Builders: SystemVue AMI Modeling Kit 11

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13 Pre-standard Capability For Rack-to-rack Optoelectronic Links See W1714, W1713 product pages and brochure EN 13

14 ADS Channel Simulator for IC Model Users Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS, EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 14

15 For Model Users: Channel Simulator in ADS Transient Convolution Element Impulse response is calculated using a short, traditional transient simulation Bit by bit mode : Superposition of bits ISI Statistical mode : Statistical techniques 15

16 Example: Determine the Optimum Value of De-emphasis Optimum de-emphasis value: 5.6 db 16

17 Voutv_S, V Voutv, V Voutv_S, V Voutv, V Causal Models from S-Parameters Causal condition: Kramers-Kronig Relations: Understanding the Kramers-Kronig Relation Using A Pictorial Proof Our patented approach Non-rigorous Reference S-parameter Rigorous Reference S-parameter time, nsec time, nsec 17

18 Non-Causal Model Underestimates Eye Closure Incorrect Eye Measurements with Non-Causal Model Correct Eye Measurements with Causal Model 18

19 Measurement-hardened Methodology Validation and Refinement Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS/EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 19

20 Verified Versus Measurement 1) Time-domain Tyco TM XAUI Backplane Measured TDR waveform (blue) corresponds exactly to ADS simulation (red) 20

21 Verified Versus Measurement 2) Frequency-domain, time-domain round trip S-parameters from VNA FFT HDMI cable (7 meters): Eye diagram Measured (pink) and simulated (blue) response correspond exactly 21

22 Method BER floor in one minute simulation Applicability & Restrictions Netlists & IBIS traditional flow Computational expensive: Modified nodal analysis of Kirchoff s current laws IBIS AMI flow: Bit-by-bit ( timedomain ) mode Bit-by-bit superposition of impulse responses IBIS AMI flow: Statistical mode Statistical calculations based on impulse response ~10-3 ~10-6 ~10-18 or lower NLTV analog & channel NLTV Tx/Rx LTI analog & channel* *SystemVue and ADS can handle NLTV mid-channel repeaters using proprietary extension NLTV Tx/Rx LTI analog & channel LTI Tx/Rx Notes: LTI = linear and time invarient, NLTV = non-linear and/or time varying Red: Slow/bad; Yellow: in between/slightly restrictive; Green: Fast/good/flexible 22

23 ADS 2012 Supports IBIS 5.1 Plus Pre-standard Capabilities Mid-channel repeaters - electrical and optical LTI and NLTV ADS 2012 and SystemVue 2012 unique in the industry Agilent and Maxim plan to propose this to IBIS Open Forum in 2012 Advanced jitter parameters plus jitter stress tester UI Consistent with a pre-standard proposal known as BIRD 123 On-die s-parameters Consistent with a pre-standard proposal known as BIRDs

24 Mid-channel Repeaters and Rack-to-rack Opto 10 Gb/s and 25Gb/s can propagate: Only a few centimeters on FR4 board Electrical repeater Only a few meters on CAT5 twisted pair Optical fiber comms SystemVue 2012 and ADS 2012: Unique modeling based on IBIS AMI 24

25 Rx Optical Fiber Communication Transceiver 1101 Tx Electrical channel Multimode fiber Electrical channel Multimode fiber Vertical Cavity Surface Emitting Laser (VCSEL) Multi-Mode Fiber (MMF) Transimpedance Amplifier P-type, intrinsic, N-type photodiode (PIN diode) 25

26 Full Channel Optical Link Simulation Flow h AC1 h AC2 Tx AMI Tx Analog model Electrical channel In Analog model Optical AMI Out Analog model Electrical channel Rx Analog model Rx AMI Tx model Optical model Rx model Laser driver VCSEL fiber Photo detector TIA Amp 26

27 Accelerate Batch Jobs: 1000 s of Simulations for Design Space Exploration Regular ADS 2012 on workstation with Channel Simulator, Transient Simulator, and Simulation Manager features e.g. W2210 or W2211 bundle Server farm with one or more W2312 Transient Convolution Distributed Computing 8-packs 27

28 Simulation Manager Controls: W2312 Transient Convolution Distributed Computing 8-pack 28

29 W2500 Transient Convolution GT Update in ADS 2012 Capability: Massively parallel R, L, C, BSIM4 model evaluation with multithreading on hundreds of cores Benefit: Overall transient simulations is 7 faster than CPU alone weekend morning Windows and Linux-64 Supports GPU cards e.g. Tesla C2075 available from NVIDIA: Tesla C2075 image courtesy of NVIDIA 29

30 ADS Transient for traditional IBIS and netlist IC Model Users Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS/EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 30

31 Customer Experience With ADS TC Versus HSPICE Solved circuits from 6k transistors to 86k transistors ADS Transient Convolution: Faster than HSPICE in ALL cases DC solve much more robust than HSPICE Accuracy much better than HSPICE Multilayer models much better than HSPICE fieldsolver Post-processing much better than HSPICE/MATLAB In addition: HSPICE doesn t even support NVIDIA GPU acceleration Run times on customer s most challenging circuit: Stop time HSPICE ADS TC ADS TC GT 2 ns 192 hours (8 days) Speed up versus HSPICE 40 hours 10 hours ns No result 136 hours 34 hours??? 31

32 ADS Momentum for EM Models of Post-Layout Artwork Key Technology Investments IC Model Builder: SystemVue HSD Designer: ADS/EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 32

33 Post-layout Success Story: NVIDIA Company: High-end graphics subsystems for computers Problem: Trial-and-error board spins to eliminate signal integrity problems. No insight. Stressful, non-deterministic product schedules. Product delays and cancellations. Solution: Evaluate EM simulators for fast, post-layout verification and rapid what-if insight, and compelling field plots of fixes. Competitor tools took 3 days just for 4- ports. Momentum gives accurate results on our 18-port extractions in only 2.5 hours. -- Hany Fahmy, Director of Compliance and Regulatory Engineering, NVIDIA Corporation Results: Deterministic schedules. Millions saved. Whole projects saved from cancellation. New, differentiated service ( Virtual EMI Lab ) offered to help their customers be successful quickly 33

34 Allegro/APD to ADS Flow APD/Allegro Momentum Export Setup Select Critical Nets or Entire Layout Select Stackup Layers Cookie-cut Power and Ground Planes Portion Create Ports Export to.ads file Import in ADS Layout Sandbox Ground Ref Port Adjustments if required Check vs spec (e.g crosstalk), visualize, and fine tune Report fixes to physical designer who adjusts golden artwork in Allegro Verify Layout using 3-D Preview and Simulate 34

35 New! W2324 High Capacity Layout Pre-processor Imports ODB++ and IPC-2581 Offspring layout data from all board tools Critical net selection and cookie cutting Exports ADFI format files ADFI = ADS Design Flow Integration Aimed at large designs in Mentor board tools Still recommend our SKILL code library for Allegro flow Still recommend Zuken integration for CR-5000/CR-8000 Native ODB++ and Gerber/drill imports still recommended for small PCBs or IPC-2581 Offspring High Capacity Layout Pre- Processor 35

36 Which EM Solver Should I Use? Start here Geometry Type? Planar / Multilayer pkg/pcb MoM* *fields are solved full 3D, full wave 3D FEM Narrowband High Q Response/ Analysis Type? Broadband TDR impulse FDTD Intermediate FEM High # Ports Device Complexity/ Problem Size? High # Mesh Cells FDTD FEM I like Frequency Domain Personal Preference? Moderate Complexity I like Time Domain FDTD 36

37 ADS with Momentum for 3D Planar EM (Multilayer) Import and draw schematics and multilayer structures ADS Momentum Simulator 3D Planar EM Method of Moments Multilayer Structures+ Momentum is great for multilayered structures like PCBs and IC packages. But what about arbitrary 3D geometries like connectors, ball grid array breakouts, dielectric bricks, bond wires, shields,? 37

38 EMPro Adds EM for Arbitrary 3D Structures to ADS Design Flows Import and draw schematics and multilayer structures ADS Parameterized 3D EM Components EMPro Import and draw 3D structures ADS Layout Export Direct Simulation: No Export Required Momentum Simulator 3D Planar EM Method of Moments Multilayer Structures+ FEM Simulator 3DEM Finite Element Method Arbitrary Structures FDTD Simulator 3DEM Finite Difference, Time Domain Arbitrary Structures 38

39 Power Integrity Challenges IC: packaged die Chip has high i and high di/dt Ceramic cap Bulk cap On-pkg cap Die Voltage Regulation Module PCB 39

40 Power Integrity From a Tx Perspective Combine lumped element models with EM-based model of distributed PCB and package PDN to simulate ripple on VDD and VSS and synchronous switching noise on victim (Rx s signal line SIG) 40

41 ADS Momentum Gives EM Model of Heavily Perforated Power Distribution Networks SI/PI Analyzer handles: Grouping of many physical pins to one electrical port Net-based EM setup User identifies the nets, wizard selects minimum geometric objects required of EM Momentum generates s-parameter EM-based model and look alike symbol Wizard places the symbol into a schematic along with lumped elements VRM, CPM chip model, decoupling capacitors Ideally suited to 2 to 8 layer packages and boards, up to ~15cm Lowest layer count is typically associated with heaviest perforation Consumer electronics boards are typically this size range This segment is not well served by traditional PI tools 41

42 New Power Integrity Example JEDEC DDR3 Reference Design 240-pin UDIMM (unbuffered dual inline memory module) 6 layer board, single power plane for core and I/O buffers Example objectives: Provide impedance profiles for power/ground from DC to 500 MHz Investigate the impact of the decoupling capacitors 42

43 Product Directions: Integration of Field Solvers, Channel Simulator, and Transient Simulator 1. Usability tuned to HSD designers: large PCBs, large port counts, no assumption of background in microwave engineering 2. Channel Simulator: performance in executing the broadest range of IC models (IBIS AMI flow, model generation and model simulation) 3. Transient Convolution: performance in executing the broadest range of IC models (traditional IBIS flow and netlist models esp. HSPICE dialect netlist models) 4. Layout pre-processing and import for EM simulation 5. EM speed and capacity while maintaining appropriate accuracy 43

44 Usability S-parameter import Import port names and differential pairings Enhanced symbol generation New object navigator (enhanced Net Explorer) Via Designer DesignGuides and Compliance DesignKits migrated and integrated IBIS AMI, DDR2/3, PCIe, USB3, HDMI, SAS2, UHS2 Workshop and Classroom training 44

45 S-Parameter Import With Port Names 45

46 Flexible Symbol Generation 46

47 Enhanced Net Explorer for object navigation 47

48 Via Drawing Utility For accurate via modeling use a field solver even for pre-layout Via Drawing Utility automates via design ready for EM modeling in Momentum or FEM Explore the design space to generate constraints 48

49 All New Post-sales Classroom Training 49

50 More Info Product page Blog Self-guided workshop 50

51 Summary Our microwave expertise enables engineering in the multigigabit/s regime Integration of field solvers, Channel Simulator, Transient Convolution New! Mid-channel repeaters electrical and optical New! Channel Simulator, Transient Convolution for server farms New! High Capacity Layout Pre-Processor import artwork from Mentor tools PI of heavily perforated power/ground planes IC Model Builder: SystemVue HSD Designer: ADS/EMPro Physical Designer: Constraint-based tool e.g. Allegro, Expedition, CR-5000 etc. 51

52 Evaluate Our Products Today! agilent.com/find/signal-integrity ADS Core Layout Element SystemVue AMI Modeling Kit Transient Convolution Element Momentum G2 Element EMPro 52