All Programmable Technologies in Academia

Transcription

1 All Programmable Technologies in Academia Patrick Lysaght Senior Director

2 Agenda Xilinx: a Generation Ahead at 28nm The Industrial Internet ~ aka The Internet of Things Academia in Transition The Post-PC Era ~ The rising importance of embedded SOCs ZED: Zynq All programmable SoCs in Education Vivado Design Suite: a CAD suite for All Programmable Systems Page 2

3 A Generation Ahead at 28nm 28nm Xilinx at 28nm Portfolio: All Programmable FPGAs, SoCs and 3D ICs today Product: Extra node of performance, power and integration Productivity: Unmatched time to integration and implementation Page 3

4 The First System Optimized FPGAs FPGAs Scalable and System Optimized Architecture In production now Virtex-7 2x bandwidth & capacity, 35% power, SerDes Kintex-7 35% power, 45% faster logic, 2x DSP Artix-7 15% faster and $5-$10 lower system BOM Page 4

5 The First All Programmable 3D IC 7V2000T in production now 2x capacity, 2x bandwidth 4x more 28Gbps SerDes channels Only programmable homogeneous and heterogeneous 3D IC Volume ramped significantly in Q2, 2012 Page 5

6 Heterogeneous Integration Highest bandwidth FPGA with 278 Tb/s serial connectivity Electrically-isolated 28G transceivers for optimal signal integrity 28G Transceivers Homogeneous digital logic 28G Transceivers Different silicon processes Passive interposer Noise isolation 13G Transceivers Page 6

7 The First All Programmable SoC All devices in production now >25% ARM performance, 45% logic performance Highest productivity with Vivado HLS, ARM ecosystem All Major OS s supported and in use, 20 unique dev boards 350+ Customers actively designing,100+ partners Shipped 20,000 devices, 4000 development boards Page 7

8 The First SoC Strength Design Suite In production now Built from the ground up for the next decade of devices Now used for ~50% of 28nm designs, 100% of 3D ICs Delivering 4x productivity, turning months to weeks Page 8

9 Industry Mandates Programmable Imperative Programmable Systems Integration Insatiable Intelligent Bandwidth Page 9

10 Insatiable Intelligent Bandwidth Overall IP Traffic in exabytes per month: CAGR 29% We Will Soon Live in a 100 Gb World Page 10

11 IPV6 enables Dramatic M2M Growth IPv6-Capable Fixed Devices by Device type, in Millions, % CAGR in Machine-to-Machine traffic starting from 2012 Source: The Zettabyte Era, Cisco VNI: Forecast and Methodology,

12 The Internet of Things The internet of things was born between 2008 and 2009 when for the first time more things or objects were connected to the Internet than people Page 12

13 IOT an Internet dominated by networked things (not PCs, cell phones and tablets) The Internet of Things, is the general idea of things, especially everyday objects, that are readable, recognizable, locatable, addressable, and controllable via the Internet US National Intelligence Council Today, more than 20 percent of Internet traffic originates from noncomputing devices Predictions are that by 2020, as many as 50 billion machines will be plugged into the Internet Tremendous opportunities for multi-disciplinary teaching research in networked, embedded systems Page 13

14 Re-target Internet technologies for the benefit of big industry Source: Industrial Internet: Pushing the Boundaries of Minds and Machines Peter C Evans and Marco Annunziata, GE, November 26, 2012 Page 14

15 Scale up the vision on a grand scale and we get the Industrial Internet Source: Industrial Internet: Pushing the Boundaries of Minds and Machines Peter C Evans and Marco Annunziata, GE, November 26, 2012 Page 15

16 Illustrative Classes of Large Rotating Machines aka Big Things that Spin Source: Page 16 Industrial Internet: Pushing the Boundaries of Minds and Machines Peter C Evans and Marco Annunziata, GE, November 26, 2012

17 Motivation: The power of 1% Source: Industrial Internet: Pushing the Boundaries of Minds and Machines Peter C Evans and Marco Annunziata, GE, November 26, 2012 Page 17

18 The Merger of Industrial Revolution and Internet Revolution is a Complex Vision These opportunities have their doppelgängers Cyber security challenge to critical infrastructure Shortage of high-quality electricity for exploding data center demand Challenge of energy-efficient, high performance computing Especially high performance, embedded computing Immediate skills shortage From digital mechanical engineers to the data analytics scientists

19 Meanwhile, Academia is in Transition Prof John Hennessy, President of Stanford University, says that this change is due to the coming tsunami in educational technology Page 19

20 Agents of Change in Educational Technology New delivery formats edx, Coursera, Udacity Khan Academy, Codeacademy Broadband Internet Video everywhere YouTube E-Books Printing-on-Demand Search engines, etc Google, Wikipedia Social media Peer interaction & learning Open Source Software & textbooks Rapid curriculum expansion Especially in electronics & computing Page 20

21 Characteristics of The Post-PC ERA Universal mobility & connectivity The Internet of people is expanding to the Internet of things Computing has become an immersive, connected experience The Cloud underpins the mobile experience Embedded systems using systems-on-chip (SOC) are the key technology enabler of the Post-PC era They are drivers for major changes in engineering education Page 21

22 Enabling Post-PC ERA Engineering Education The PC is not dead it remains a powerful tool for more competent users But non-pc, consumer, electronic devices proliferate These devices have more specialized functionalities and more intuitive interfaces, for example smart phones, tablets, E-readers, HDTVs Embedded heterogeneous SOCs will drive of the Industrial Internet The curriculum in Electronics and Computer Engineering must change to meets the need to teach and research the challenges of engineering of SOCs in embedded systems Education for SOC Engineering is Vital Page 22

23 The Emerging Educational Challenges Coping with curriculum expansion driven by the rise of SOC technology in embedded systems in the post PC era Educating a generation of engineers in systems design and integration Educating students to understand and practice design re-use by using third-party IP and designing for re-use by creating their own re-usable IP Introducing High-level Synthesis from traditional software programming languages such as C, C++, SystemC Page 23

24 256 An Image Processing Example The Back Projection algorithm is used in variety of tomography applications, including CAT scanners Takes raw data from a scan at different angles and reconstructs an image based on that data From Datasets re-construct the image Page 24

25 Complete Design Consumes 2 Watts!!! ARM CoreSight Multi-core & Trace Debug NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches ACP m s s AXI4 interconnect s s 512 KB L2 Cache Snoop Control Unit (SCU) Timers / Counters General Interrupt Controller 256 KB On-Chip Memory DMA Configuration s m m AXI_DMA s m m AXI_DMA Memory AMBA Switches Accelerator Accelerator m s s HDMI Output AXI4 Lite interconnect m m m m Page 25

26 The Next Step: Design for Re-use ARM CoreSight Multi-core & Trace Debug NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches ACP m s s AXI4 interconnect s s 512 KB L2 Cache Snoop Control Unit (SCU) Timers / Counters General Interrupt Controller 256 KB On-Chip Memory DMA Configuration s m m AXI_DMA s m m AXI_DMA Memory AMBA Switches Accelerator Accelerator m s s HDMI Output AXI4 Lite interconnect m m m m These are the only new IP blocks in the design Page 26

27 Zynq-7000: ALL PROGRAMMABLE Platform for Post-PC Era Engineering Education Complete ARM -based Processing System Dual ARM Cortex -A9 MPCore, processor centric Integrated memory controllers & peripherals Fully autonomous to the Programmable Logic Tightly Integrated Programmable Logic Processing System Memory Interfaces 7 Series Programmable Logic Used to extend Processing System High performance ARM AXI interfaces Scalable density and performance Common Peripherals ARM Dual Cortex-A9 MPCore System Common Peripherals Custom Peripherals Flexible Array of I/O Common Accelerators Custom Accelerators Wide range of external multi-standard I/O High performance integrated serial transceivers Analog-to-Digital Converter inputs Best-in-class Embedded Processing and FPGA Technologies Page 27

28 Embedded Processing Leader for Post-PC Era SOC Designs ARM is the world s leading semiconductor IP company 800 processor licenses sold to more than 250 companies Over 20 billion ARM based chips shipped to date Two billion chips based on ARM RISC processor technology shipped during the second quarter of 2012* In contrast: Fewer than 100 million worldwide PC shipments in Q2 2012** * Source wwwarmcom ; ** Source Gartner Page 28

29 Zed Board: Zynq in Education and Development Low cost Zynq Evaluation and Development Kit (XC7Z020) Open source SW and IP Linux Eclipse based IDE Vivado HLS: C to FPGA Reference designs See zedboardorg Configurable levels of abstraction for the first-time, novice user, or the most advanced researcher Page 29

30 ZRobot Robot Example ZED board enabled Robot wirelessly controlled by an Android tablet with full video relay from ZRobot cameras to tablet display See the demo at the Xilinx Booth Page 30

31 Next Steps: ZRobot- Mark 2 Android App Remote Video Remote Control IE Webpage Robotics/Industrial RTOS Advanced Motor Control Linux Boa Webserver MJPEG Encoding OpenCV Computer Vision WIFI Access Point DDR 3 Car Wheels Processing System GE DDR Memory Controller AMBA Switches Programmable Logic Motor Control PWM Robotic ARMs Status LEDs GPIO APU Dual ARM Cortex-A9 Video Pre-processing Surround CCD Cameras SD Card SDIO AMBA Switches AXI4 Interconnect (Lite) Sensor Interfaces Sensor Farm S_AXI_HP 64 bit S_AXI_GP 32b bit Voice Processing Face Detection Lane Detection Computer Vision ZED Board Sensor & Peripheral Reference Designs Page 31 Copyright Xilinx

32 Xilinx Tools: From Vision to Deployment More Than Just Silicon A Comprehensive Platform Offering Page 32

33 Vivado Design Reuse: Hierarchical Design Flows Design Reuse Flow enables parallel implementation for Team Design Place & Route modules out of context from top level design Iterate on these modules without overhead of the full design Assemble results in context of top for exact preservation Package IP and reuse in new designs Reuse module as a pre-verified placed & routed result Page 33

34 Package Designs into System-Level IP for Reuse Standardized IP-XACT representation Vivado IP Integrator Memory Interface Source (C, RTL, IP, etc) Simulation Models Documentation Example Designs Test Bench IP Packager Xilinx IP 3 rd Party IP User IP PCIe Processor System Memory Interfaces Embedded Interconnect Display User IP Xilinx IP 3 rd Party IP Processing Datapath Share IP within your team, project or company 3 rd party IP delivered with a common look and feel Reuse IP at any point in the implementation process Source, placed, or placed and routed Reuse in different designs Reuse multiple times Page 34

35 Seamless IP Access and Customization Integrated IP catalog Powerful search capabilities Single-click access to IP functionality and collateral IP customization and generation Instant access to customization GUI Generate output products in project or remote directory Customize graphically or via Tcl Page 35

36 IP Packager: IP-XACT IEEE 1685 IP-XACT is an industry standard way to represent data about IP (meta-data) Port information Latency Configurable parameters Etc ASCII XML based Enables IP to be used in multiple vendor tools flows Page 36

37 Extensible IP Catalog: Add Packaged IP 1 Unzip IP to a local directory 2 Right-click on IP Catalog 3 Add directory to IP Catalog Page 37

38 Vivado IP Integrator A graphical design environment to enable rapid and accurate connection of complex IP Connections made at the interface level, not the individual signal level Automatic setting and propagation of IP parameters Automated generated of RTL Full support for arbitrary levels of design hierarchy Capable of processor-based or non-processor based design creation Tight integration with Vivado IP Packager flow for rapid IP and subsystem reuse Page 38

39 IP Integrator User Interface Hierarchy Support System Hierarchy View Interface Connections with Real-time DRCs TCL Console Page 39

40 Vivado High-Level Synthesis Design Flow Vivado HLS Starts at C C Function C Design C Specification C Verification C Test Bench C++ SystemC Produces RTL Architecture RTL Design C Synthesis Verilog VHDL SystemC RTL Verification C Wrapper Behavioral Verification Automates Flow RTL Verification IP Block Packaging Vivado IP Packager IP Packaging IP Package Vivado IP Integrator System Generator Page 40

41 Function versus Architecture Function Sequential void top ( int& dout1, int& dout2, int din1, int din2 ) { dout1 = din1+din2; dout2 = din1*din2; } Architecture Interface module top (dout1,dout2, din1,din2, ovld,ivld, clk,rst); output [31:0] dout1,dout2; output ovld; input [31:0] din1,din2; input ivld; input clk; input rst; reg [31:0] tmp,rdin1,rdin2; reg [31:0] dout1,dout2; reg ovld; reg [1:0] state, next_state; parameter RESET=2 b00,input=2 b01, CALC=2 b10,output=2 b11; Parallel Process endmodule Storage State machine clk) begin if (rst == 1 b1) state <= RESET; else state <= next_state; case (state) RST: next_state <= INPUT; INPUT: if (ivld == 1 b1) begin next_state <= CALC; rdin1 <= din1; rdin2 <= din2; end CALC: next_state <= OUTPUT; OUTPUT: next_state <= RESET; default: next_state <= RESET; endcase end OUTPUT RESET CALC rst INPUT Datapath clk) case (state) RST: begin dout1 <= 32 b0; dout2 <= 32 b0; ovld <= 0 b0; end CALC: begin dout1 <= din1+din2; din1 tmp <= din1*din2; end OUTPUT: begin dout2 <= tmp; ovld <= 1 b1; din2 end endcase ivld!ivld + * dout1 dout2 Page 41

42 Zynq and Vivado in Education Zynq All Programmable SoCs integrate state-of-the-art FPGA technology with best-in-class embedded CPUs to define a new class of ALL PROGRAMMABLE SOC devices which are ideal for teaching and research Vivado Design Suite is a new tool suite based on hierarchical, design re-use and high-level synthesis which has been designed for the next decade of programmable systems integration Teaching and researching the principles and practice of SOC engineering is now possible at the undergraduate and graduate levels Page 42

43 Promoting & Disseminating Best Practice The collective opportunity is huge but the complexity is nontrivial Especially for integrated multi-disciplinary teaching and research The individual contribution is crucial But the challenge can be overwhelming in isolation Effective collaboration and re-use are essential Not only to promote rapid dissemination But also rapid, widespread reuse of best practice The Internet is both the challenge and the opportunity Page 43

44 XUP s Charter Xilinx is a learning company We provide enabling technologies not vertical products so we are constantly learning from our customers and partners XUP adopts the same approach with our academic partners We strive to Provide the best possible enabling technology Identify and support best teaching and research practices Partner to disseminate best practice as widely as possible So please, give us your feedback We need your good ideas! Page 44

45 Closing Thoughts Don t believe everything you read on the Internet Abraham Lincoln, US President Page 45

46 Enabling Technologies for Academia Xilinx: All Programmable leadership at 28nm The Internet is both the opportunity and the challenge Zynq and Vivado 28nm will enable Professors and students to reach new levels of creativity and collaboration in their teaching and research Page 46

47 Thank You Page 47